Low-Power Logic Synthesis
Low-Power Logic Synthesis
Low-Power Logic Synthesis
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Dynamic <strong>Power</strong><br />
• Dynamic power of a CMOS gate<br />
1<br />
2<br />
Pavg = × CL<br />
× VDD<br />
× fp<br />
× N<br />
2<br />
– C L : Load capacitance<br />
– V DD : <strong>Power</strong> supply voltage<br />
– f p : Clock frequency<br />
– N: Average # of gate output transition (switching<br />
activity) per cycle<br />
NCHUCS 4
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