Low-Power Logic Synthesis
Low-Power Logic Synthesis Low-Power Logic Synthesis
Future Works • Accurate power estimation • Extension of methods to datapath components – Should be useful for pipelined ALU • Retiming circuit to optimize – Power – Speed • Testability issues NCHUCS 34
- Page 1 and 2: Low-Power Logic Synthesis 王 行
- Page 3 and 4: Power Model • Total power P total
- Page 5 and 6: Low-Power Design Techniques • Can
- Page 7 and 8: Multiple Supply Voltages • Basic
- Page 9 and 10: Circuit Level Techniques • Transi
- Page 11 and 12: Gate Reorganization • Transform o
- Page 13 and 14: Switching Activity Reduction • Ba
- Page 15 and 16: Precomputation • Proposed by M. A
- Page 17 and 18: Precomputation Logic— Version 1 x
- Page 19 and 20: Precomputation Logic— Version 2 x
- Page 21 and 22: Partition • Based on Shannon’s
- Page 23 and 24: An Example a b c d e f g h i j FFa
- Page 25 and 26: Data Synchronization • A retimed
- Page 27 and 28: Selecting Retimed Block • Goal -
- Page 29 and 30: Algorithm • Algorithm: Finding th
- Page 31 and 32: CKT NAME New Results Old Paper Refe
- Page 33: Conclusion • Many low-power desig
Future Works<br />
• Accurate power estimation<br />
• Extension of methods to datapath components<br />
– Should be useful for pipelined ALU<br />
• Retiming circuit to optimize<br />
– <strong>Power</strong><br />
– Speed<br />
• Testability issues<br />
NCHUCS 34
Change language