Low-Power Logic Synthesis
Low-Power Logic Synthesis Low-Power Logic Synthesis
A Comparison Precomputation Partition Retiming Area overhead Medium Large Small or No Critical path delay Unchanged More Unchanged or Less Critical path delay in previous stage Unchanged or More Unchanged Unchanged or More Testability Problem Yes No No NCHUCS 32
Conclusion • Many low-power design techniques have been developed – Most of them can be applied simultaneously – Ad hoc solutions usually work well in practice • A new logic level low-power synthesis is presented – The target is to reduce switching activities – The performance is better than previous methods in terms of • Reduction in switching activities • Area • Critical path delay NCHUCS 33
- Page 1 and 2: Low-Power Logic Synthesis 王 行
- Page 3 and 4: Power Model • Total power P total
- Page 5 and 6: Low-Power Design Techniques • Can
- Page 7 and 8: Multiple Supply Voltages • Basic
- Page 9 and 10: Circuit Level Techniques • Transi
- Page 11 and 12: Gate Reorganization • Transform o
- Page 13 and 14: Switching Activity Reduction • Ba
- Page 15 and 16: Precomputation • Proposed by M. A
- Page 17 and 18: Precomputation Logic— Version 1 x
- Page 19 and 20: Precomputation Logic— Version 2 x
- Page 21 and 22: Partition • Based on Shannon’s
- Page 23 and 24: An Example a b c d e f g h i j FFa
- Page 25 and 26: Data Synchronization • A retimed
- Page 27 and 28: Selecting Retimed Block • Goal -
- Page 29 and 30: Algorithm • Algorithm: Finding th
- Page 31: CKT NAME New Results Old Paper Refe
Conclusion<br />
• Many low-power design techniques have been developed<br />
– Most of them can be applied simultaneously<br />
– Ad hoc solutions usually work well in practice<br />
• A new logic level low-power synthesis is presented<br />
– The target is to reduce switching activities<br />
– The performance is better than previous methods in terms of<br />
• Reduction in switching activities<br />
• Area<br />
• Critical path delay<br />
NCHUCS 33
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