Low-Power Logic Synthesis
Low-Power Logic Synthesis Low-Power Logic Synthesis
Outline • Overview – Power model – Low-power design techniques • Low Power Logic Synthesis • Switching Activity Reduction – Sequential – Combinational • Retiming-Based Approach • Preliminary Results • Conclusion and Future Work NCHUCS 2
Power Model • Total power P total = P s + P d + P sc – P s : Static power due to leakage current – P d : Short circuit current due to switching transient – P d : Charge and discharge of capacitance • Dynamic power (P d ) is usually the dominant factor in CMOS technology NCHUCS 3
- Page 1: Low-Power Logic Synthesis 王 行
- Page 5 and 6: Low-Power Design Techniques • Can
- Page 7 and 8: Multiple Supply Voltages • Basic
- Page 9 and 10: Circuit Level Techniques • Transi
- Page 11 and 12: Gate Reorganization • Transform o
- Page 13 and 14: Switching Activity Reduction • Ba
- Page 15 and 16: Precomputation • Proposed by M. A
- Page 17 and 18: Precomputation Logic— Version 1 x
- Page 19 and 20: Precomputation Logic— Version 2 x
- Page 21 and 22: Partition • Based on Shannon’s
- Page 23 and 24: An Example a b c d e f g h i j FFa
- Page 25 and 26: Data Synchronization • A retimed
- Page 27 and 28: Selecting Retimed Block • Goal -
- Page 29 and 30: Algorithm • Algorithm: Finding th
- Page 31 and 32: CKT NAME New Results Old Paper Refe
- Page 33 and 34: Conclusion • Many low-power desig
<strong>Power</strong> Model<br />
• Total power<br />
P total<br />
= P s<br />
+ P d<br />
+ P sc<br />
– P s<br />
: Static power due to leakage current<br />
– P d<br />
: Short circuit current due to switching transient<br />
– P d<br />
: Charge and discharge of capacitance<br />
• Dynamic power (P d<br />
) is usually the dominant<br />
factor in CMOS technology<br />
NCHUCS 3
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