Low-Power Logic Synthesis
Low-Power Logic Synthesis
Low-Power Logic Synthesis
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Estimating Switching Activities<br />
• For a net y, let PS(y) be the probability of signal<br />
switching on a clock cycle<br />
PS(<br />
y)<br />
=<br />
=<br />
=<br />
Pr<br />
Pr<br />
Pr<br />
{ a transitionon y at time t}<br />
{<br />
t−1<br />
t<br />
y ⊕ y = 1}<br />
{ t−1<br />
t<br />
( 0) ( 1) ) t−1<br />
t<br />
y = ∧ y = ∨ ( y = 0) ∧ ( y = 1) )}<br />
• ESC(y, c): the expected amount of saved switching<br />
activity if net y is set to value c<br />
ESC(<br />
p)<br />
=<br />
Pr{ y = c}<br />
×∑z<br />
∈<br />
DCNS(<br />
p)<br />
PS(<br />
z)<br />
NCHUCS 28
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