Low-Power Logic Synthesis

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Selecting Load-Enabled Registers • Not all registers can be disabled – Inputs with fanout to other outputs can not be disabled – Ex: R 2 can not be disabled C FF yi R1 D G R2 yj NCHUCS 26
Selecting Retimed Block • Goal – Find a logic block which, when retimed, maximizes the reduced switching activities – The retimed block must be small in order to reduce the extra registers • In our experiment, at most 2 registers are need • Need to estimate the switching activities NCHUCS 27
Page 1 and 2: Low-Power Logic Synthesis 王行
Page 3 and 4: Power Model • Total power P total
Page 5 and 6: Low-Power Design Techniques • Can
Page 7 and 8: Multiple Supply Voltages • Basic
Page 9 and 10: Circuit Level Techniques • Transi
Page 11 and 12: Gate Reorganization • Transform o
Page 13 and 14: Switching Activity Reduction • Ba
Page 15 and 16: Precomputation • Proposed by M. A
Page 17 and 18: Precomputation Logic— Version 1 x
Page 19 and 20: Precomputation Logic— Version 2 x
Page 21 and 22: Partition • Based on Shannon’s
Page 23 and 24: An Example a b c d e f g h i j FFa
Page 25: Data Synchronization • A retimed
Page 29 and 30: Algorithm • Algorithm: Finding th
Page 31 and 32: CKT NAME New Results Old Paper Refe
Page 33 and 34: Conclusion • Many low-power desig

Low-Power Logic Synthesis

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