Low-Power Logic Synthesis
Low-Power Logic Synthesis Low-Power Logic Synthesis
A Retiming-Based Approach • Move a part of the functional block, rather than reproduce the block. – Assume the controlling value of gate G be c t-1 t-1 x x 1 1 t-1 R t t-1 x k 1 C y 1 x k t f t-1 t t-1 x k+1 G x k+1 t-1 R 2 x D t t-1 n x n t-1 C t-1 y 1 y m y 2 y 1 ≠c LE R 2 D FF t y 2 t y 1 t y m G f t NCHUCS 22
An Example a b c d e f g h i j FFa FFb FFc FFd FFe FFf FFg FFh FFi FFj a' b' c' d' e' f' g' h' i' j' l m n o k p q r z NCHUCS 23
- Page 1 and 2: Low-Power Logic Synthesis 王 行
- Page 3 and 4: Power Model • Total power P total
- Page 5 and 6: Low-Power Design Techniques • Can
- Page 7 and 8: Multiple Supply Voltages • Basic
- Page 9 and 10: Circuit Level Techniques • Transi
- Page 11 and 12: Gate Reorganization • Transform o
- Page 13 and 14: Switching Activity Reduction • Ba
- Page 15 and 16: Precomputation • Proposed by M. A
- Page 17 and 18: Precomputation Logic— Version 1 x
- Page 19 and 20: Precomputation Logic— Version 2 x
- Page 21: Partition • Based on Shannon’s
- Page 25 and 26: Data Synchronization • A retimed
- Page 27 and 28: Selecting Retimed Block • Goal -
- Page 29 and 30: Algorithm • Algorithm: Finding th
- Page 31 and 32: CKT NAME New Results Old Paper Refe
- Page 33 and 34: Conclusion • Many low-power desig
A Retiming-Based Approach<br />
• Move a part of the functional block, rather than<br />
reproduce the block.<br />
– Assume the controlling value of gate G be c<br />
t-1<br />
t-1<br />
x<br />
x 1<br />
1<br />
t-1 R t<br />
t-1<br />
x k 1 C y 1<br />
x k<br />
t<br />
f<br />
t-1<br />
t<br />
t-1<br />
x k+1<br />
G<br />
x k+1<br />
t-1 R 2<br />
x<br />
D<br />
t<br />
t-1<br />
n x n<br />
t-1<br />
C<br />
t-1<br />
y 1<br />
y m<br />
y 2<br />
y 1 ≠c<br />
LE<br />
R 2<br />
D<br />
FF<br />
t<br />
y 2<br />
t<br />
y 1<br />
t<br />
y m<br />
G<br />
f<br />
t<br />
NCHUCS 22
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