Low-Power Logic Synthesis

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Self-Timed Precomputation x 1 x 2 A R1 en x 3 x 4 R2 en B f x 5 g NCHUCS 20
Partition • Based on Shannon’s Expansion f ( x 1 , K, x ) = x f + n i x x i f i x i R 1 f xi MUX f x 1 … x n R 2 f xi x i NCHUCS 21
Page 1 and 2: Low-Power Logic Synthesis 王行
Page 3 and 4: Power Model • Total power P total
Page 5 and 6: Low-Power Design Techniques • Can
Page 7 and 8: Multiple Supply Voltages • Basic
Page 9 and 10: Circuit Level Techniques • Transi
Page 11 and 12: Gate Reorganization • Transform o
Page 13 and 14: Switching Activity Reduction • Ba
Page 15 and 16: Precomputation • Proposed by M. A
Page 17 and 18: Precomputation Logic— Version 1 x
Page 19: Precomputation Logic— Version 2 x
Page 23 and 24: An Example a b c d e f g h i j FFa
Page 25 and 26: Data Synchronization • A retimed
Page 27 and 28: Selecting Retimed Block • Goal -
Page 29 and 30: Algorithm • Algorithm: Finding th
Page 31 and 32: CKT NAME New Results Old Paper Refe
Page 33 and 34: Conclusion • Many low-power desig

Low-Power Logic Synthesis

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