Low-Power Logic Synthesis

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Basic Architecture Inputs Input Registers Controllable Input Registers Circuit Outputs Precomputaion <strong>Logic</strong> NCHUCS 16
Precomputation <strong>Logic</strong>— Version 1 x 1 2 ‧‧‧‧‧‧ x n ‧‧‧‧‧‧ R1 LE ‧‧‧‧‧‧ A R2 f g1 g2 FF FF g1=1 ⇒ f = 1 g2=1 ⇒ f = 0 NCHUCS 17
Page 1 and 2: Low-Power Logic Synthesis 王行
Page 3 and 4: Power Model • Total power P total
Page 5 and 6: Low-Power Design Techniques • Can
Page 7 and 8: Multiple Supply Voltages • Basic
Page 9 and 10: Circuit Level Techniques • Transi
Page 11 and 12: Gate Reorganization • Transform o
Page 13 and 14: Switching Activity Reduction • Ba
Page 15: Precomputation • Proposed by M. A
Page 19 and 20: Precomputation Logic— Version 2 x
Page 21 and 22: Partition • Based on Shannon’s
Page 23 and 24: An Example a b c d e f g h i j FFa
Page 25 and 26: Data Synchronization • A retimed
Page 27 and 28: Selecting Retimed Block • Goal -
Page 29 and 30: Algorithm • Algorithm: Finding th
Page 31 and 32: CKT NAME New Results Old Paper Refe
Page 33 and 34: Conclusion • Many low-power desig

Low-Power Logic Synthesis

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