Low-Power Logic Synthesis
Low-Power Logic Synthesis
Low-Power Logic Synthesis
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Precomputation<br />
• Proposed by M. Alidina et al (IEEE Tran. CAD,<br />
1994)<br />
– Synthesize a small “precomputation logic” in addition<br />
to the normal circuit<br />
– This block operated one cycle ahead of the normal<br />
functional circuit (“precomputatiuon”)<br />
– Part of the normal circuit is suspended when the<br />
precomputation condition is true<br />
– The precomputation block is decided by the ODC<br />
(Observability Don’t-Care) of the output function<br />
NCHUCS 15
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