Low-Power Logic Synthesis
Low-Power Logic Synthesis
Low-Power Logic Synthesis
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Example<br />
• Consider the following n-bit comparator<br />
a n–1 …a 0 b n–1 …b 0<br />
Comparator<br />
><br />
– The output is known if a n–1 b n–1 = 10 or 01<br />
– So at least 50% switching activities can be reduced if FFs<br />
corresponding to a n–2 …a 0 and b n–2 …b 0 can be disabled<br />
NCHUCS 14
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