Low-Power Logic Synthesis
Low-Power Logic Synthesis
Low-Power Logic Synthesis
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<strong>Low</strong>-<strong>Power</strong> <strong>Logic</strong> <strong>Synthesis</strong><br />
• Gate reorganization<br />
– Try to reduce capacitive load<br />
• Pass transistor logic<br />
• Reducing switching activities<br />
– Precomputation<br />
– Partition<br />
– Retiming<br />
NCHUCS 10
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