Low-Power Logic Synthesis

Low-Power Logic Synthesis
王 行 健
國 立 中 興 大 學
資 訊 科 學 系
Sying-Jyan Wang
Dept. Computer Science
National Chung-Hsing Univ.

Outline
• Overview
– Power model
– Low-power design techniques
• Low Power Logic Synthesis
• Switching Activity Reduction
– Sequential
– Combinational
• Retiming-Based Approach
• Preliminary Results
• Conclusion and Future Work
NCHUCS 2

Power Model
• Total power
P total
= P s
+ P d
+ P sc
– P s
: Static power due to leakage current
– P d
: Short circuit current due to switching transient
– P d
: Charge and discharge of capacitance
• Dynamic power (P d
) is usually the dominant
factor in CMOS technology
NCHUCS 3

Dynamic Power
• Dynamic power of a CMOS gate
1
2
Pavg = × CL
× VDD
× fp
× N
2
– C L : Load capacitance
– V DD : Power supply voltage
– f p : Clock frequency
– N: Average # of gate output transition (switching
activity) per cycle
NCHUCS 4

Low-Power Design Techniques
• Can be applied in any
level of the design process
• Various technologies can
be applied simultaneously
• Goal of optimization
– Reduce C L
– Reduce V DD
– Reduce N
– Clock frequency is NOT a
target
Architectural
RTL
Logic
Circuit
Physical
NCHUCS 5

Architecture Level Techniques
• Sleep Mode
– Deactivate non-operating functional units
– Require little hardware and design complexity
• Asynchronous data processing
– Conduct computation only when necessary
– Reduce switching activities
• Multiple power supply voltages
– Reduce power supply voltages without sacrificing performance
• Architecture transformation
NCHUCS 6

Multiple Supply Voltages
• Basic idea
– Slow down non-critical paths won’t increase cycle time
– So supply voltages of non-critical components can be reduced
• Implementation
– Architecture level: reduce power supply voltage for selected
modules
– Logic level: use dual power supply voltages
• Integer Linear Programming (ILP) technique is used to find the best
solution
• Problem: unmatched voltage swing may actually increase power
NCHUCS 7

RTL Techniques
• State encoding for FSM
– Assign adjacent codes to
neighboring states
– To reduce switching
activities in the
combinational logic
• Retiming
– Moving registers to reduce
glitches
00 11
S 1 S 2
S 3
01
NCHUCS 8

Circuit Level Techniques
• Transistor sizing
– Trade silicon area for speed and/or power
• Special flip-flop and latch
– Reduce power in storage elements
• Special logic family
– PPRPL
– PCFL3
– DyCML
– SCSL
– Etc.
NCHUCS 9

Low-Power Logic Synthesis
• Gate reorganization
– Try to reduce capacitive load
• Pass transistor logic
• Reducing switching activities
– Precomputation
– Partition
– Retiming
NCHUCS 10

Gate Reorganization
• Transform one logic circuit to another that
– Functionally equivalent
– Consume less power
• Apply at
– Logic synthesis
– Technology mapping
NCHUCS 11

Pass Transistor Logic
• Most logic synthesis systems are based on logic
gates
– Processed through Boolean equations
– Implemented with NAND/NOR gates
• Pass transistor logic can implement certain
complex Boolean function efficiently
• In some cases, the power consumption may be
reduced
NCHUCS 12

Switching Activity Reduction
• Basic idea
– Circuit output may be solely decided by part of the
circuit function
– Thus the remaining part of the circuit can be “turned off”
dynamically
• Implementation
– Extract part of the circuit so it can be computed first
• This part of the circuit is usually small
– “Freeze” registers that are not useful if the output is
decided
NCHUCS 13

Example
• Consider the following n-bit comparator
a n–1 …a 0 b n–1 …b 0
Comparator
>
– The output is known if a n–1 b n–1 = 10 or 01
– So at least 50% switching activities can be reduced if FFs
corresponding to a n–2 …a 0 and b n–2 …b 0 can be disabled
NCHUCS 14

Precomputation
• Proposed by M. Alidina et al (IEEE Tran. CAD,
1994)
– Synthesize a small “precomputation logic” in addition
to the normal circuit
– This block operated one cycle ahead of the normal
functional circuit (“precomputatiuon”)
– Part of the normal circuit is suspended when the
precomputation condition is true
– The precomputation block is decided by the ODC
(Observability Don’t-Care) of the output function
NCHUCS 15

Basic Architecture
Inputs
Input
Registers
Controllable
Input
Registers
Circuit
Outputs
Precomputaion
Logic
NCHUCS 16

Precomputation Logic— Version 1
x 1
2
‧‧‧‧‧‧
x n
‧‧‧‧‧‧
R1
LE
‧‧‧‧‧‧
A
R2
f
g1
g2
FF
FF
g1=1 ⇒ f = 1
g2=1 ⇒ f = 0
NCHUCS 17

Precomputation Logic— Version 1
• Idea
(Cnt’d)
– g1 implements ON-set of f
– g2 implements OFF-set of f
– R1 is disabled if the precomputation condition is TRUE.
• Problem:
– Delay is increased
– Performance is degraded.
NCHUCS 18

Precomputation Logic— Version 2
x 1
2
R1
‧‧‧‧
‧‧‧‧
‧‧‧‧
A
R3
f
x n
R2
LE
g1
g2
NCHUCS 19

Self-Timed
Precomputation
x 1
x 2
A
R1
en
x 3
x 4
R2
en
B
f
x 5
g
NCHUCS 20

Partition
• Based on Shannon’s Expansion
f ( x 1
, K,
x ) = x f +
n
i
x
x
i
f
i x i
R
1
f
xi
MUX
f
x 1 … x n
R
2
f
xi
x i
NCHUCS 21

A Retiming-Based Approach
• Move a part of the functional block, rather than
reproduce the block.
– Assume the controlling value of gate G be c
t-1
t-1
x
x 1
1
t-1 R t
t-1
x k 1 C y 1
x k
t
f
t-1
t
t-1
x k+1
G
x k+1
t-1 R 2
x
D
t
t-1
n x n
t-1
C
t-1
y 1
y m
y 2
y 1 ≠c
LE
R 2
D
FF
t
y 2
t
y 1
t
y m
G
f
t
NCHUCS 22

An Example
a
b
c
d
e
f
g
h
i
j
FFa
FFb
FFc
FFd
FFe
FFf
FFg
FFh
FFi
FFj
a'
b'
c'
d'
e'
f'
g'
h'
i'
j'
l
m
n
o
k
p
q
r
z
NCHUCS 23

NCHUCS 24
An Example
An Example (Cnt
(Cnt’d)
d)
a'
b'
c
d
e
f
g
h
i
j
z
k'
r
l
m
n
o
p
q
c'
d'
e'
f'
g'
h'
i'
j'
FFj
E
FFh
E
FFf
E
FFd
E
FFk
FFc
E
FFe
E
FFg
E
FFi
E
k

Data Synchronization
• A retimed block may create synchronization if its
internal node has fanout branches to other gates
• Need extra registers to solve this problem
t-1
x1
t-1
R C
yi t
xk
yj t
t-1
x1
t-1
xk
C
yi t-1
yj t-1
FF
FF
yi t
yj t
NCHUCS 25

Selecting Load-Enabled Registers
• Not all registers can be disabled
– Inputs with fanout to other outputs can not be disabled
– Ex: R 2 can not be disabled
C
FF
yi
R1
D
G
R2
yj
NCHUCS 26

Selecting Retimed Block
• Goal
– Find a logic block which, when retimed, maximizes the
reduced switching activities
– The retimed block must be small in order to reduce the
extra registers
• In our experiment, at most 2 registers are need
• Need to estimate the switching activities
NCHUCS 27

Estimating Switching Activities
• For a net y, let PS(y) be the probability of signal
switching on a clock cycle
PS(
y)
=
=
=
Pr
Pr
Pr
{ a transitionon y at time t}
{
t−1
t
y ⊕ y = 1}
{ t−1
t
( 0) ( 1) ) t−1
t
y = ∧ y = ∨ ( y = 0) ∧ ( y = 1) )}
• ESC(y, c): the expected amount of saved switching
activity if net y is set to value c
ESC(
p)
=
Pr{ y = c}
×∑z
∈
DCNS(
p)
PS(
z)
NCHUCS 28

Algorithm
• Algorithm: Finding the optimal C-cones to be retimed.
• Input: A netlist N and a given k.
• Output: A subset of N to be retimed.
• 1. MaxSaving←0, BestSolution←∅;
• 2. Construct the set of all controlling points CP;
• 3. for (i=1; i MaxSaving) {
• 9. MaxSaving← ES(P);
• 10. BestSolution←P;
}
}
}
11. Report CNS(P);
NCHUCS 29

Experimental Results
NCHUCS 30

CKT NAME New Results Old Paper Reference [1]
cmb 51.76% 22.60% 43.00%
cm138a 52.73% 72.40% 47.00%
majority 55.97% 41.00% 19.00%
cht 43.73% 30.30% 16.00%
cm150 51.27% 22.60% 43.00%
c 43.11% 29.30% 39.00% o
mux 50.20% 52.20% 22.00%
pcle 52.17% 60.40% 30.00%
pcler8 56.09% 41.20% 38.00%
unreg 48.87% 28.40% 18.00%
dalu 43.94% 34.00%
i2 59.40% 65.00%
sao2 41.51% 65.00%
spla 52.31% 41.00%
seq 54.02% 65.00%
apex2 68.40% 42.00%
cps 39.84% 41.00%
duke2 42.57% 23.00%
misex2 48.79% 15.00%
misex3 29.63% 19.00%
e64 66.03% 75.00%
Average 50.11% 40.04% 38.10%
NCHUCS 31

A Comparison
Precomputation Partition Retiming
Area overhead Medium Large Small or No
Critical path delay Unchanged More Unchanged or
Less
Critical path delay
in previous stage
Unchanged or
More
Unchanged
Unchanged or
More
Testability
Problem
Yes No No
NCHUCS 32

Conclusion
• Many low-power design techniques have been developed
– Most of them can be applied simultaneously
– Ad hoc solutions usually work well in practice
• A new logic level low-power synthesis is presented
– The target is to reduce switching activities
– The performance is better than previous methods in terms of
• Reduction in switching activities
• Area
• Critical path delay
NCHUCS 33

Future Works
• Accurate power estimation
• Extension of methods to datapath components
– Should be useful for pipelined ALU
• Retiming circuit to optimize
– Power
– Speed
• Testability issues
NCHUCS 34