lecture 10 11 12 class room slides - BITS Pilani
lecture 10 11 12 class room slides - BITS Pilani
lecture 10 11 12 class room slides - BITS Pilani
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HARDWARE SOFTWARE<br />
CO-DESIGN<br />
<strong>BITS</strong> <strong>Pilani</strong><br />
Dubai Campus<br />
Dr Jagadish Nayak
Specification Languages<br />
<strong>BITS</strong> <strong>Pilani</strong><br />
Dubai Campus
Introduction<br />
۞The conceptual models we have seen could be used to<br />
understand, organize and define the system functionality<br />
۞These models are theoretical concept<br />
۞These models are captured using specification<br />
languages to bring the model to reality.<br />
۞Designer need to describe the conceptual view in terms<br />
of an executable specification language, which is<br />
capable of capturing the functionality of the system in a<br />
machine readable and simulatable form<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Introduction<br />
This allows the designer to verify the correctness of the<br />
systems intended functionality.<br />
Second advantage of this is , direct input to the synthesis<br />
tools. (easiness in system implementation)<br />
Specification languages can also serves as<br />
comprehensive documentation, providing an<br />
unambiguous description of the systems intended<br />
functionality.<br />
It also serves as a good medium for the exchange of<br />
design information among various users and tools. This<br />
reduces the problem associated with the system<br />
integration.<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Introduction<br />
Goal of any language is to capture the conceptual view of<br />
the system with a minimum effort on the part of the<br />
designer.<br />
– Eg : C++ most useful for capturing Object Oriented conceptual<br />
model. HCFSM can be better implemented using Statecharts<br />
language.<br />
Languages must suitable the model characteristics<br />
Direct capture of the conceptual model is possible , when<br />
one- to-one correlation between model and language<br />
construct is established.<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Characteristics of Conceptual<br />
Model<br />
͏ Concurrency<br />
͏ State Transitions<br />
͏ Hierarchy<br />
͏ Programming constructs<br />
͏ Behavioral completion<br />
͏ Communication<br />
͏ Synchronization<br />
͏ Exceptional handling<br />
͏ Non-determinism<br />
͏ Timing<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Concurrency<br />
♠ Behavior:<br />
a chunk of system functionality<br />
– e.g. process, procedure, state-machine<br />
♠ System often conceptualized as set of concurrent behaviors<br />
♠ Concurrency can exist at different abstraction levels:<br />
– Job-level<br />
– Task-level<br />
– Statement-level<br />
– Operation-level<br />
– Bit-level<br />
♠ Two types of concurrency within a behavior<br />
– Data-driven, Control-driven<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Concurrency<br />
Job-level : Parallel execution of several jobs by means of mechanism<br />
such as multiprogramming multi processing and time sharing.<br />
Task level : simultaneous execution of several tasks that comprise of<br />
job. Each task is a behavior and most of the systems are<br />
conceptualized in this level.<br />
Statement level : Parallel execution of statements in the task<br />
(execution of loops on a vector machines)<br />
Operation level : Concurrent operation of several operations in the<br />
system. (Ex: Addition operation may be concurrently executed with a<br />
multiplication operation. Processors, filters and DSPs)<br />
Bit level granularity : bitwise computation performed inside the ALU<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Data-driven concurrency<br />
♠ Operations execute when input data is available<br />
♠ Execution order determined by data dependencies<br />
1: Q = A + B<br />
2: Y = X + P<br />
3: P = (C − D) * Q<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Control-driven concurrency<br />
♠ Control thread : set of operations executed sequentially<br />
♠ Concurrency represented by multiple control threads<br />
Fork-join statement<br />
sequential behavior X<br />
begin<br />
Q();<br />
fork<br />
R();<br />
end behavior X;<br />
A(); B(); C(); join;<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Control-driven concurrency<br />
Process statement<br />
concurrent behavior X<br />
begin<br />
process A();<br />
process B();<br />
process C();<br />
end behavior X;<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Control-driven concurrency<br />
(explicitly specified statement level)<br />
♠ Special constructs for executing several statements in<br />
parallel.<br />
Example: parallel compound statement in HardwareC<br />
<<br />
x=b+c<br />
y=p-q<br />
><br />
♠ In the above statement computations associated with the<br />
assignments x and y are to be performed simultaneously<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Control-driven concurrency<br />
(implicitly specified statement level)<br />
♠ Updating of values scheduled to occur in future.<br />
s
State transitions<br />
♠ A system has various modes of behaviour<br />
Ex: Traffic light controller might have different modes<br />
– for day and night operations<br />
– for manual and automatic functioning<br />
– for status of the traffic light itself<br />
♠ Transition between these modes some times may be<br />
unstructured as opposed to the linear sequencing<br />
♠ Goto statements are example for such arbitrary transitions.<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
State transitions<br />
♠ In the above figure transition sequencing between modes P<br />
Q R S and T determined solely by certain condition<br />
♠ For N state machine , there are N N possible transitions<br />
between them.<br />
♠ Transition between certain modes can be triggered by the<br />
detection of certain events or certain conditions.<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Hierarchy<br />
♠ Required for managing system complexity<br />
o Allows system modeller to focus on one subsystem at a time<br />
o Enhances comprehension of system functionality<br />
o Scoping mechanism for objects like types and variables<br />
Two types of hierarchy<br />
• Structural hierarchy<br />
• Behavioural hierarchy<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Structural hierarchy<br />
♠ System represented as set of interconnected<br />
components<br />
♠ Interconnections between components represent wires<br />
♠ Several levels: systems, chips, RT-components, gates<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Behavioural hierarchy<br />
♠ Ability to successively decompose behaviour into subbehaviors.<br />
♠ Concurrent decomposition<br />
– Fork-join<br />
– Process<br />
♠ Sequential decomposition<br />
– Procedure<br />
– State-machine<br />
behavior P<br />
variable x, y;<br />
begin<br />
Q(x) ;<br />
R(y) ;<br />
end behavior P;<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Programming constructs<br />
♠ Some behaviors easily conceptualized as sequential<br />
algorithms<br />
♠ Wide variety of constructs available<br />
– Assignment, branching, iteration, subprograms,<br />
– recursion, complex data types (records, lists)<br />
type<br />
buffer_type is array (1 to <strong>10</strong>) of integer;<br />
variable buf : buffer_type;<br />
variable i, j : integer;<br />
for i = 1 to <strong>10</strong><br />
for j = i to i<br />
if (buf(i) > buf(j)) then<br />
SWAP(buf(i), buf(j));<br />
end if;<br />
end for;<br />
end for;<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Behavioral completion<br />
♠ Behavior completes when all computations performed<br />
♠ Advantages<br />
– Behavior can be viewed without inter-level transitions<br />
– Allows natural decomposition into sequential subbehaviors<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Communication<br />
♠ Concurrent behaviors exchange data<br />
♠ Shared-memory model<br />
– Sender updates common medium<br />
– Persistent, Non-persistent<br />
♠ Message-passing model<br />
– Data sent over abstract channels<br />
– Unidirectional / bidirectional<br />
– Point-to-point / multiway<br />
– Blocking / non-blocking<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Synchronization<br />
♠ Concurrent behaviours execute at different speeds<br />
♠ Synchronization required when<br />
‣Data exchanged between behaviours<br />
‣Different activities must be performed simultaneously<br />
♠ Two types of synchronization mechanisms<br />
‣Control-dependent<br />
‣Data-dependent<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Control-dependent<br />
synchronization<br />
♠ Synchronization based on control structure of behaviour<br />
Fork-join<br />
behavior X<br />
begin<br />
Q();<br />
fork A(); B(); C(); join;<br />
R();<br />
end behavior X;<br />
Behavior X forked into<br />
three concurrent behavior<br />
These distinct execution<br />
stream of behavior X is<br />
synchronized by join<br />
statement , this ensures<br />
that A,B,C is complete<br />
before R<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Control-dependent synchronization<br />
(initialization or Reset)<br />
♠ Processes are synchronized to their initial state either the first<br />
time the system is initialized (HDLs) or during the execution<br />
of the process.<br />
♠ Consider following state chart<br />
Event e associated with the<br />
transition arc that reenters the<br />
boundary of ABC, is designated to<br />
synchronize all the orthogonal<br />
states A,B,C into their default sub<br />
states.<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Control-dependent synchronization<br />
(initialization or Reset)<br />
Event e causes B to initialize to its<br />
default sub state B1 and at the<br />
same time transitioning A from A1<br />
to A2<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Data-dependent<br />
synchronization<br />
Synchronization based on communication of data between<br />
behaviours (shared memory or message passing)<br />
Synchronization by<br />
common event<br />
Synchronization by<br />
status detection<br />
Synchronization by<br />
common variable<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Exception handling<br />
♠ Occurrence of event terminates current computation<br />
♠ Control transferred to appropriate next mode<br />
♠ Example of exceptions: interrupts, resets<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Non – Determinism<br />
♠ Options for particular transition or computations to be<br />
performed in the system.<br />
♠ The designer can specify multiple options.<br />
♠ During the simulation of the specification one of the several<br />
choices are selected arbitrarily<br />
♠ There are two type<br />
Selection non determinism<br />
if (x) then<br />
do EITHER a OR b<br />
end if<br />
Ordering non determinism<br />
if (x) then<br />
do both a and b<br />
end if<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
Timing<br />
♠ Required to represent real world implementations<br />
♠ Functional timing: affects simulation of system specication<br />
– wait for 200 ns;<br />
– A
Embedded system specification<br />
♠ Embedded system: behavior defined by interaction with<br />
environment<br />
♠ Essential characteristics<br />
State-transitions , Exceptions , Behavioural hierarchy<br />
Concurrency, Programming constructs, Behavioural completion<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
VHDL<br />
☻VHSIC Hardware Description Language<br />
☻Developed in 1989, by Defense and standardized by IEEE<br />
☻Assists in the development, documentation and exchange of<br />
design.<br />
☻Wide range of tools are available<br />
☻There is design entity, which is single portion of a larger<br />
design, and performs specific function and has well defined<br />
input and outputs.<br />
☻Functionality of these entity can be defined using<br />
programming statements, dataflow, structure or combination<br />
of thereof.<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
VHDL<br />
Characteristics supported<br />
☺Behavioral hierarchy : single level of processes<br />
☺Structural hierarchy : nested blocks and component<br />
instantiations<br />
☺Concurrency : task-level (process), statement-level (signal<br />
assignment)<br />
☺Programming constructs<br />
☺Communication : shared-memory using global signals<br />
☺Synchronization : wait on and wait until statements<br />
☺Timing : wait for statement, after clause in assignments<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
VHDL (Structural Hierarchy)<br />
entity Counter_E is<br />
port(clk : in bit ; cnt : out integer);<br />
End counter_E;<br />
architecture Counter_struct of Counter_E is<br />
component Reg_E<br />
port(d : in integer; clk: bit; o: out integer; clear : in bit);<br />
end component;<br />
component Add_E<br />
port(a,b : in integer; o: out integer)<br />
end component<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
VHDL (Structural Hierarchy)<br />
component Cmp_E<br />
port(i0,i1 : in integer; o : out bit)<br />
end component<br />
signal one : integer :=1;<br />
signal nine : integer :=9;<br />
signal cnt_in,cnt_out, add_out : integer;<br />
signal clear bit;<br />
<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus
VHDL (Structural Hierarchy)<br />
Begin<br />
Conreg : Reg_E<br />
port map(cnt_in, clk, cnt_out, clear);<br />
Adder: Add_E<br />
port map(cnt_out, one, add_out)<br />
Comparator : cmp_E<br />
port map(nine, cnt_in, clear);<br />
cnt