lecture 10 11 12 class room slides - BITS Pilani

HARDWARE SOFTWARE 

CO-DESIGN 

BITS Pilani 

Dubai Campus 

Dr Jagadish Nayak

Specification Languages 

BITS Pilani 

Dubai Campus

Introduction 

۞The conceptual models we have seen could be used to 

understand, organize and define the system functionality 

۞These models are theoretical concept 

۞These models are captured using specification 

languages to bring the model to reality. 

۞Designer need to describe the conceptual view in terms 

of an executable specification language, which is 

capable of capturing the functionality of the system in a 

machine readable and simulatable form 

BITS Pilani, Dubai Campus

Introduction 

This allows the designer to verify the correctness of the 

systems intended functionality. 

Second advantage of this is , direct input to the synthesis 

tools. (easiness in system implementation) 

Specification languages can also serves as 

comprehensive documentation, providing an 

unambiguous description of the systems intended 

functionality. 

It also serves as a good medium for the exchange of 

design information among various users and tools. This 

reduces the problem associated with the system 

integration. 


Introduction 

Goal of any language is to capture the conceptual view of 

the system with a minimum effort on the part of the 

designer. 

– Eg : C++ most useful for capturing Object Oriented conceptual 

model. HCFSM can be better implemented using Statecharts 

language. 

Languages must suitable the model characteristics 

Direct capture of the conceptual model is possible , when 

one- to-one correlation between model and language 

construct is established. 


Characteristics of Conceptual 

Model 

͏ Concurrency 

͏ State Transitions 

͏ Hierarchy 

͏ Programming constructs 

͏ Behavioral completion 

͏ Communication 

͏ Synchronization 

͏ Exceptional handling 

͏ Non-determinism 

͏ Timing 


Concurrency 

♠ Behavior: 

a chunk of system functionality 

– e.g. process, procedure, state-machine 

♠ System often conceptualized as set of concurrent behaviors 

♠ Concurrency can exist at different abstraction levels: 

– Job-level 

– Task-level 

– Statement-level 

– Operation-level 

– Bit-level 

♠ Two types of concurrency within a behavior 

– Data-driven, Control-driven 


Concurrency 

Job-level : Parallel execution of several jobs by means of mechanism 

such as multiprogramming multi processing and time sharing. 

Task level : simultaneous execution of several tasks that comprise of 

job. Each task is a behavior and most of the systems are 

conceptualized in this level. 

Statement level : Parallel execution of statements in the task 

(execution of loops on a vector machines) 

Operation level : Concurrent operation of several operations in the 

system. (Ex: Addition operation may be concurrently executed with a 

multiplication operation. Processors, filters and DSPs) 

Bit level granularity : bitwise computation performed inside the ALU 


Data-driven concurrency 

♠ Operations execute when input data is available 

♠ Execution order determined by data dependencies 

1: Q = A + B 

2: Y = X + P 

3: P = (C − D) * Q 


Control-driven concurrency 

♠ Control thread : set of operations executed sequentially 

♠ Concurrency represented by multiple control threads 

Fork-join statement 

sequential behavior X 

begin 

Q(); 

fork 

R(); 

end behavior X; 

A(); B(); C(); join; 



Process statement 

concurrent behavior X 

begin 

process A(); 

process B(); 

process C(); 




(explicitly specified statement level) 

♠ Special constructs for executing several statements in 

parallel. 

Example: parallel compound statement in HardwareC 

< 

x=b+c 

y=p-q 

> 

♠ In the above statement computations associated with the 

assignments x and y are to be performed simultaneously 



(implicitly specified statement level) 

♠ Updating of values scheduled to occur in future. 

s

State transitions 

♠ A system has various modes of behaviour 

Ex: Traffic light controller might have different modes 

– for day and night operations 

– for manual and automatic functioning 

– for status of the traffic light itself 

♠ Transition between these modes some times may be 

unstructured as opposed to the linear sequencing 

♠ Goto statements are example for such arbitrary transitions. 


State transitions 

♠ In the above figure transition sequencing between modes P 

Q R S and T determined solely by certain condition 

♠ For N state machine , there are N N possible transitions 

between them. 

♠ Transition between certain modes can be triggered by the 

detection of certain events or certain conditions. 


Hierarchy 

♠ Required for managing system complexity 

o Allows system modeller to focus on one subsystem at a time 

o Enhances comprehension of system functionality 

o Scoping mechanism for objects like types and variables 

Two types of hierarchy 

• Structural hierarchy 

• Behavioural hierarchy 


Structural hierarchy 

♠ System represented as set of interconnected 

components 

♠ Interconnections between components represent wires 

♠ Several levels: systems, chips, RT-components, gates 


Behavioural hierarchy 

♠ Ability to successively decompose behaviour into subbehaviors. 

♠ Concurrent decomposition 

– Fork-join 

– Process 

♠ Sequential decomposition 

– Procedure 

– State-machine 

behavior P 

variable x, y; 

begin 

Q(x) ; 

R(y) ; 

end behavior P; 


Programming constructs 

♠ Some behaviors easily conceptualized as sequential 

algorithms 

♠ Wide variety of constructs available 

– Assignment, branching, iteration, subprograms, 

– recursion, complex data types (records, lists) 

type 

buffer_type is array (1 to 10) of integer; 

variable buf : buffer_type; 

variable i, j : integer; 

for i = 1 to 10 

for j = i to i 

if (buf(i) > buf(j)) then 

SWAP(buf(i), buf(j)); 

end if; 

end for; 

end for; 


Behavioral completion 

♠ Behavior completes when all computations performed 

♠ Advantages 

– Behavior can be viewed without inter-level transitions 

– Allows natural decomposition into sequential subbehaviors 


Communication 

♠ Concurrent behaviors exchange data 

♠ Shared-memory model 

– Sender updates common medium 

– Persistent, Non-persistent 

♠ Message-passing model 

– Data sent over abstract channels 

– Unidirectional / bidirectional 

– Point-to-point / multiway 

– Blocking / non-blocking 


Synchronization 

♠ Concurrent behaviours execute at different speeds 

♠ Synchronization required when 

‣Data exchanged between behaviours 

‣Different activities must be performed simultaneously 

♠ Two types of synchronization mechanisms 

‣Control-dependent 

‣Data-dependent 


Control-dependent 

synchronization 

♠ Synchronization based on control structure of behaviour 

Fork-join 

behavior X 

begin 

Q(); 

fork A(); B(); C(); join; 

R(); 


Behavior X forked into 

three concurrent behavior 

These distinct execution 

stream of behavior X is 

synchronized by join 

statement , this ensures 

that A,B,C is complete 

before R 


Control-dependent synchronization 

(initialization or Reset) 

♠ Processes are synchronized to their initial state either the first 

time the system is initialized (HDLs) or during the execution 

of the process. 

♠ Consider following state chart 

Event e associated with the 

transition arc that reenters the 

boundary of ABC, is designated to 

synchronize all the orthogonal 

states A,B,C into their default sub 

states. 


Control-dependent synchronization 

(initialization or Reset) 

Event e causes B to initialize to its 

default sub state B1 and at the 

same time transitioning A from A1 

to A2 


Data-dependent 

synchronization 

Synchronization based on communication of data between 

behaviours (shared memory or message passing) 

Synchronization by 

common event 


status detection 


common variable 


Exception handling 

♠ Occurrence of event terminates current computation 

♠ Control transferred to appropriate next mode 

♠ Example of exceptions: interrupts, resets 


Non – Determinism 

♠ Options for particular transition or computations to be 

performed in the system. 

♠ The designer can specify multiple options. 

♠ During the simulation of the specification one of the several 

choices are selected arbitrarily 

♠ There are two type 

Selection non determinism 

if (x) then 

do EITHER a OR b 

end if 

Ordering non determinism 

if (x) then 

do both a and b 

end if 


Timing 

♠ Required to represent real world implementations 

♠ Functional timing: affects simulation of system specication 

– wait for 200 ns; 

– A

Embedded system specification 

♠ Embedded system: behavior defined by interaction with 

environment 

♠ Essential characteristics 

State-transitions , Exceptions , Behavioural hierarchy 

Concurrency, Programming constructs, Behavioural completion 


VHDL 

☻VHSIC Hardware Description Language 

☻Developed in 1989, by Defense and standardized by IEEE 

☻Assists in the development, documentation and exchange of 

design. 

☻Wide range of tools are available 

☻There is design entity, which is single portion of a larger 

design, and performs specific function and has well defined 

input and outputs. 

☻Functionality of these entity can be defined using 

programming statements, dataflow, structure or combination 

of thereof. 


VHDL 

Characteristics supported 

☺Behavioral hierarchy : single level of processes 

☺Structural hierarchy : nested blocks and component 

instantiations 

☺Concurrency : task-level (process), statement-level (signal 

assignment) 

☺Programming constructs 

☺Communication : shared-memory using global signals 

☺Synchronization : wait on and wait until statements 

☺Timing : wait for statement, after clause in assignments 


VHDL (Structural Hierarchy) 

entity Counter_E is 

port(clk : in bit ; cnt : out integer); 

End counter_E; 

architecture Counter_struct of Counter_E is 

component Reg_E 

port(d : in integer; clk: bit; o: out integer; clear : in bit); 

end component; 

component Add_E 

port(a,b : in integer; o: out integer) 

end component 



component Cmp_E 

port(i0,i1 : in integer; o : out bit) 

end component 

signal one : integer :=1; 

signal nine : integer :=9; 

signal cnt_in,cnt_out, add_out : integer; 

signal clear bit; 



Begin 

Conreg : Reg_E 

port map(cnt_in, clk, cnt_out, clear); 

Adder: Add_E 

port map(cnt_out, one, add_out) 

Comparator : cmp_E 

port map(nine, cnt_in, clear); 

cnt

lecture 10 11 12 class room slides - BITS Pilani

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