Full-Custom Design Flow in LaRC (Cadence)

Full-Custom Design Flow in 

LaRC (Cadence) 

M.J. Hsiao 08/28/2002

Outlines 

Related files 

How to startup 

Create a new cell 

Recommended setup 

Start drawing 

Some tricks 

Instance a cell (Pcell) 

Contacts, pins, lables 

On-line checking 

2

Outlines 

Off-line checking 

Command file 

Stream out 

Schematic file 

Execution 

Outputs 

Make a Pcell 

Hspice simulation 

Some commands 

Execution and outputs 

Waveform viewer 

Resources 

3

Related files 

All files are placed at ~cic/Techfile/ 

Including 

Technology file (*.tf) 

Dracula cmdfiles (*.lvs *.drc *.lpe *.com) 

SPICE models (*.l) 

Pcell library (Macro cells for layout). 

I/O Pads 

Documents 

display.drf (rules for displaying layers) 

diva*.rul (For on-line checking) 

4

Related files 

Prefix all directories with ~cic/Techfile/ 

0.35um in directory tsmc035/ 


TF, display.drf, diva*.rul: techfile/ 

Dracula cmdfiles: cmdfiles/ 

SPICE model: models/ 

Pcell library: 0X5pcell/ 

Documents: doc/ 

5

Related files 


For Mixed-signal purpose 

MixedSignal/ 

For RF purpose 

RF/ 

Then all directories are the same as previous. 

6


Create a startup directory and copy the 

display.drf to this directory (differs by 

technology). 

Start “icfb &” then File New Library 

Fill in the library name and 

technology file 

7


Copy *.rul to the diretory 

startup_directory/library_name for on-line 

checking 

Add Pcell library (very powerful) 

Tools Library Path Editor 

Choose a name for it and fill the path of Pcell 

library 

In Library Path Editor, Files Save 

Or you can directly modify the file 

startup_directory/cds.lib to add it 

8

Create a new cell 

File New Cellview 

Choose your preferred cell name and the 

library that it belongs to. 

For creating layout view 

View name = layout 

Tool = Virtuoso 

For creating schematic view 

View name = schematic 

Tool = Composer-Schematic 

Manage your designs by: 

Tools Library Manager 

9


In Virtuoso, Options Display 


is shown in figure, 

including: 

• Display Levels 

• Grid Controls 

• Snap Modes 

After the setup is 

done, remember save 

to file. 

10


In Virtuoso, Options Layout Editor 

Uncheck 

“Auto Set Reference Point” 

and “Gravity on”. 

Remember save to file. 

11


Upper row shows the position and current command 

Lower row shows the hint and actions of buttons 

Pick desired layer at LSW 

12


All hotkeys all shown in the menus 

Frequently used hotkeys 

r 

Draw rectangle 

u 

Undo 

p 

Draw path 

U 

Redo 

o 

Create various contacts 

del 

Delete 

^p 

Create pin 

s 

Strech one side of a polygon or path 

l(el) 

Create label 

m 

Move 

^z 

Zoom in by 2 

c 

Copy 

Z 

Zoom out by 2 

R 

Reshape a polygon 

^r 

Redraw 

i 

Create instance (Pcell or other cells) 

f 

Fit draw in window 

q 

Set properties 

k 

Create ruler 

Esc 

Cancel current command 

K 

Clean all ruler 

13

Some tricks 

Reshape 

or 

Make Cell 

Make selected geometries to a cell. 

When a cell is modified, all instances of it will be 

updated. 

Also can flip selected geometries (when using “i” to 

instance a cell) 

Flatten: don’t maintain cell hierarchy, i.e., your 

layout is no longer dependent to other cells. 

14

Instance a cell (Pcell) 

Sideways: flip horizontal 

Upside down: flip vertical 

Fill 

parameters 

for Pcell here 

15

Contacts, pins, labels 

Contacts: besides connection contacts 

Power contacts (M1_P in NWELL) 

Ground contacts (M1_N in p-substrate) 

must be placed within a distance. 

Lots of Power/Ground contacts in series 

Guard ring, shield the noise from 

NWELL/substrate 

Pins: for on-line checking (Verify DRC) 

Must use METAL1 for power (vdd!) and 

ground (gnd!), therefore, it’s a part of layout. 

16

Contacts, pins, labels 

Labels: for off-line checking (Dracula) 

Must use text2 for power (vdd!) and ground 

(gnd!), it’s not a part of layout. 

Sometimes Dracula will miss the labels, 

increase its size or change position then try 

again… 

17

On-line checking 

In Virtuoso, Verify DRC 

Just press OK 

Usually only perform on-line Design-Rule- 

Checking, it’s fast to get results. 

Erroneous area will be shown in blinking 

“X”, and error messages are shown in 

CIW window (icfb window) 

Use Verify Markers to get the message 

of an erroneous area 

18

Off-line checking 

Dracula, for CONFIDENCE LEVEL! 

DRC, LVS, LPE 

Preparing 

Command files 

Stream data of your layout 

Schematic file (created by Composer) 

or SPICE netlist for LVS (layout vs. schematic) 

A TEMPERORY DIRECTORY, it generates 

LOTS of temporary files 

19

Command file 

Command file, copy one to the temporary 

directory and modify it. 

The following lines are located at the beginning of 

the command file 

PRIMARY = _cell_name_ ;top module name 

INDISK = _cell_name_.gds ;gds file name 

OUTDISK = _cell_name_.out ;output file name 

PRINTFILE = _cell_name_ ; 

20

Stream out 

In CIW, File Export Stream 

Fill library name, cell 

name, and output file 

name 

The stream-out data is 

also known as GDSII 

format, which is what 

you submit to FAB 

21


For Composer schematic file, in CIW, 

File Export CDL 

to get netlist file. 

For SPICE netlist, enclose your top 

module by a sub-circuit description (no 

stimulus required) 

At the temporary directory, type LOGLVS 

to generate files of LVS 

22


After enter LOGLVS, the prompt is: 

(upper is the help message) 

ENTER COMMAND 

: 

Then type 

:htv 

:cir netlist_filename 

:con top_module_name 

:x 

For checking R and C, 

*.BIPOLAR 

Must be included in the netlist file 

23

Execution 

When all items are ready, type PDRACULA at 

the temporary directory, the prompt is 

******************************************************************************* 

*/N* DRACULA3 ( REV. 4.8 / SUN-4 S5R4 /GENDATE: 29-OCT/1999 ) 

*** ( Copyright 1995, Cadence ) *** 

*/N* EXEC TIME =22:47:57 DATE =27-AUG-2002 HOSTNAME = bluebird 

******************************************************************************* 

: 

Then type 

:/g command_filename n 

:/f 

A jxrun.com will be generated, the run it at unix prompt: 

> jxrun.com >! xxx.log & 

For large layout, it may take a few hours, so you may 

logout after execute it at backgroud. 

24

Outputs 

DRC: *.sum 

LVS: *.lvs 

Hard to understand and debug 

In Virtuoso, Tools Dracula Interactive 

then select the LVS menu for more friendly 

interface (sometime it will crash… ) 

LPE: similar as LVS, but you must pass 

LVS first, a SPICE01.DAT will be generated. 

Trick: run LPE without LVS first, mark the 

line “LPECHK[SOREF]...” at the end of LPE 

command file 

25

Make a Pcell 

In Virtuoso, Tools Pcell 

Draw a basic resistor first 

In Pcell menu, Stretch Stretch in X 

draw the stretch line (in yellow), the double 

click the line shows the form 

26

Make a Pcell 

In Pcell menu, Repetition Repeat in Y 

select the shapes to be repeated, double click 

the shapes show the form 

Use the modify or redefine submenus to modify 

it (arithmetic expression is allowed) 

27

Make a Pcell 

Parameters Summarize to show the status 

Compile To Pcell (function selects none) 

Done 

28

Make a Pcell 

Instance it 

29

Hspice simulation 

A demonstration file 

* First line must be empty or a comment line 

* ‘*’ is the symbol of comments 

.protect 

.lib './ls35_4_1.l' TT 

.unprotect 

.options post 

m1 1 6 3 3 nch w=100u l=0.6u 

m2 3 4 5 5 nch w=10u l=0.6u 

m3 6 3 5 5 nch w=10u l=0.6u 

r4 1 6 20k 

c1 6 0 100u 

r1 5 0 2k 

v1 4 0 5 

c2 3 0 0.001u 

v2 1 0 pulse(11 12 0 0 0 5n 10n) 

.tran 1n 10u 

.end 

30

Some commands 

.protect/.unprotect 

Don’t dump the contents that is enclosed by 

them, usually to avoid displaying the whole 

model file. 

.lib ‘spice_model_file’model 

Model TT is typical NMOS and PMOS 

Model SS is slow NMOS and PMOS 

Model FF is fast NMOS and PMOS 

These models can be found at the beginning 

of the model file. 

31

Some commands 

.options post 

Set options, post means generate waveform 

files (for waveform viewer) 

.tran Time domain analysis 

.ac Frequency domain analysis 

.dc DC (steady state) analysis 

Monte Carlo (statistical) analysis 

Work with .tran .ac .dc 

Useful for evaluating process variation 

32

Some commands 

.measure 

Performs your desired measurement on 

waveform 

Reduce the usage of waveform viewer (slow) 

.inc ‘filename’ 

Include another spice netlist file 

.subckt subcktname iolist ..... 

Create sub-circuit, like module in verilog 

End with .ends 

33

Execution and outputs 

Execution: At unix prompt 

>hspice –l xxx.lis xxx.sp & 

Outputs: 

.lis 

.sw# 

.ms# 

.ac# 

.ma# 

.tr# 

.mt# 

.ic 

Output list 

DC analysis results 

DC measurement results 

AC analysis results 

AC measurement results 

Transient analysis results 

Transient measurement results 

Initial condition of nodal voltages 

34

Waveform viewer 

awaves: 

View the waveforms of analysis 

Slow if the waveform data is large (~100MB) 

Supports arithmetic operations on output 

variables (ex. voltage and current). 

Use middle button to drag the variable into 

function menu 

Can change X-axis to other variables 

Update waveform without re-launching 

awaves: ^u 

35

Resources 

Lots of useful sub-circuits are located at: 

/usr/meta/cur/parts 

including discrete component (FET, BJT, 

diode) and linear circuits (OP) 

Demos can be found at 

/usr/meta/cur/demo 

including the demos of awaves and 

hspice 

How to draw eye diagrams on awaves can be 

found here. 

36

Full-Custom Design Flow in LaRC (Cadence)

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