Hardware Design Guide Revision 0.3 - elinux
Hardware Design Guide Revision 0.3 - elinux
Hardware Design Guide Revision 0.3 - elinux
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Eng.Mang.<br />
Title<br />
WG7310-to-3V3 Host Reference <strong>Design</strong><br />
Size Document Number Rev<br />
Custom<br />
WG7310R00<br />
R02<br />
Date: Friday , June 12, 2009<br />
Sheet 2 of 2<br />
Name Date Sign<br />
<strong>Design</strong>er<br />
Approval<br />
Chief Eng.<br />
JORJIN TECHNOLOGIES INC.<br />
WiFi Interface: SDIO or SPI<br />
BT Interface: UART, PCM<br />
FM Interface: UART (with BT together),<br />
I2S, Audio IN/OUT<br />
Fast Clock: 38.4MHz built-inside<br />
Slow Clock: 32.768KHz from outside<br />
VBAT_IN: 2.3~4.8V => 3.3V TYP<br />
VIO_IN: 1.62~1.92V => 1.8V TYP<br />
Slow Clock: 32.768KHz for module boot<br />
and deep sleep<br />
WL_EN and BT_EN: Please attach a 3.3K ohm<br />
up to VIO_IN if no use<br />
R118<br />
10K<br />
R0402<br />
R19<br />
12K<br />
R0402<br />
2<br />
GND<br />
O/P<br />
3<br />
OSC1<br />
KK3270022<br />
3.2X2.5MM<br />
1<br />
PD VDD 4<br />
C17<br />
0.1uF<br />
CAP1005<br />
C18<br />
10nF<br />
CAP1005<br />
C19<br />
0.1uF<br />
CAP1005<br />
C16<br />
0.1uF<br />
C0402<br />
Scheme Brief<br />
** Boot Conditions<br />
VBAT_IN<br />
3V3<br />
U3<br />
TPS73618DBV<br />
SOT-23-5<br />
1<br />
IN<br />
2<br />
GND<br />
EN<br />
VBAT_IN<br />
VIO_IN<br />
3V3 1V8<br />
5<br />
3<br />
OUT<br />
4<br />
NR/FB<br />
32.768K XOSC<br />
1.8V LDO<br />
PCM_AUD_OUT_89 E5<br />
F5<br />
GND_90<br />
GND_91 G5<br />
GND_92 G6<br />
GND_93 G7<br />
F7<br />
GND_94<br />
GND_95 E7<br />
GND_96 E6<br />
L2<br />
NL/120nH<br />
L0402<br />
L4<br />
12nH<br />
L0402<br />
2<br />
FA_TX_ANT<br />
FM RF-OUT<br />
1<br />
ANT3<br />
FMA0101<br />
24x5mm<br />
R11 0R R0402<br />
R12 0R R0402<br />
L3<br />
100nH<br />
L0402<br />
BD_HCI_RTS_1V8<br />
BD_HCI_CTS_1V8<br />
TP7 Must be reserv ed f or test<br />
TP8 Must be reserv ed f or test<br />
TP9 Must be reserv ed f or test<br />
TP10 Must be reserv ed f or test<br />
BD_HCI_TX_1V8<br />
R9 0R R0402<br />
R10 0R R0402<br />
BD_HCI_RX_1V8<br />
C9 1uF/NL C0402<br />
VIO_IN<br />
1V8<br />
WB_RF_ANT<br />
C5<br />
1uF/NL<br />
C0402<br />
FA_RX_ANT<br />
***** WiFi SDIO/SPI<br />
DS_SDIO_D1<br />
R3 0R R0402 DS_SDIO_D1_1V8<br />
DS_SDIO_D2 R4 0R R0402 DS_SDIO_D2_1V8<br />
DS_SPI_CSX R5 0R R0402 DS_SPI_CSX_1V8<br />
DS_SPI_DIN R6 0R R0402 DS_SPI_DIN_1V8<br />
DS_SPI_DOUT R7 0R R0402 DS_SPI_DOUT_1V8<br />
DS_SPI_CLK R8 0R R0402 DS_SPI_CLK_1V8<br />
** It's recommended to insert 0 ohm resistors in WiFi SDIO/SPI<br />
pathes and keep them close to WG7310 module for test<br />
** The six traces from U1 ( module ) to U2 ( level shifter )<br />
and from U2 to Host must be treated like two buses. The<br />
bus length shall be as short as possible and every trace<br />
length must be the same as the others. Enough space above<br />
1.5 time trace width or ground shielding between trace<br />
and trace will be benefit to make sure signal quality,<br />
especially for SDIO_CLK trace. Besides, please remember<br />
to keep them away from the other digital or analog signal<br />
traces. To add ground shielding to around the buses will<br />
be good.<br />
E3<br />
GND<br />
D3<br />
GND<br />
E5<br />
GND<br />
E4<br />
GND<br />
Doc No: WG7310-00-HDG-R03<br />
GND_01<br />
WG7310-00<br />
A1<br />
VBAT_FEM_02 A2<br />
BT_FUNC2: BT_WU/ DC2DC_03 B1<br />
GND_04 B2<br />
BT_FUNC6: BT_SDA_05 C1<br />
BT_FUNC4: BT_TX_DBG_06 C2<br />
BT_FUNC5: HOST_WU_07 D1<br />
GND_08 D2<br />
GND_09 E1<br />
DRPWPABC_10 E2<br />
F1<br />
BT_RF_ANT_11<br />
F2<br />
GND_12<br />
GND_13 G1<br />
DRPWPDET_14 G2<br />
WL_TX_SW_15 H1<br />
GND_16 H2<br />
J1<br />
WL_BTH_SW_17<br />
J2<br />
WL_RX_SW_18<br />
GND_19 K1<br />
VCC_DCOW_20 K2<br />
L1<br />
NC_C3_21<br />
L2<br />
GND_22<br />
L3<br />
FM_EN_23<br />
VCC_RXW_24 K3<br />
L4<br />
GND_25<br />
BT_EN_26 K4<br />
L5<br />
WB_RF_ANT_27<br />
GND_28 K5<br />
L6<br />
GND_29<br />
WL_RS232_RX/ I2S_M_SCL_30 K6<br />
L7<br />
SDIO_D1_31<br />
WL_RS232_TX/ I2S_M_SDA_32 K7<br />
L8<br />
SDIO_D2_33<br />
SPI_CSX/ SDIO_D3_34 K8<br />
L9<br />
SPI_DIN/ SDIO_CMD_35<br />
SPI_DOUT/ SDIO_D0_36 K9<br />
L10<br />
SPI_CLK/ SDIO_CLK_37<br />
FM_I2S_FSYNC_38 K10<br />
L11<br />
WL_EN_39<br />
FM_SDA_40 K11<br />
J11<br />
FM_SCL_41<br />
J10<br />
FM_IRQ_42<br />
FM_I2S_CLK_43 H11<br />
FM_I2S_DI_44 H10<br />
FM_I2S_DO_45 G11<br />
GND_46 G10<br />
F11<br />
GND_47<br />
F10<br />
SLOWCLK_48<br />
FM_TX_ANT_49 E11<br />
GND_50 E10<br />
GND_51 D11<br />
FMAUDROUT_52 D10<br />
FM_RX_ANT_53 C11<br />
GND_54 C10<br />
GND_55 B11<br />
FMAUDLOUT_56 B10<br />
FMAUDRIN_57 A11<br />
GND_58 A10<br />
FMAUDLIN_59 A9<br />
GND_60 B9<br />
GND_61 A8<br />
XTALP_62 B8<br />
XTALM_63 A7<br />
GND_64 B7<br />
GND_65 A6<br />
BT_FUNC1: DC2DC/ btSPI_CLK_66 B6<br />
DC_REQ_67 A5<br />
TPS_DC2DC_68 B5<br />
VIO_69 A4<br />
1V8_70 B4<br />
VBAT_71 A3<br />
VDD_LDO_IN_CLASS1P5_72 B3<br />
PCM_AUD_CLK_73 D4<br />
PCM_AUD_IN_74 E4<br />
F4<br />
GND_75<br />
WL_PAEN_B_76 G4<br />
GND_77 H4<br />
VCC_ANAW_78 H5<br />
VCC_TXBW_79 H6<br />
WL_UART_DBG_80 H7<br />
CLK_REQ_OUT_81 H8<br />
WLAN_IRQ_82 G8<br />
F8<br />
HCI_RX/ btSPI_DIN_83<br />
HCI_TX/ btSPI_DOUT_84 E8<br />
BT_FUNC7: BT_SCL_85 D8<br />
HCI_RTS/ btSPI_IRQ_86 D7<br />
HCI_CTS/ btSPI_CS_87 D6<br />
PCM_AUD_FSYNC_88 D5<br />
BD_HCI_RTS<br />
BD_HCI_CTS<br />
BD_PCM_AUD_FSYNC<br />
BD_PCM_AUD_OUT<br />
FM RF-IN<br />
C15<br />
1nF<br />
C0402<br />
2<br />
BD_HCI_RX<br />
BD_HCI_TX<br />
FA_RX_ANT<br />
1<br />
ANT2<br />
FMA0101<br />
24x5mm<br />
C10 1uF/NL C0402<br />
WD_UART_DBG<br />
WD_IRQ<br />
TP6 Must be reserv ed f or test<br />
AS_VCC_ANAW<br />
AS_VCC_TXBW<br />
BD_PCM_AUD_CLK<br />
BD_PCM_AUD_IN<br />
C7<br />
NL/2.2uF<br />
C0402<br />
8<br />
7<br />
3<br />
4<br />
L1<br />
NL<br />
L0402<br />
2<br />
WiFi/BT RF-I/O<br />
5<br />
1<br />
ANT1<br />
AT8010-E2R9HAA<br />
8x1mm<br />
C8 1uF/NL C0402<br />
SW1<br />
MM8430<br />
3x3mm<br />
6<br />
2<br />
1<br />
C13<br />
10pF<br />
C0402<br />
C14<br />
10pF<br />
C0402<br />
1V8 FM AUDIO<br />
C6<br />
10uF/NL<br />
C0805<br />
FA_AUD_IN_L<br />
VIO_IN<br />
VBAT_IN<br />
VBAT_IN ANTENNA 1V8 3V3<br />
3V3<br />
CIRCUITS<br />
** AUD_DIR = R26 NL, R27 0 ohm --> AUD_FSYNC and AUD_CLK from WG7310 to Host;<br />
AUD_DIR = R26 0 ohm, R27 NL --> AUD_FSYNC and AUD_CLK from Host to WG7310<br />
FA_AUD_OUT_L<br />
FA_AUD_IN_R<br />
FA_AUD_OUT_R<br />
R16 NL/0R<br />
R0402<br />
R17 0R<br />
R0402<br />
Copyright © JORJIN TECHNOLOGIES INC. LIMITED 2009<br />
CONFIDENTIAL<br />
FA_TX_ANT<br />
MD_SLOWCLK<br />
VBAT_IN<br />
B4<br />
AUD_DIR A4<br />
FD_I2S_CLK<br />
FD_I2S_DI<br />
FD_I2S_DO<br />
MD_SLOWCLK<br />
R15 NL<br />
R0402<br />
F4<br />
R2<br />
3.3K<br />
R0402<br />
PCM_AUD_OUT_A G3<br />
SLOW_CLK_A G4<br />
BD_EN<br />
R14 0R/NL<br />
R0402<br />
BD_EN_1V8<br />
BD_HCI_RX_1V8<br />
BD_HCI_CTS_1V8<br />
BD_HCI_TX_1V8<br />
BD_HCI_RTS_1V8<br />
BD_PCM_AUD_IN<br />
BD_PCM_AUD_CLK<br />
BD_PCM_AUD_FSYNC<br />
BD_PCM_AUD_OUT<br />
MD_SLOWCLK_1V8<br />
LS<br />
WD_IRQ<br />
WD_EN<br />
R13 0R/NL<br />
R0402<br />
R20 0R/NL<br />
R0402<br />
C5<br />
D5<br />
B6<br />
C6<br />
C7<br />
B7<br />
A6<br />
A7<br />
D6<br />
D7<br />
E7<br />
E6<br />
G7<br />
F7<br />
G6<br />
F6<br />
F5<br />
A5<br />
B5<br />
G5<br />
E1<br />
CLK_REQ_A<br />
E2<br />
BT_ENABLE_A<br />
BT_UART_RX_A G1<br />
F1<br />
BT_UART_CTS_A<br />
BT_UART_TX_A G2<br />
F2<br />
BT_UART_RTS_A<br />
F3<br />
PCM_AUDIO_IN_A<br />
A3<br />
PCM_AUDIO_CLK_A<br />
B3<br />
PCM_AUDIO_F_SYNC_A<br />
WLAN_ENABLE_A D1<br />
WLAN_IRQ_A D2<br />
R1<br />
3.3K<br />
R0402<br />
VCCA C4<br />
VCCA D4<br />
B2<br />
SDIO_DATA0_A<br />
SDIO_DATA1_A C2<br />
SDIO_DATA2_A C1<br />
B1<br />
SDIO_DATA3_A<br />
A2<br />
SDIO_CMD_A<br />
A1<br />
SDIO_CLK_A<br />
** SDIO_D1 and SDIO_D2 shall be connected to<br />
GND if using SPI host interface<br />
** SDIO lines should be held high by the host<br />
U2<br />
TWL1200<br />
4.1x4.1mm<br />
VCCB<br />
VCCB<br />
SPI_DOUT/ SDIO_DATA0_B<br />
SDIO_DATA1_B<br />
SDIO_DATA2_B<br />
SPI_CSX/ SDIO_DATA3_B<br />
SPI_DIN/ SDIO_CMD_B<br />
SPI_CLK/ SDIO_CLK_B<br />
WLAN_ENABLE_B<br />
WLAN_IRQ_B<br />
CLK_REQ_B<br />
BT_ENABLE_B<br />
BT_UART_RX_B<br />
BT_UART_CTS_B<br />
BT_UART_TX_B<br />
BT_UART_RTS_B<br />
PCM_AUDIO_IN_B<br />
PCM_AUDIO_CLK_B<br />
PCM_AUDIO_F_SYNC_B<br />
PCM_AUD_OUT_B<br />
SLOW_CLK_B<br />
OE<br />
BD_PCM_AUD_OUT_3V3<br />
MD_SLOWCLK_3V3<br />
1V8 FM I2S<br />
FD_I2S_FSYNC<br />
TP5 Must be reserv ed f or test<br />
TP4 Must be reserv ed f or test<br />
BD_EN_3V3<br />
BD_HCI_RX_3V3<br />
BD_HCI_CTS_3V3<br />
BD_HCI_TX_3V3<br />
BD_HCI_RTS_3V3<br />
BD_PCM_AUD_IN_3V3<br />
BD_PCM_AUD_CLK_3V3<br />
BD_PCM_AUD_FSYNC_3V3<br />
VIO_IN<br />
DS_SPI_DOUT_1V8<br />
DS_SDIO_D1_1V8<br />
DS_SDIO_D2_1V8<br />
DS_SPI_CSX_1V8<br />
DS_SPI_DIN_1V8<br />
DS_SPI_CLK_1V8<br />
WD_EN_1V8<br />
WD_IRQ_1V8<br />
WD_EN_3V3<br />
WD_IRQ_3V3<br />
AS_VCC_RXW<br />
BD_EN<br />
WB_RF_ANT<br />
WD_RS232_RX<br />
DS_SDIO_D1<br />
WD_RS232_TX<br />
DS_SDIO_D2<br />
DS_SPI_CSX<br />
DS_SPI_DIN<br />
DS_SPI_DOUT<br />
DS_SPI_CLK<br />
WD_EN<br />
VIO_IN<br />
C4 1uF/NL C0402<br />
AS_VCC_DCOW<br />
AS_NC_C3<br />
C2 1uF/NL C0402<br />
C3 1uF/NL C0402<br />
DS_SPI_DOUT_3V3<br />
DS_SDIO_D1_3V3<br />
DS_SDIO_D2_3V3<br />
DS_SPI_CSX_3V3<br />
DS_SPI_DIN_3V3<br />
DS_SPI_CLK_3V3<br />
C11 0.1uF<br />
C0402<br />
C12 0.1uF<br />
C0402<br />
3V3<br />
BD_TX_DBG<br />
BD_HOST_WU<br />
TP2 Must be reserv ed f or test<br />
TP3 Reserv ed f or host CPU which doesn't support UART wakeup<br />
VIO_IN<br />
1V8<br />
VBAT_IN<br />
TP1 Reserv ed f or host CPU which doesn't support UART wakeup<br />
BD_WU<br />
C1 1uF/NL C0402<br />
3V3 I/O to HOST<br />
U1<br />
WG7310-00<br />
10x10mm<br />
WG7310-00 MODULE<br />
TWL1200 1V8-to-3V3 LEVEL SHIFTER<br />
- 20-<br />
WG7310-to-3V3 Host Reference <strong>Design</strong><br />
( Preliminary-subject to change )
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