Hardware Design Guide Revision 0.3 - elinux
Hardware Design Guide Revision 0.3 - elinux
Hardware Design Guide Revision 0.3 - elinux
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3. Power Sequence<br />
3.1. WLAN Power on Sequence<br />
Figure 1. WLAN Power on sequence<br />
Doc No: WG7310-00-HDG-R03<br />
The duration of T1 is defined as the time from WL_EN=high until Fref is<br />
valid for the SoC.<br />
T1 ~ 55ms<br />
The duration of T2 depends on:<br />
� Operation system<br />
� Host enumeration for the SDIO/SPI<br />
� PLL configuration<br />
� Firmware download<br />
� Releasing the core from reset<br />
� Firmware initialization<br />
Copyright © JORJIN TECHNOLOGIES INC. LIMITED 2009<br />
CONFIDENTIAL<br />
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