Hardware Design Guide Revision 0.3 - elinux

a module solution provider 

WG7310-00 WLAN+BT+FM Module 

Hardware Design Guide 

Revision 0.3 

Copyright © JORJIN TECHNOLOGIES INC. LIMITED 2009 

TI WL1271 solution

Contents 

Doc No: WG7310-00-HDG-R03 

1. WG7310 MODULE DESCRIPTION........................................................................3 

1.1. WG7310 BLOCK DIAGRAM ...............................................................................3 

1.2. PIN DESCRIPTION .................................................................................................4 

2. ELECTRICAL CHARACTERISTICS .........................................................................7 

2.1. ABSOLUTE MAXIMUM RATINGS.............................................................................7 

2.2. RECOMMENDED OPERATING CONDITIONS..........................................................7 

2.3. EXTERNAL SLOW CLOCK INPUT (SLEEP_CLK).....................................................7 

3. POWER SEQUENCE ................................................................................................9 

3.1. WLAN POWER ON SEQUENCE ............................................................................9 

3.2. BLUETOOTH POWER UP/DOWN SEQUENCE........................................................10 

4. INTERFACE CHARACTERISTICS ......................................................................... 11 

4.1. WLAN SDIO CHARACTERISTIC.........................................................................11 

4.1.1. SDIO Read Timing ................................................................................ 11 

4.1.2. SDIO Interface Write Timing ..............................................................12 

4.1.3. SDIO Clock Timing ...................................................................................12 

4.2. WLAN WSPI CHARACTERISTICS ........................................................................13 

4.2.1. SPI Read/Write Timing.........................................................................13 

4.2.2. SPI Clock Timing....................................................................................14 

4.3. BLUETOOTH HCI INTERFACE ...............................................................................15 

4.4. BLUETOOTH PCM INTERFACE.............................................................................16 

5. DEBUG INTERFACE...............................................................................................18 

5.1. WLAN RS232 TESTING PORT ............................................................................18 

5.2. BLUETOOTH HCI TESTING PORT ..........................................................................18 

6. REFERENCE SCHEMATIC.....................................................................................19 

7. MODULE MECHANICAL OUTLINE.....................................................................21 

8. LAYOUT RECOMMENDATION ...........................................................................22 

8.1. RECOMMENDED BUMP PAD DESIGN *...............................................................22 

8.2. RECOMMENDED STENCIL DESIGN *....................................................................22 

8.3. RECOMMENDED TRACE LAYOUT ........................................................................22 

9. SMT AND BAKING RECOMMENDATION ........................................................25 


CONFIDENTIAL 

- 1-


9.1. BAKING RECOMMENDATION..............................................................................25 

9.2. SMT RECOMMENDATION...................................................................................25 

10. HISTORY CHANGE.............................................................................................27 


CONFIDENTIAL 

- 2-

1. WG7310 Module Description 


WG7310, a WLAN , Bluetooth and FM SiP (system in package) module, is 

the most demanded design for all handset and portable devices with TI 

WL1271 IEEE 802.11b/g/n and BT v2.1 EDR solutions to provide the best 

WLAN and BT coexistence interoperability and power saving 

technologies from TI. 

1.1. WG7310 Block Diagram 

VBAT 

VIO 

Slow CLK 

Host I/F 

Host Signaling 

Debug I/F 

DC2DC 

38.4M X’tal 

WL1271 

WLAN 

BT 

FM 

WG7310 

WL1271 FE 

PA(b/g/n) 


CONFIDENTIAL 

SW 

TX 

RX 

BPF 

- 3- 

Matching 

Matching

1.2. Pin Description 


No. Index Name Type Description 

1 A1 GND GND GROUND 

2 A2 VBAT_FEM O FEM POWER SUPPLY 

3 B1 BT_FUNC2: BT_WU/ DC2DC O BT WU (default) or BT DC2DC 

4 B2 GND GND GROUND 

5 C1 BT_FUNC6: BT_SDA O BT SDA (internal use only) 

6 C2 BT_FUNC4: BT_TX_DBG O BT UARTD (reserved for debug) 

7 D1 BT_FUNC5: HOST_WU O HOST WU 

8 D2 GND GND GROUND 

9 E1 GND GND GROUND 

10 E2 DRPWPABC O WL PA BIAS (internal use only) 

11 F1 BT_RF_ANT I/O BT RF ANT (internal use only) 

12 F2 GND GND GROUND 

13 G1 GND GND GROUND 

14 G2 DRPWPDET I WL POWER DET IN (internal use only) 

15 H1 WL_TX_SW O WLPA_IF (internal use only) 

16 H2 GND GND GROUND 

17 J1 WL_BTH_SW O WLPA_IF (internal use only) 

18 J2 WL_RX_SW O WLPA_IF (internal use only) 

19 K1 GND GND GROUND 

20 K2 VCC_DCOW O WL DCO SUPPLY 

21 L1 NC_C3/VCC_TXAW O WL PPA A SUPPLY 

22 L2 GND GND GROUND 

23 L3 FM_EN I FM RST 

24 K3 VCC_RXW O WL LNA SUPPLY 


26 K4 BT_EN I BT RST 

27 L5 WB_RF_ANT I/O WL/BT RF ANT 

28 K5 GND GND GROUND 


30 K6 WL_RS232_RX/ I2S_M_SCL I RS232_RX (default) or I2C_M_SCL 

(reserved for debug) 

31 L7 SDIO_D1 I/O SDIO IF 

32 K7 WL_RS232_TX/ I2S_M_SDA O RS232_TX (default) or I2C_M_SDA 


CONFIDENTIAL 

- 4-

33 L8 SDIO_D2 I/O SDIO IF 

34 K8 SPI_CSX/ SDIO_D3 I/O SDIO IF 

35 L9 SPI_DIN/ SDIO_CMD I/O SDIO IF 

36 K9 SPI_DOUT/ SDIO_D0 I/O SDIO IF 

37 L10 SPI_CLK/ SDIO_CLK I SDIO IF 

38 K10 FM_I2S_FSYNC I/O FM I2S IF 

39 L11 WL_EN I WL RST 

40 K11 FM_SDA I/O FM I2C IF 

41 J11 FM_SCL I/O FM I2C IF 

42 J10 FM_IRQ O FM I2C IF 

43 H11 FM_I2S_CLK I/O FM I2S IF 

44 H10 FM_I2S_DI I FM I2S IF 

45 G11 FM_I2S_DO O FM I2S IF 



48 F10 SLOWCLK I SLEEP CLK 

49 E11 FM_TX_ANT O FM TX ANT 


51 D11 GND GND GROUND 


(reserved for debug) 

52 D10 FMAUDROUT O FM AUD OUT 

53 C11 FM_RX_ANT I FM RX ANT 

54 C10 GND GND GROUND 


56 B10 FMAUDLOUT O FM AUD OUT 

57 A11 FMAUDRIN I FM AUD IN 


59 A9 FMAUDLIN I FM AUD IN 



62 B8 XTALP O FREF INPUT (internal use only) 

63 A7 XTALM O FREF INPUT (internal use only) 



66 B6 BT_FUNC1: O BT DC2DC mode (default) 


CONFIDENTIAL 

- 5-

DC2DC/ btSPI_CLK or btSPI_CLK 


67 A5 DC_REQ O DC_REQ to INTERNAL DC2DC 

68 B5 TPS_DC2DC I MODE SELECTION PIN OF DC2DC 

69 A4 VIO I 1.62~1.92V POWER SUPPLY, 1.8V TYP 

70 B4 1V8 O 1.8V DC2DC POWER SUPPLY 

71 A3 VBAT I 2.3~4.8V POWER SUPPLY, 3.3V TYP 

72 B3 VDD_LDO_IN_CLASS1P5 I BT CLASS2/CLASS1.5 POWER SUPPLY 

73 D4 PCM_AUD_CLK/ 

FM_I2S_CLK 

I/O PCM I/F (default ) or FM I2S CLK 

74 E4 PCM_AUD_IN/ FM_I2S_DI I/O PCM I/F (default ) or FM I2S DI 


76 G4 WL_PAEN_B O WLPA_IF (internal use only) 

77 H4 GND GND GROUND 

78 H5 VCC_ANAW O WLANA INPUT SUPPLY 

79 H6 VCC_TXBW O WL PPA BG SUPPLY 

80 H7 WL_UART_DBG O WL_UART_DBG (reserved for debug) 

81 H8 CLK_REQ_OUT O CLK_REQ positive polarity 

82 G8 WLAN_IRQ O WLAN interrupt request 

83 F8 HCI_RX/ btSPI_DIN I BT UART I/F (default) or btSPI DIN 

84 E8 HCI_TX/ btSPI_DOUT O BT UART I/F (default) or btSPI DOUT 

85 D8 BT_FUNC7: BT_SCL I/O BT_SCL (internal use only) 

86 D7 HCI_RTS/ btSPI_IRQ I/O BT UART I/F (default) or btSPI IRQ 

87 D6 HCI_CTS/ btSPI_CS I/O BT UART I/F (default) or btSPI CS 

88 D5 PCM_AUD_FSYNC/ 

FM_I2S_FSYNC 

89 E5 PCM_AUD_OUT/ 

FM_I2S_DO 








I/O PCM I/F (default) or FM I2S FSYNC 

O PCM I/F (default) or FM_I2S_DO 


CONFIDENTIAL 

- 6-

2. Electrical Characteristics 

2.1. Absolute Maximum Ratings 

Over operating free-air temperature range 

Supply Voltage Range 


Characteristics Value Unit 

VBAT -0.5 to 5.5 V 

VIO -0.5 to 2.1 V 

Input Voltage to Analog Pins -0.5 to 2.1 V 

Input Voltage to all Other Pins -0.5 to VIO + 0.5V V 

Operating Ambient Temperature Range -20 to 70 °C 

Storage Temperature Range -45 to 85 °C 

2.2. Recommended Operating Conditions 

The WG7310 requires two supplies: VBAT and VIO. 

Power Supply 

Voltage 

Min. Typ. Max. 

VBAT 2.7V 3.3V 4.8V 

VIO 1.62V 1.8V 1.92V 

2.3. External Slow Clock Input (SLEEP_CLK) 

The external slow clock input SLEEP_CLK must be present at all times. The 

slow clock is used to maintain timers that synchronize the device to the 

access point (AP) beacons. 

Table 1. External Slow Clock Input Requirements 

Characteristics Condition Min. Typ. Max. Unit 

Frequency 32.768 KHz 

Reference Frequency 

Accuracy 

WLAN, BT, 

FM_RX 


CONFIDENTIAL 

+/-150 

FM_TX +/- 40 

Input Transmit Time 10% ~ 90% 100 ns 

- 7- 

ppm


Frequency Duty Cycle 30 50 70 % 

Fail Safe Maximum 

Value 

Input Voltage Limits 

VIH 0.65xVIO VIO 

(Square Wave) VIL 0 0.35xVIO 


CONFIDENTIAL 

2.0 V 

- 8- 

Vpeak 

Input Impedance 1 MΩ 

Input Capacitance 5 pF 

Rise and fall time 100 ns 

Phase noise 1kHz -125 dBc/Hz

3. Power Sequence 

3.1. WLAN Power on Sequence 

Figure 1. WLAN Power on sequence 


The duration of T1 is defined as the time from WL_EN=high until Fref is 

valid for the SoC. 

T1 ~ 55ms 

The duration of T2 depends on: 

� Operation system 

� Host enumeration for the SDIO/SPI 

� PLL configuration 

� Firmware download 

� Releasing the core from reset 

� Firmware initialization 


CONFIDENTIAL 

- 9-

3.2. Bluetooth Power Up/Down Sequence 


Power up requirements: 

1. BT_EN must be low 

2. VIO must be stable before releasing BT_EN. 

3. Slow clock must be stable within 2 ms of BT_EN high. 

Figure 2. Bluetooth Power Up/Down sequence 

WG7310 indicates completion of power up sequence by asserting RTS 

low. This occurs up to 100ms after BT_EN goes high. 


CONFIDENTIAL 

- 10-

4. Interface Characteristics 

tCR 

tID 

tCC 

tRC 

tAC 

4.1. WLAN SDIO Characteristic 

4.1.1. SDIO Read Timing 

Figure 3. SDIO Single Block Read 


Table 2. SDIO Read Switching characteristics 

Parameter Min. Max. Unit 

Delay time, assign relative address/data transfer 

mode, CMD command invalid to CMD response 

valid 

Delay time, identification, CMD command invalid 

to CMD response valid 

Delay time, CMD command invalid to CMD 

response valid 

Delay time, CMD response invalid to CMD 

command valid 

Access time, CMD command invalid to SD3-SD3 

read data valid 

2 64 

5 5 

8 --- 

8 --- 

2 --- 


CONFIDENTIAL 

Clock 

Cycles 

Clock 

Cycles 

Clock 

Cycles 

Clock 

Cycles 

- 11-

4.1.2. SDIO Interface Write Timing 


(1) CRC status and busy waveforms are only for data line 0. Data lines 1-3 are N/A. The 

busy waveform is optional and may not be present. 

td1 

td2 

Figure 4. SDIO Single Block Write 

Table 3. SDIO Write Switching characteristics 


Delay time, CMD card response invalid to SD3-SD0 

write data valid 

Delay time, SD3-SD0 write data invalid end to CRC 

status valid 

4.1.3. SDIO Clock Timing 

2 --- 

2 2 


CONFIDENTIAL 

Clock 

Cycles 

Clock 

Cycles 

- 12-

Figure 5. SDIO Clock Timing 

Table 4. SDIO Timing requirement 



fclock Clock frequency, CLK 0 25 MHZ 

DC Low/high duty cycle 40 60 % 

tWL Pulse duration, CLK low 10 ns 

tWH Pulse duration, CLK high 10 ns 

tTLH Rise time, CLK 4.3 ns 

tTHL Fall time, CLK 3.5 ns 

tISU Setup time, input valid before CLK↑ 5 ns 

t1H Hold time, input valid after CLK↑ 5 ns 

tODLY1 Delay time, CLK↓ to output valid 0 14 ns 

TODLY2 Delay time, CLK↓ to output invalid 0 14 ns 

4.2. WLAN wSPI Characteristics 

The SPI interface signals are shared with the SDIO bus in the WG7310. 

4.2.1. SPI Read/Write Timing 

Figure 6. SPI Read Timing 


CONFIDENTIAL 

- 13-

tCS 

tCR 

Figure 7. SPI Write Timing 


Table 5. SPI Read/Write Switching characteristics 


Delay time, CS↓ to DIN read/write command 

valid 

Delay time, DIN read command invalid to 

DOUT/DIN card response valid 

tbusy Fixed busy delay till DOUT data valid 1 7 

tEC Delay time, DOUT data invalid CS↑ 0 

tDB Data block size 1 

4.2.2. SPI Clock Timing 


CONFIDENTIAL 

0 

1 

16 Clock 

Cycles 

16 Clock 

Cycles 

16/32 Clock 

Cycles 

16 Clock 

Cycles 

16/32 Clock 

Cycles 

- 14-

Figure 8. SPI Clock Timing 

Table 6. SPI Timing requirement 



fclock Clock frequency, CLK 0 48 MHZ 

DC Low/high duty cycle 40 60 % 

tWL Pulse duration, CLK low 5 ns 

tWH Pulse duration, CLK high 5 ns 

tTLH Rise time, CLK 4.3 ns 

tTHL Fall time, CLK 3.5 ns 

tISU Setup time, input valid before CLK↑ 5 ns 

t1H Hold time, input valid after CLK↑ 5 ns 

tODLY1 Delay time, CLK↑ to output valid 4 15 ns 

TODLY2 Delay time, CLK↓ to output invalid 5 15 ns 

4.3. Bluetooth HCI Interface 

* STR: Start bit; D0…Dn: Data bits (LSB first); PAR: Parity bit (if parity is used); STP: Stop bit 


CONFIDENTIAL 

- 15-

Table 7. BT HCI Timing characteristics 


Characteristics Condition Symbol Min Typ. Max Unit 

Baud rate Any rate (1) 37.5 115.2 4000 kbps 

Baud rate accuracy Receive/Transmit t5/t7 -2.5to+1.5 % 

CTS low to TX_DATA on t3 0 2 us 

CTS high to TX_DATA off 

Hardware flow 

control 

t4 1 Byte 

CTS high pulse width t6 1 bit 

RTS low to RX_DATA on t1 0 2 us 

RTS high to RX_DATA off 

Interrupt set to 

1/4 FIFO 

(1) Exception for 19.2MHz: Maximum baud rate = 3.84Mbps. 

4.4. Bluetooth PCM Interface 

t2 16 Bytes 

Bluetooth can be setting as master or slave mode. For more stable 

voice performance, slave mode is recommended. 

Table 8. BT PCM Slave mode Timing characteristics 

Characteristics Symbol Min Typ. Max Unit 

Master clock frequency 1/t1 64 16000 KHz 

Clock duty cycle 40 50 60 % 


CONFIDENTIAL 

- 16-


Synchronization clock frequency 1/t3 1/(8xt1) 1/(65535xt1) KHz 

Synchronization signal width t1 165545xt1 

Setup time for AUD_FSYNC high to AUD_CLK 

low 

Hold time from AUD_CLK low to AUD_FSYNC 

low 

t2 5 ns 

t4 8 ns 

Setup time for AUD_IN valid to AUD_CLK low t8 5 ns 

Hold time from AUD_CLK low to AUD_IN 

invalid 

Delay time from AUD_CLK high to AUD_OUT 

data valid 

Delay time from AUD_CLK low to last data bit 

of AUD_OUT output set to high impedance 

t9 8 ns 

t5 20 ns 

t7 20 ns 


CONFIDENTIAL 

- 17-

5. Debug Interface 


The debug interface helps customers to evaluate the HW/SW features 

for their application. It also helps to debug during the development 

stage. The WG7310 module support RS232 signals and UART signals for 

debug purpose. Connect RS232 and UART signals to the test points for 

future debug support. 

5.1. WLAN RS232 Testing Port 

“Direct” serial interface (RS232_TX, RS232_RX) used by WLAN TrioScope 

software package for WLAN RF performance test, debug and 

manufacturing application. 

5.2. Bluetooth HCI Testing Port 

HCI_TX and HCI_RX are used by Bluetooth “HCI Tester” software 

package for Bluetooth RF performance test, debug and 

manufacturing application. 

Please reserve test pads for all test ports debug purpose. 


CONFIDENTIAL 

- 18-

Eng.Mang. 

WiFi Interface: SDIO or SPI 

BT Interface: UART, PCM 

FM Interface: UART (with BT together), 

I2S, Audio IN/OUT 

Fast Clock: 38.4MHz built-inside 

Slow Clock: 32.768KHz from outside 

and deep sleep 

WL_EN and BT_EN: Please attach a 3.3K ohm 

up to VIO_IN if no use 

Title 

WG7310-to-1V8 Host Reference Design 

Size Document Number Rev 

Custom 

WG7310R01 

R02 

Date: Monday , June 15, 2009 

Sheet 2 of 2 

VIO_IN: 1.62~1.92V => 1.8V TYP 

Slow Clock: 32.768KHz for module boot 

Name Date Sign 

Designer 

Approval 

Chief Eng. 

JORJIN TECHNOLOGIES INC. 

VBAT_IN: 2.3~4.8V => 3.3V TYP 

6. Reference Schematic 

Scheme Brief 

** Boot Conditions 

PCM_AUD_OUT_89 E5 

F5 

GND_90 

GND_91 G5 

GND_92 G6 

GND_93 G7 

F7 

GND_94 

GND_95 E7 

GND_96 E6 

R12 0R R0402 

BD_HCI_RTS_1V8 

BD_HCI_CTS_1V8 

GND_01 

WG7310-00 

A1 

VBAT_FEM_02 A2 

BT_FUNC2: BT_WU/ DC2DC_03 B1 

GND_04 B2 

BT_FUNC6: BT_SDA_05 C1 

BT_FUNC4: BT_TX_DBG_06 C2 

BT_FUNC5: HOST_WU_07 D1 

GND_08 D2 

GND_09 E1 

DRPWPABC_10 E2 

F1 

BT_RF_ANT_11 

F2 

GND_12 

GND_13 G1 

DRPWPDET_14 G2 

WL_TX_SW_15 H1 

GND_16 H2 

J1 

WL_BTH_SW_17 

J2 

WL_RX_SW_18 

GND_19 K1 

VCC_DCOW_20 K2 

L1 

NC_C3_21 

L2 

GND_22 

L3 

FM_EN_23 

VCC_RXW_24 K3 

L4 

GND_25 

BT_EN_26 K4 

L5 

WB_RF_ANT_27 

GND_28 K5 

L6 

GND_29 

WL_RS232_RX/ I2S_M_SCL_30 K6 

L7 

SDIO_D1_31 

WL_RS232_TX/ I2S_M_SDA_32 K7 

L8 

SDIO_D2_33 

SPI_CSX/ SDIO_D3_34 K8 

L9 

SPI_DIN/ SDIO_CMD_35 

SPI_DOUT/ SDIO_D0_36 K9 

L10 

SPI_CLK/ SDIO_CLK_37 

FM_I2S_FSYNC_38 K10 

L11 

WL_EN_39 

FM_SDA_40 K11 

J11 

FM_SCL_41 

J10 

FM_IRQ_42 

FM_I2S_CLK_43 H11 

FM_I2S_DI_44 H10 

FM_I2S_DO_45 G11 

GND_46 G10 

F11 

GND_47 

F10 

SLOWCLK_48 

FM_TX_ANT_49 E11 

GND_50 E10 

GND_51 D11 

FMAUDROUT_52 D10 

FM_RX_ANT_53 C11 

GND_54 C10 

GND_55 B11 

FMAUDLOUT_56 B10 

FMAUDRIN_57 A11 

GND_58 A10 

FMAUDLIN_59 A9 

GND_60 B9 

GND_61 A8 

XTALP_62 B8 

XTALM_63 A7 

GND_64 B7 

GND_65 A6 

BT_FUNC1: DC2DC/ btSPI_CLK_66 B6 

DC_REQ_67 A5 

TPS_DC2DC_68 B5 

VIO_69 A4 

1V8_70 B4 

VBAT_71 A3 

VDD_LDO_IN_CLASS1P5_72 B3 

PCM_AUD_CLK_73 D4 

PCM_AUD_IN_74 E4 

F4 

GND_75 

WL_PAEN_B_76 G4 

GND_77 H4 

VCC_ANAW_78 H5 

VCC_TXBW_79 H6 

WL_UART_DBG_80 H7 

CLK_REQ_OUT_81 H8 

WLAN_IRQ_82 G8 

F8 

HCI_RX/ btSPI_DIN_83 

HCI_TX/ btSPI_DOUT_84 E8 

BT_FUNC7: BT_SCL_85 D8 

HCI_RTS/ btSPI_IRQ_86 D7 

HCI_CTS/ btSPI_CS_87 D6 

PCM_AUD_FSYNC_88 D5 

BD_HCI_RTS 

BD_HCI_CTS 

BD_PCM_AUD_FSYNC 

BD_PCM_AUD_OUT 

TP7 Must be reserv ed f or test 




R9 0R R0402 

R10 0R R0402 

R11 0R R0402 

R19 

12K 

R0402 

BD_HCI_TX_1V8 

R118 

10K 

R0402 

GND 

BD_HCI_RX_1V8 

2 

O/P 3 

BD_HCI_RX 

BD_HCI_TX 

C10 1uF/NL C0402 

WD_UART_DBG 

WD_IRQ 


AS_VCC_ANAW 

AS_VCC_TXBW 

C9 1uF/NL C0402 

C17 

0.1uF 

CAP1005 

C18 

10nF 

CAP1005 

C19 

0.1uF 

CAP1005 

VIO_IN 

1V8 

OSC1 

KK3270022 

3.2X2.5MM 

1 

PD VDD 4 

BD_PCM_AUD_CLK 

BD_PCM_AUD_IN 

C7 

NL/2.2uF 

C0402 

C16 

0.1uF 

C0402 

C8 1uF/NL C0402 

VBAT_IN 

3V3 

U3 

TPS73618DBV 

SOT-23-5 

1 

3 

IN 

2 

EN 

GND NR/FB 4 

VBAT_IN 

VIO_IN 

3V3 1V8 

5 

OUT 

1V8 FM AUDIO 

C5 

1uF/NL 

C0402 

C6 

10uF/NL 

C0805 

32.768K XOSC 

1.8V LDO 

FA_AUD_IN_L 

VIO_IN 

VBAT_IN 

VBAT_IN 

1V8 3V3 

3V3 

FA_AUD_OUT_L 

FA_AUD_IN_R 

FA_RX_ANT 

FA_AUD_OUT_R 

FA_TX_ANT 

MD_SLOWCLK 

FD_I2S_CLK 

FD_I2S_DI 

FD_I2S_DO 



CONFIDENTIAL 

R2 

3.3K 

R0402 

1V8 FM I2S 

WB_RF_ANT 

WD_RS232_RX 

DS_SDIO_D1 

WD_RS232_TX 

DS_SDIO_D2 

DS_SPI_CSX 

DS_SPI_DIN 

DS_SPI_DOUT 

DS_SPI_CLK 

WD_EN 

VIO_IN 

DS_SDIO_D1 

R3 0R R0402 DS_SDIO_D1_1V8 

DS_SDIO_D2 R4 0R R0402 DS_SDIO_D2_1V8 

DS_SPI_CSX R5 0R R0402 DS_SPI_CSX_1V8 

DS_SPI_DIN R6 0R R0402 DS_SPI_DIN_1V8 

DS_SPI_DOUT R7 0R R0402 DS_SPI_DOUT_1V8 

DS_SPI_CLK R8 0R R0402 DS_SPI_CLK_1V8 

** It's recommended to insert 0 ohm resistors in WiFi SDIO/SPI 

pathes and keep them close to WG7310 module for test 

** The six traces from U1 ( module ) to Host must be 

treated like a bus. The bus length shall be as short 

as possible and every trace length must be the same as 

the others. Enough space above 1.5 time trace width or 

ground shielding between trace and trace will be benefit 

to make sure signal quality, especially for SDIO_CLK 

trace. Besides, please remember to keep them away from 

the other digital or analog signal traces. To add ground 

shielding to around the buses will be good. 

FD_I2S_FSYNC 



***** WiFi SDIO/SPI 

FM RF-OUT 

L2 

NL/120nH 

L0402 

L4 

12nH 

L0402 

2 

AS_VCC_RXW 

BD_EN 

C4 1uF/NL C0402 

R1 

3.3K 

R0402 

FA_TX_ANT 

1 

ANT3 

FMA0101 

24x5mm 

L3 

100nH 

L0402 

AS_VCC_DCOW 

AS_NC_C3 

C2 1uF/NL C0402 

C3 1uF/NL C0402 

VIO_IN 

FM RF-IN 

C15 

1nF 

C0402 

2 

FA_RX_ANT 

1 

ANT2 

FMA0101 

24x5mm 

BD_TX_DBG 

BD_HOST_WU 


TP3 Reserv ed f or host CPU which doesn't support UART wakeup 

8 

7 

3 

4 

L1 

NL 

L0402 

2 

WiFi/BT RF-I/O 


BD_WU 

WB_RF_ANT 

5 

1 

ANT1 

AT8010-E2R9HAA 

8x1mm 

C1 1uF/NL C0402 

SW1 

MM8430 

3x3mm 

6 

2 

1 

C13 

10pF 

C0402 

C14 

10pF 

C0402 

U1 

WG7310-00 

10x10mm 

WG7310-00 MODULE 

ANTENNA CIRCUITS 


( Preliminary-subject to change ) 

- 19-

Eng.Mang. 

Title 


Size Document Number Rev 

Custom 

WG7310R00 

R02 

Date: Friday , June 12, 2009 

Sheet 2 of 2 

Name Date Sign 

Designer 

Approval 

Chief Eng. 

JORJIN TECHNOLOGIES INC. 

WiFi Interface: SDIO or SPI 

BT Interface: UART, PCM 

FM Interface: UART (with BT together), 

I2S, Audio IN/OUT 

Fast Clock: 38.4MHz built-inside 

Slow Clock: 32.768KHz from outside 

VBAT_IN: 2.3~4.8V => 3.3V TYP 

VIO_IN: 1.62~1.92V => 1.8V TYP 

Slow Clock: 32.768KHz for module boot 

and deep sleep 

WL_EN and BT_EN: Please attach a 3.3K ohm 

up to VIO_IN if no use 

R118 

10K 

R0402 

R19 

12K 

R0402 

2 

GND 

O/P 

3 

OSC1 

KK3270022 

3.2X2.5MM 

1 

PD VDD 4 

C17 

0.1uF 

CAP1005 

C18 

10nF 

CAP1005 

C19 

0.1uF 

CAP1005 

C16 

0.1uF 

C0402 

Scheme Brief 

** Boot Conditions 

VBAT_IN 

3V3 

U3 

TPS73618DBV 

SOT-23-5 

1 

IN 

2 

GND 

EN 

VBAT_IN 

VIO_IN 

3V3 1V8 

5 

3 

OUT 

4 

NR/FB 

32.768K XOSC 

1.8V LDO 

PCM_AUD_OUT_89 E5 

F5 

GND_90 

GND_91 G5 

GND_92 G6 

GND_93 G7 

F7 

GND_94 

GND_95 E7 

GND_96 E6 

L2 

NL/120nH 

L0402 

L4 

12nH 

L0402 

2 

FA_TX_ANT 

FM RF-OUT 

1 

ANT3 

FMA0101 

24x5mm 

R11 0R R0402 

R12 0R R0402 

L3 

100nH 

L0402 







BD_HCI_TX_1V8 

R9 0R R0402 

R10 0R R0402 

BD_HCI_RX_1V8 

C9 1uF/NL C0402 

VIO_IN 

1V8 

WB_RF_ANT 

C5 

1uF/NL 

C0402 

FA_RX_ANT 

***** WiFi SDIO/SPI 

DS_SDIO_D1 

R3 0R R0402 DS_SDIO_D1_1V8 

DS_SDIO_D2 R4 0R R0402 DS_SDIO_D2_1V8 

DS_SPI_CSX R5 0R R0402 DS_SPI_CSX_1V8 

DS_SPI_DIN R6 0R R0402 DS_SPI_DIN_1V8 

DS_SPI_DOUT R7 0R R0402 DS_SPI_DOUT_1V8 

DS_SPI_CLK R8 0R R0402 DS_SPI_CLK_1V8 

** It's recommended to insert 0 ohm resistors in WiFi SDIO/SPI 

pathes and keep them close to WG7310 module for test 

** The six traces from U1 ( module ) to U2 ( level shifter ) 

and from U2 to Host must be treated like two buses. The 

bus length shall be as short as possible and every trace 

length must be the same as the others. Enough space above 

1.5 time trace width or ground shielding between trace 

and trace will be benefit to make sure signal quality, 

especially for SDIO_CLK trace. Besides, please remember 

to keep them away from the other digital or analog signal 

traces. To add ground shielding to around the buses will 

be good. 

E3 

GND 

D3 

GND 

E5 

GND 

E4 

GND 


GND_01 

WG7310-00 

A1 

VBAT_FEM_02 A2 

BT_FUNC2: BT_WU/ DC2DC_03 B1 

GND_04 B2 

BT_FUNC6: BT_SDA_05 C1 

BT_FUNC4: BT_TX_DBG_06 C2 

BT_FUNC5: HOST_WU_07 D1 

GND_08 D2 

GND_09 E1 

DRPWPABC_10 E2 

F1 

BT_RF_ANT_11 

F2 

GND_12 

GND_13 G1 

DRPWPDET_14 G2 

WL_TX_SW_15 H1 

GND_16 H2 

J1 

WL_BTH_SW_17 

J2 

WL_RX_SW_18 

GND_19 K1 

VCC_DCOW_20 K2 

L1 

NC_C3_21 

L2 

GND_22 

L3 

FM_EN_23 

VCC_RXW_24 K3 

L4 

GND_25 

BT_EN_26 K4 

L5 

WB_RF_ANT_27 

GND_28 K5 

L6 

GND_29 

WL_RS232_RX/ I2S_M_SCL_30 K6 

L7 

SDIO_D1_31 

WL_RS232_TX/ I2S_M_SDA_32 K7 

L8 

SDIO_D2_33 

SPI_CSX/ SDIO_D3_34 K8 

L9 

SPI_DIN/ SDIO_CMD_35 

SPI_DOUT/ SDIO_D0_36 K9 

L10 

SPI_CLK/ SDIO_CLK_37 

FM_I2S_FSYNC_38 K10 

L11 

WL_EN_39 

FM_SDA_40 K11 

J11 

FM_SCL_41 

J10 

FM_IRQ_42 

FM_I2S_CLK_43 H11 

FM_I2S_DI_44 H10 

FM_I2S_DO_45 G11 

GND_46 G10 

F11 

GND_47 

F10 

SLOWCLK_48 

FM_TX_ANT_49 E11 

GND_50 E10 

GND_51 D11 

FMAUDROUT_52 D10 

FM_RX_ANT_53 C11 

GND_54 C10 

GND_55 B11 

FMAUDLOUT_56 B10 

FMAUDRIN_57 A11 

GND_58 A10 

FMAUDLIN_59 A9 

GND_60 B9 

GND_61 A8 

XTALP_62 B8 

XTALM_63 A7 

GND_64 B7 

GND_65 A6 

BT_FUNC1: DC2DC/ btSPI_CLK_66 B6 

DC_REQ_67 A5 

TPS_DC2DC_68 B5 

VIO_69 A4 

1V8_70 B4 

VBAT_71 A3 

VDD_LDO_IN_CLASS1P5_72 B3 

PCM_AUD_CLK_73 D4 

PCM_AUD_IN_74 E4 

F4 

GND_75 

WL_PAEN_B_76 G4 

GND_77 H4 

VCC_ANAW_78 H5 

VCC_TXBW_79 H6 

WL_UART_DBG_80 H7 

CLK_REQ_OUT_81 H8 

WLAN_IRQ_82 G8 

F8 

HCI_RX/ btSPI_DIN_83 

HCI_TX/ btSPI_DOUT_84 E8 

BT_FUNC7: BT_SCL_85 D8 

HCI_RTS/ btSPI_IRQ_86 D7 

HCI_CTS/ btSPI_CS_87 D6 

PCM_AUD_FSYNC_88 D5 

BD_HCI_RTS 

BD_HCI_CTS 



FM RF-IN 

C15 

1nF 

C0402 

2 

BD_HCI_RX 

BD_HCI_TX 

FA_RX_ANT 

1 

ANT2 

FMA0101 

24x5mm 

C10 1uF/NL C0402 

WD_UART_DBG 

WD_IRQ 


AS_VCC_ANAW 

AS_VCC_TXBW 


BD_PCM_AUD_IN 

C7 

NL/2.2uF 

C0402 

8 

7 

3 

4 

L1 

NL 

L0402 

2 

WiFi/BT RF-I/O 

5 

1 

ANT1 

AT8010-E2R9HAA 

8x1mm 

C8 1uF/NL C0402 

SW1 

MM8430 

3x3mm 

6 

2 

1 

C13 

10pF 

C0402 

C14 

10pF 

C0402 

1V8 FM AUDIO 

C6 

10uF/NL 

C0805 

FA_AUD_IN_L 

VIO_IN 

VBAT_IN 

VBAT_IN ANTENNA 1V8 3V3 

3V3 

CIRCUITS 

** AUD_DIR = R26 NL, R27 0 ohm --> AUD_FSYNC and AUD_CLK from WG7310 to Host; 

AUD_DIR = R26 0 ohm, R27 NL --> AUD_FSYNC and AUD_CLK from Host to WG7310 

FA_AUD_OUT_L 

FA_AUD_IN_R 

FA_AUD_OUT_R 

R16 NL/0R 

R0402 

R17 0R 

R0402 


CONFIDENTIAL 

FA_TX_ANT 

MD_SLOWCLK 

VBAT_IN 

B4 

AUD_DIR A4 

FD_I2S_CLK 

FD_I2S_DI 

FD_I2S_DO 

MD_SLOWCLK 

R15 NL 

R0402 

F4 

R2 

3.3K 

R0402 

PCM_AUD_OUT_A G3 

SLOW_CLK_A G4 

BD_EN 

R14 0R/NL 

R0402 

BD_EN_1V8 

BD_HCI_RX_1V8 


BD_HCI_TX_1V8 


BD_PCM_AUD_IN 




MD_SLOWCLK_1V8 

LS 

WD_IRQ 

WD_EN 

R13 0R/NL 

R0402 

R20 0R/NL 

R0402 

C5 

D5 

B6 

C6 

C7 

B7 

A6 

A7 

D6 

D7 

E7 

E6 

G7 

F7 

G6 

F6 

F5 

A5 

B5 

G5 

E1 

CLK_REQ_A 

E2 

BT_ENABLE_A 

BT_UART_RX_A G1 

F1 

BT_UART_CTS_A 

BT_UART_TX_A G2 

F2 

BT_UART_RTS_A 

F3 

PCM_AUDIO_IN_A 

A3 

PCM_AUDIO_CLK_A 

B3 

PCM_AUDIO_F_SYNC_A 

WLAN_ENABLE_A D1 

WLAN_IRQ_A D2 

R1 

3.3K 

R0402 

VCCA C4 

VCCA D4 

B2 

SDIO_DATA0_A 

SDIO_DATA1_A C2 

SDIO_DATA2_A C1 

B1 

SDIO_DATA3_A 

A2 

SDIO_CMD_A 

A1 

SDIO_CLK_A 

** SDIO_D1 and SDIO_D2 shall be connected to 

GND if using SPI host interface 

** SDIO lines should be held high by the host 

U2 

TWL1200 

4.1x4.1mm 

VCCB 

VCCB 

SPI_DOUT/ SDIO_DATA0_B 

SDIO_DATA1_B 

SDIO_DATA2_B 

SPI_CSX/ SDIO_DATA3_B 

SPI_DIN/ SDIO_CMD_B 

SPI_CLK/ SDIO_CLK_B 

WLAN_ENABLE_B 

WLAN_IRQ_B 

CLK_REQ_B 

BT_ENABLE_B 

BT_UART_RX_B 

BT_UART_CTS_B 

BT_UART_TX_B 

BT_UART_RTS_B 

PCM_AUDIO_IN_B 

PCM_AUDIO_CLK_B 

PCM_AUDIO_F_SYNC_B 

PCM_AUD_OUT_B 

SLOW_CLK_B 

OE 

BD_PCM_AUD_OUT_3V3 

MD_SLOWCLK_3V3 

1V8 FM I2S 

FD_I2S_FSYNC 



BD_EN_3V3 

BD_HCI_RX_3V3 


BD_HCI_TX_3V3 


BD_PCM_AUD_IN_3V3 

BD_PCM_AUD_CLK_3V3 

BD_PCM_AUD_FSYNC_3V3 

VIO_IN 

DS_SPI_DOUT_1V8 

DS_SDIO_D1_1V8 


DS_SPI_CSX_1V8 

DS_SPI_DIN_1V8 

DS_SPI_CLK_1V8 

WD_EN_1V8 

WD_IRQ_1V8 

WD_EN_3V3 

WD_IRQ_3V3 

AS_VCC_RXW 

BD_EN 

WB_RF_ANT 

WD_RS232_RX 

DS_SDIO_D1 

WD_RS232_TX 

DS_SDIO_D2 

DS_SPI_CSX 

DS_SPI_DIN 

DS_SPI_DOUT 

DS_SPI_CLK 

WD_EN 

VIO_IN 

C4 1uF/NL C0402 

AS_VCC_DCOW 

AS_NC_C3 

C2 1uF/NL C0402 

C3 1uF/NL C0402 

DS_SPI_DOUT_3V3 



DS_SPI_CSX_3V3 

DS_SPI_DIN_3V3 

DS_SPI_CLK_3V3 

C11 0.1uF 

C0402 

C12 0.1uF 

C0402 

3V3 

BD_TX_DBG 

BD_HOST_WU 



VIO_IN 

1V8 

VBAT_IN 


BD_WU 

C1 1uF/NL C0402 

3V3 I/O to HOST 

U1 

WG7310-00 

10x10mm 

WG7310-00 MODULE 

TWL1200 1V8-to-3V3 LEVEL SHIFTER 

- 20- 


( Preliminary-subject to change )

7. Module Mechanical Outline 


WG7310 Bottom View Side View 

‧ Pin array = 11x11 

‧ Pin number = 96 pins 

‧ Bump pitch = 0.85mm 

‧ Bump diameter = 0.5mm 

WG7310 Bottom View 


CONFIDENTIAL 

- 21-

8. Layout Recommendation 

8.1. Recommended Bump Pad Design * 


Figure 9. Recommended Bump Pad Design 

COMMENT: 

SMD = Solder Mask Define 

S/M= Solder Mask 

B/P= Bump Pad 

8.2. Recommended Stencil Design * 

The bump pad size, it’s solder mask opening and the relevant stencil 

via diameter described in Section 8.1 and Section 8.2 shall be followed 

completely otherwise the module mounting yield rate couldn’t be 

insured. The recommended stencil via diameter is 570 um. 

8.3. Recommended Trace Layout 

� Digital Signals Layout 

� SDIO signals traces (CLK, CMD, D0, D1, D2 and D3) should 

be routed in parallel to each other and as short as possible. 

Every trace length must be the same as the others. Enough 

space above 1.5 time trace width or ground shielding 

between trace and trace will be benefit to make sure 

signal quality, especially for SDIO_CLK trace. 

Besides, to keep them away from the other digital or 

analog signal traces and to add ground plane around 

them are also recommended strongly. 


CONFIDENTIAL 

- 22-


� SDIO/SPI Clock, Audio Clock (PCM_AUD_CLK), FM I2S Clock 

(FM_I2S_CLK), FM I2C Clock (FM_SCL), these digital clock 

signals are a source of noise. Keep the traces of these 

signals as short as possible. Whenever possible, maintain a 

clearance around them. 

� RF Trace & Antenna 

� WB_RF_ANT and FM_RX_ANT are required as 50 ohm traces, 

and FM_TX_ANT is as 75ohm one. If 75 ohm is difficult to be 

achieved, FM_TX_ANT could be designed as 50 ohm also 

but the trace length between module to FM_TX_ANT 

matching circuit is recommended as short as possible. 

� Recommended 50ohm trace design for PCB layout 

Height Between L1 and L2 (H): 10.0 mil 

Trace (W): 14.3 mil 

(W1): 14.3 mil 

Thickness (T): 2.1 mil 

Separation (S): 10.0 mil 

Dielectric (Er): 4.3 

� Move all the high-speed traces and components far away 

from the antenna. 

� Check ANT vendor for the layout guideline and clearance. 

� Matching circuit layout should be as following figure. 


CONFIDENTIAL 

- 23-


� Power Trace 

� Power trace for VBAT should be 40mil wide. 1.8V trace 

should be 18mil wide. 

� Ground 

� Having a complete Ground and more GND vias under 

module in layer1 for system stable and thermal dissipation 

as following figure. 

� Have a complete Ground pour in layer 2 for thermal 

dissipation. 

� Increase the GND pour in the 1st layer, move all the traces 

from the 1st layer to the inner layers if possible. 

� Move GND vias close to the pad. 

� Slow Clock 

� FM RF module uses the 32-kHz clock, it is extremely 

important that the slow-clock trace not be routed next to 

any digital signals. 

� The slow clock trace should not be routed above or below 

digital signals on other layers. 


CONFIDENTIAL 

- 24-

9. SMT and Baking Recommendation 

9.1. Baking Recommendation 


� Baking condition: 

- Follow MSL Level 4 to do baking process. 

- After bag is opened, devices that will be subjected to reflow 

solder or other high temperature process must be 

a) Mounted within 72 hours of factory conditions


No. Item Temperature (°C) Time (sec) 

1 Pre-heat D1: 140 ~ D2: 200 T1: 80 ~ 120 

2 Soldering D2: = 220 T2: 60 +/- 10 

3 Peak-Temp. D3: 250 °C max 

Note: (1) Reflow soldering is recommended two times maximum. 

(2) Add Nitrogen while Reflow process: SMT solder ability will be 

better. 

� Stencil thickness: 0.13~ 0.15 mm (Recommended) 

� Soldering paste (without Pb): Recommended SENJU 

N705-GRN3360-K2-V can get better soldering effects. 


CONFIDENTIAL 

- 26-

10. History Change 

Revision Date Description 

R 0.1 2009/05/26 New release 


R 0.2 2009/07/13 Modify Storage/Operating Temperature Range, Pin out 

description & Reference Schematic 

R 0.3 2009/08/10 Update Section 6 Reference Schematic, Section 7 

Mechanical Figure for Pin1 indicator, Section 8.2 

Recommended Stencil Design, Section 9 Baking Condition. 


CONFIDENTIAL 

- 27-

Hardware Design Guide Revision 0.3 - elinux

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