SL811HS Embedded USB Host/Slave Controller
SL811HS Embedded USB Host/Slave Controller
SL811HS Embedded USB Host/Slave Controller
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<strong>SL811HS</strong><br />
DMA Read Cycle<br />
nDRQ<br />
tdckdr<br />
nDACK<br />
tdack<br />
tdakrq<br />
D0-D7<br />
tdaccs<br />
tddrdlo<br />
DATA<br />
tdhld<br />
nRD<br />
tdrdp<br />
SL811 SL811 DMA DMA READ Read Cycle CYCLE Timing TIMING<br />
Parameter Description Min. Typ. Max.<br />
tdack nDACK low 100 ns<br />
tddrdlo nDACK to nRD low delay 0 ns<br />
tdckdr nDACK low to nDRQ high delay 5 ns<br />
tdrdp nRD pulse width 90 ns<br />
tdhld Date hold after nDACK high 5 ns<br />
tddaccs Data access from nDACK low 85 ns<br />
tdrdack nRD high to nDACK high 0 ns<br />
tdakrq nDRQ low after nDACK high 5 ns<br />
trdcycle DMA Read Cycle Time 150 ns<br />
Note Data is held until nDACK goes high regardless of state of nREAD.<br />
Reset Timing<br />
nRST<br />
treset<br />
nRD or nWR<br />
tioact<br />
Reset Timing<br />
Parameter Description Min. Typ. Max.<br />
t RESET nRst Pulse width 16 clocks<br />
t IOACT nRst HIGH to nRD or nWR active 16 clocks<br />
Note Clock is 48 MHz nominal.<br />
Document 38-08008 Rev. *D Page 29 of 32<br />
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