SL811HS Embedded USB Host/Slave Controller

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<strong>SL811HS</strong> DMA Write Cycle nDRQ nDACK D0-D7 tdakrq tdack tdwrlo DATA tackrq nWR tdsu tdwrp tdhld tackwrh SL811 DMA DMA WRITE Write Cycle CYCLE TIMING Parameter Description Min. Typ. Max. tdack nDACK low 80 ns tdwrlo nDACK to nWR low delay 5 ns tdakrq nDACK low to nDRQ high delay 5 ns tdwrp nWR pulse width 65 ns tdhld Data hold after nWR high 5 ns tdsu Data set-up to nWR strobe low 60 ns tackrq NDACK high to nDRQ low 5 ns tackwrh NDACK high to nDRQ low 5 ns twrcycle DMA Write Cycle Time 150 ns Note nWR must go low after nDACK goes low in order for nDRQ to clear. If this sequence is not implemented as requested, the next nDRQ is not inserted. Document 38-08008 Rev. *D Page 28 of 32 [+] Feedback
<strong>SL811HS</strong> DMA Read Cycle nDRQ tdckdr nDACK tdack tdakrq D0-D7 tdaccs tddrdlo DATA tdhld nRD tdrdp SL811 SL811 DMA DMA READ Read Cycle CYCLE Timing TIMING Parameter Description Min. Typ. Max. tdack nDACK low 100 ns tddrdlo nDACK to nRD low delay 0 ns tdckdr nDACK low to nDRQ high delay 5 ns tdrdp nRD pulse width 90 ns tdhld Date hold after nDACK high 5 ns tddaccs Data access from nDACK low 85 ns tdrdack nRD high to nDACK high 0 ns tdakrq nDRQ low after nDACK high 5 ns trdcycle DMA Read Cycle Time 150 ns Note Data is held until nDACK goes high regardless of state of nREAD. Reset Timing nRST treset nRD or nWR tioact Reset Timing Parameter Description Min. Typ. Max. t RESET nRst Pulse width 16 clocks t IOACT nRst HIGH to nRD or nWR active 16 clocks Note Clock is 48 MHz nominal. Document 38-08008 Rev. *D Page 29 of 32 [+] Feedback
Page 1 and 2: SL811HS SL811HS Embedded USB Host/S
Page 3 and 4: SL811HS PLL Clock Generator Either
Page 5 and 6: SL811HS USB-A/USB-B Host Control Re
Page 7 and 8: SL811HS USB-A/USB-B Host Transfer C
Page 9 and 10: SL811HS Interrupt Enable Register [
Page 11 and 12: SL811HS Table 16. SOF Counter LOW A
Page 13 and 14: SL811HS Endpoint Control Registers
Page 15 and 16: SL811HS Control Register 1, Address
Page 17 and 18: SL811HS Current Data Set Register,
Page 19 and 20: SL811HS The diagram below illustrat
Page 21 and 22: SL811HS 48/28-Pin USB Host Controll
Page 23 and 24: SL811HS Package Markings (48-Pin TQ
Page 25 and 26: SL811HS DC Characteristics Paramete
Page 27: SL811HS I/O Read Cycle twr twrrdl n
Page 31 and 32: SL811HS Package Diagrams (continued

SL811HS Embedded USB Host/Slave Controller

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