SL811HS Embedded USB Host/Slave Controller

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<strong>SL811HS</strong> Bus Interface Timing Requirements I/O Write Cycle nWR twr twrhigh A0 D0-D7 twasu twdsu Register or Memory Address twahld twdhld twdsu DATA twdhld twcsu twshld nCS Tcscs See Note. I/O Write Cycle to Register or Memory Buffer Parameter Description Min. Typ. Max. t WR Write pulse width 85 ns t WCSU Chip select set-up to nWR LOW 0 ns t WSHLD Chip select hold time 0 ns After nWR HIGH t WASU A0 address set-up time 85 ns t WAHLD A0 address hold time 10 ns t WDSU Data to Write HIGH set-up time 85 ns t WDHLD Data hold time after Write HIGH 5 ns t CSCS nCS inactive to nCS* asserted 85 ns t WRHIGH NWR HIGH 85 ns Note nCS an be held LOW for multiple Write cycles provided nWR is cycled. Write Cycle Time for Auto Inc Mode Writes is 170 ns minimum. Document 38-08008 Rev. *D Page 26 of 32 [+] Feedback
<strong>SL811HS</strong> I/O Read Cycle twr twrrdl nWR A0 twasu twahld nRD trdp D0-D7 twdsu Register or Memory Address twdhld tracc DATA trdhld trcsu trshld nCS Tcscs *Note I/O Read Cycle from Register or Memory Buffer Parameter Description Min. Typ. Max. t WR Write pulse width 85 ns t RD Read pulse width 85 ns t WCSU Chip select set-up to nWR 0 ns t WASU A0 address set-up time 85 ns t WAHLD A0 address hold time 10 ns t WDSU Data to Write HIGH set-up time 85 ns t WDHLD Data hold time after Write HIGH 5 ns t RACC Data valid after Read LOW 25 ns 85 ns t RDHLD Data hold after Read HIGH 40 ns t RCSU Chip select LOW to Read LOW 0 ns t RSHLD NCS hold after Read HIGH 0 ns T CSCS * nCS inactive to nCS *asserted 85 ns t WRRDL nWR HIGH to nRD LOW 85ns Note nCS can be kept LOW during multiple Read cycles provided nRD is cycled. Rd Cycle Time for Auto Inc Mode Reads is 170 ns minimum. Document 38-08008 Rev. *D Page 27 of 32 [+] Feedback
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Page 5 and 6: SL811HS USB-A/USB-B Host Control Re
Page 7 and 8: SL811HS USB-A/USB-B Host Transfer C
Page 9 and 10: SL811HS Interrupt Enable Register [
Page 11 and 12: SL811HS Table 16. SOF Counter LOW A
Page 13 and 14: SL811HS Endpoint Control Registers
Page 15 and 16: SL811HS Control Register 1, Address
Page 17 and 18: SL811HS Current Data Set Register,
Page 19 and 20: SL811HS The diagram below illustrat
Page 21 and 22: SL811HS 48/28-Pin USB Host Controll
Page 23 and 24: SL811HS Package Markings (48-Pin TQ
Page 25: SL811HS DC Characteristics Paramete
Page 29 and 30: SL811HS DMA Read Cycle nDRQ tdckdr
Page 31 and 32: SL811HS Package Diagrams (continued

SL811HS Embedded USB Host/Slave Controller

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