SL811HS Embedded USB Host/Slave Controller
SL811HS Embedded USB Host/Slave Controller
SL811HS Embedded USB Host/Slave Controller
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<strong>SL811HS</strong><br />
Bus Interface Timing Requirements<br />
I/O Write Cycle<br />
nWR<br />
twr<br />
twrhigh<br />
A0<br />
D0-D7<br />
twasu<br />
twdsu<br />
Register or Memory<br />
Address<br />
twahld<br />
twdhld<br />
twdsu<br />
DATA<br />
twdhld<br />
twcsu<br />
twshld<br />
nCS<br />
Tcscs See Note.<br />
I/O Write Cycle to Register or Memory Buffer<br />
Parameter Description Min. Typ. Max.<br />
t WR Write pulse width 85 ns<br />
t WCSU Chip select set-up to nWR LOW 0 ns<br />
t WSHLD<br />
Chip select hold time<br />
0 ns<br />
After nWR HIGH<br />
t WASU A0 address set-up time 85 ns<br />
t WAHLD A0 address hold time 10 ns<br />
t WDSU Data to Write HIGH set-up time 85 ns<br />
t WDHLD Data hold time after Write HIGH 5 ns<br />
t CSCS nCS inactive to nCS* asserted 85 ns<br />
t WRHIGH NWR HIGH 85 ns<br />
Note nCS an be held LOW for multiple Write cycles provided nWR is cycled. Write Cycle Time for Auto Inc Mode Writes is 170<br />
ns minimum.<br />
Document 38-08008 Rev. *D Page 26 of 32<br />
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