SL811HS Embedded USB Host/Slave Controller

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SL811HS Table 35. 48-Pin TQFP AXC Pin No. 48/28-Pin TQFP AXC Pin Assignments and Definitions (continued) 28-Pin PLCC Pin No. Pin Type Pin Name Pin Description 33 25 BIDIR D6 Data 6. Microprocessor Data/Address Bus. 34 – NC NC No connection. 35 – NC NC No connection. 36 – NC NC No connection. 37 – NC NC No connection. 38 – NC NC No connection. 39 26 BIDIR D7 Data 7. Microprocessor Data/Address Bus. 40 27 IN M/S Master/Slave Mode Select. ’1’ selects Slave. ’0’ = Master. 41 28 [8] VDD +3.3 VDC Device V DD Power. 42 [9] 1 [9] IN A0 A0 = ’0’. Selects address pointer. Register A0 = ’1’. Selects data buffer or register. 43 2 IN nDACK DMA Acknowledge. An active LOW input used to interface to an external DMA controller. DMA is enabled only in slave mode. In host mode, the pin should be tied HIGH (logic ’1’). 44 3 OUT nDRQ DMA Request. An active LOW output used with an external DMA controller. nDRQ and nDACK form the handshake for DMA data transfers. In host mode, leave the pin unconnected. 45 4 IN nRD Read Strobe Input. An active LOW input used with nCS to read registers/data memory. 46 – NC NC No connection. 47 – NC NC No connection. 48 – NC NC No connection. Notes 8. VDD can be derived from the USB supply. Figure 5 on page 19 shows a simple method to provide 3.3V/30 mA. Another option is to use a Torex Semiconductor, Ltd. 3.3V SMD regulator (part number XC62HR3302MR). 9. The A0 Address bit is used to access address register or data registers in I/O Mapped or Memory Mapped applications. Document 38-08008 Rev. *D Page 22 of 32 [+] Feedback
SL811HS Package Markings (48-Pin TQFP) Part Number YYWW-X.X XXXX YYWW = Date code XXXX = Product code X.X = Silicon revision number Document 38-08008 Rev. *D Page 23 of 32 [+] Feedback
Page 1 and 2: SL811HS SL811HS Embedded USB Host/S
Page 3 and 4: SL811HS PLL Clock Generator Either
Page 5 and 6: SL811HS USB-A/USB-B Host Control Re
Page 7 and 8: SL811HS USB-A/USB-B Host Transfer C
Page 9 and 10: SL811HS Interrupt Enable Register [
Page 11 and 12: SL811HS Table 16. SOF Counter LOW A
Page 13 and 14: SL811HS Endpoint Control Registers
Page 15 and 16: SL811HS Control Register 1, Address
Page 17 and 18: SL811HS Current Data Set Register,
Page 19 and 20: SL811HS The diagram below illustrat
Page 21: SL811HS 48/28-Pin USB Host Controll
Page 25 and 26: SL811HS DC Characteristics Paramete
Page 27 and 28: SL811HS I/O Read Cycle twr twrrdl n
Page 29 and 30: SL811HS DMA Read Cycle nDRQ tdckdr
Page 31 and 32: SL811HS Package Diagrams (continued

SL811HS Embedded USB Host/Slave Controller

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