AVRÂ® STK501 User Guide - Atmel Corporation

STK501 

............................................................................. 

User Guide

Table of Contents 


Section 1 

Introduction ........................................................................................... 1-1 

1.1 Features....................................................................................................1-2 

Section 2 

Using the STK501 Top Module............................................................. 2-1 

2.1 Connecting the STK501 to the STK500 Starter Kit...................................2-1 

2.1.1 Placing an ATmega103(L) or ATmega128(L) on the STK500............2-1 

2.2 PORT Connectors.....................................................................................2-2 

2.2.1 PORT E/PORT F ................................................................................2-2 

2.2.2 PORT G/AUX .....................................................................................2-3 

2.2.2.1 PG0 - PG4 ...................................................................................2-3 

2.2.2.2 A16...............................................................................................2-3 

2.2.2.3 SRAMEN......................................................................................2-3 

2.2.2.4 PEN..............................................................................................2-3 

2.3 Programming the ATmega103(L)/ 128(L) .................................................2-3 

2.3.1 In-System Programming.....................................................................2-3 

2.3.2 High-voltage Programming.................................................................2-4 

2.4 JTAG Connector .......................................................................................2-5 

2.5 External SRAM .........................................................................................2-6 

2.5.1 A16 .....................................................................................................2-7 

2.5.2 SRAMEN ............................................................................................2-7 

2.6 Ram High Address Jumpers .....................................................................2-8 

2.7 A[7:0] Connector .......................................................................................2-8 

2.8 Using the SRAM Interface with AT90S/LS8515 and ATmega161 ............2-8 

2.9 TOSC Switch ............................................................................................2-9 

2.10 RS-232C Port............................................................................................2-9 

Section 3 

Troubleshooting Guide ......................................................................... 3-1 

Section 4 

Technical Specifications ....................................................................... 4-1 

Section 5 

Technical Support................................................................................. 5-1 

i


Section 6 

Complete Schematics........................................................................... 6-1 

ii

Section 1 

Introduction 

The STK501 board is a top module designed to add ATmega103(L) and ATmega128(L) 

support to the STK500 development board from Atmel Corporation. With this board the 

STK500 is extended to support all current AVR devices in a single development 

environment. 

The STK501 includes connectors, jumpers and hardware allowing full utilization of the 

new features of the ATmega128(L) while the Zero Insertion Force (ZIF) socket allows 

easy use of TQFP packages for prototyping. 

This user guide acts as a general getting started guide as well as a complete technical 

reference for advanced users. 

In addition to adding support for new devices, it also adds new support for peripherals 

previously not supported by the STK500. An additional RS-232 port and external SRAM 

interface are09/01 among the new features. Devices with dual UART or XRAM interface 

can all take advantage of the new resources on the STK501 board. 

Figure 1-1. STK501 Top Module for STK500 

AVR ® STK501 User Guide 1-1 

Rev. 2491A-09/01

Introduction 

1.1 Features STK500 Compatible 

AVR Studio ® Compatible 

 

Supports ATmega103(L) and ATmega128(L) 

 

Zero Insertion Force Socket for TQFP Packages 

 

TQFP Footprint for Emulator Adapters 

 

Supports all Added Features in ATmega128(L) 

 

JTAG Connector for On-chip Debugging Using JTAG ICE (ATmega128(L)) 

 

Additional RS-232C Port with Available RTS/CTS Handshake Lines 

Adds External SRAM Support to the STK500 Board (Usable for all Devices with 

 

XRAM Interface) 

On-board 32 kHz Crystal for Easy RTC Implementations 

 

1-2 AVR ® STK501 User Guide

Section 2 

Using the STK501 Top Module 

2.1 Connecting the 

STK501 to the 

STK500 Starter 

Kit 

The STK501 should be connected to the STK500 expansion header 0 and 1. It is important 

that the top module is connected in the correct orientation as shown in Figure 2-1. 

The EXPAND0 written on the STK501 top module should match the EXPAND0 written 

beside the expansion header on the STK500 board. 

Figure 2-1. Connecting STK501 to the STK500 Board 

Note: 

Connecting the STK501 with wrong orientation may damage the board. 

2.1.1 Placing an 

ATmega103(L) or 

ATmega128(L) on 

the STK500 

The STK501 contains both a ZIF socket, and the pinout for a TQFP package; which 

allows an easy way of soldering an emulator adapter directly into the STK501. Care 

should be taken so that the device (or adapter) is mounted with the correct orientation. 

Figure 2-2 shows the location of pin 1 for the ZIF socket and the TQFP footprint. 

Caution: Do not mount an ATmega103(L) or ATmega128(L) on the STK501 at the 

same time as an AVR is mounted on the STK500 board. 

AVR ® STK501 User Guide 2-1 

Rev. 2491A-09/01


Figure 2-2. Pin1 on ZIF Socket and TQFP Footprint 

2.2 PORT 

Connectors 

Since the ATmega103(L) and ATmega128(L) have additional ports not available on the 

STK500, these ports are located on the STK501 board. They have the same pinout and 

functionality as the ports on the STK500 board. Port A to Port D which are already 

present on the STK500 board are not duplicated on the STK501. 

2.2.1 PORT E/PORT F Figure 2-3 shows the pinout for the I/O port headers Port E and Port F. 

Figure 2-3. General I/O Ports 

PE0 

PE2 

PE4 

PE6 

GND 

1 2 

PORT E 

PE1 

PE3 

PE5 

PE7 

VTG 

PF0 

PF2 

PF4 

PF6 

GND 

1 2 

PORT F 

PF1 

PF3 

PF5 

PF7 

VTG 

Note: 

Port E is also present on the STK500, but only PE0 to PE2 (3 least significant 

bits) are accessible there. To access all Port E bits the connector on the 

STK501 must be used. 



2.2.2 PORT G/AUX In addition to the normal Port G pins, this connector has some extra signals. See Figure 

2-4. 

Figure 2-4. PORTG/AUX 

PG0 

PG2 

PG4 

SRAMEN 

GND 

2.2.2.1 PG0 - PG4 These are general I/O ports for the ATmega128(L) and connect to the ZIF socket and 

the TQFP footprint. The PG3 and PG4 signals are routed through the TOSC switch 

since these pins also are inputs for a 32 kHz oscillator. For a description on the TOSC 

switch see Section 2.9. 

Note: ATmega103(L) does not have Port G. 

2.2.2.2 A16 This line goes to A16 (most significant address bit) on the SRAM. See Section 2.5 for 

more information about this signal. can be connected to any AVR pin. 

2.2.2.3 SRAMEN The SRAMEN signal controls if the SRAM is enabled or not. To enable the SRAM a 

LOW level should be applied to this pin. See “External SRAM”, Section 2.5, for more 

information on how to use this signal. This signal is pulled high by default. 

2.2.2.4 PEN The PEN pin is connected to the PEN pin on the ATmega103(L)/128(L). This pin is 

described in the programming section of the ATmega103(L) and ATmega128(L) 

datasheets. 

1 2 

PG1 

PG3 

A16 

PEN 

VTG 

PORT G/AUX 

2.3 Programming the 

ATmega103(L)/ 

128(L) 

2.3.1 In-System 

Programming 

The ATmega103(L) and ATmega128(L) can be programmed using both SPI and Highvoltage 

Parallel Programming. This sub section will explain how to connect the programming 

cables to successfully use one of these two modes. The AVR Studio STK500 

software is used in the same way as for other AVR parts. 

Note: 

The ATmega128(L) also supports Self Programming. See AVR109 application 

note for more information on this topic. 

To program the ATmega103(L) or ATmega128(L) using ISP programming mode, connect 

the 6-wire cable between the ISP6PIN connector on the STK500 board and the ISP 

connector on the STK501 board as shown in Figure 2-5. 

The device can be programmed using the serial programming mode in the AVR Studio 

STK500 software. 

Note: 

See the STK500 User Guide for information on how to use the STK500 frontend 

software for ISP programming. 

AVR ® STK501 User Guide 2-3


Figure 2-5. In-System Programming 

2.3.2 High-voltage 

Programming 

To program the ATmega103(L) or ATmega128(L) using High-voltage (Parallel) Programming, 

connect the PROGCTRL to PORTD and PROGDATA to PORTB on the 

STK500 as shown in Figure 2-6. 

As described in the STK500 User Guide, the BSFL2 jumper must be mounted when 

High-voltage Programming ATmega devices. This also applies to the High-voltage Programming 

of ATmega103(L) and ATmega128(L). 

The device can now be programmed using the High-voltage Programming mode in AVR 

Studio STK500 software. 

Note: 

See the STK500 User Guide for information on how to use the STK500 frontend 

software in High-voltage Programming mode. 

Note: For the High-voltage Programming mode to function correctly, the target voltage 

must be higher than 4.5V. 

Caution: Make sure the SRAM (if mounted) can handle this voltage. 



Figure 2-6. High-voltage (Parallel) Programming 

2.4 JTAG Connector The JTAG connector is intended for the ATmega128(L) that has a built-in JTAG interface. 

The pinout of the JTAG connector is shown in Figure 2-7 and is compliant with the 

pinout of the JTAG ICE available from Atmel. Connecting a JTAG ICE to this connector 

allows On-chip Debugging of the ATmega128(L). 

More information about the JTAG ICE and On-chip Debugging can be found in the AVR 

JTAG ICE User Guide, which is available at the Atmel web site, www.atmel.com. 

Figure 2-7. JTAG Connector 

TCK 

TDO 

TMS 

VTG 

TDI 

1 2 

JTAG 

GND 

VTG 

RST 

NC 

GND 

Figure 2-8 shows how to connect the JTAG ICE probe on the STK501 board. 



Figure 2-8. Connecting JTAG ICE to the STK501 

2.5 External SRAM The STK501 contains a footprint where an external SRAM device can be mounted. 

Make sure the SRAM device has the same voltage range as the rest of the design. 

Caution: Special care should be taken if a low voltage SRAM is used, since High-voltage 

Programming requires a programming voltage higher than 4.5V. Low-voltage 

SRAM may be damaged if High-voltage Programming of the target AVR is done. 

Table 2-1 shows a list of recommended SRAM devices, and typical range of operation. 

It is important that the SRAM device is soldered with the correct orientation as shown in 

Figure 2-9. 

Note: 

The SRAM is disabled by default. To enable SRAM support, put a jumper 

between the SRAMEN and GND pin on the PORTG/AUX connector. 

Figure 2-9. Pin1 on SRAM Footprint and Pinout 

A0 

A1 

A2 

A3 

CS 

D0 

D1 

VCC 

GND 

D2 

D3 

WE 

A4 

A5 

A6 

A7 

1 

32 

2 

31 

3 

30 

4 

29 

5 

28 

6 

27 

7 

26 

8 

25 

128Kx8 

9 

24 

10 

23 

11 

22 

12 

21 

13 

20 

14 

19 

15 

18 

16 17 

A16 

A15 

A14 

A13 

OE 

D7 

D6 

GND 

VCC 

D5 

D4 

A12 

A11 

A10 

A9 

A8 



Table 2-1. Recommended SRAM Devices 

Manufacturer Part Number Supply Voltage (V) Package 

ISSI IS63LV1024-T 3.3 TSOP-II 

ISSI IS63LV1024-J 3.3 SOJ 300-mil 

ISSI IS63LV1024-K 3.3 SOJ 400-mil 

IDT IDT71124-Y 5.0 SOJ 400-mil 

IDT IDT71V124SA-TY 3.3 SOJ 300-mil 

IDT IDT71V124SA-Y 3.3 SOJ 400-mil 

IDT IDT71V124SA-PH 3.3 TSOP-II 

2.5.1 A16 The A16 pin on the PORTG/AUX connector is connected to A16 (address pin 16) on the 

SRAM. ATmega103(L) and ATmega128(L) support up to 60 KB of external SRAM. The 

STK501 SRAM footprint is for a 128 KB SRAM. Implementing software control of the 

A16 line will increase the memory range from 64 KB to 128 KB. This line is pulled low by 

default, addressing the lower 64 KB of the SRAM. 

Figure 2-10. SRAM Block Schematic 

AVR 

SRAM 

PORTC 

From 

PORTG/AUX 

connector 

A16 

SRAMEN 

PC7 

PC6 

PC5 

PC4 

PC3 

PC2 

PC1 

PC0 

RAM HIGH 

ADDRESS 

VTG 

A16 

A15 

A14 

A13 

A12 

A11 

A10 

A9 

A8 

10K x 12 

RD (PG1) 

WR (PG0) 

CE 

OE 

WE 

ALE (PG2) 

LE 

OE 

PA7 

PA6 

PA5 

PA4 

PA3 

PA2 

PA1 

PA0 

D7 

D6 

D5 

D4 

D3 

D2 

D1 

D0 

LATCH 

Q7 

Q6 

Q5 

Q4 

Q3 

Q2 

Q1 

Q0 

A7 

A6 

A5 

A4 

A3 

A2 

A1 

A0 

A0 

A2 

A4 

A6 

A[7:0] 

A1 

A3 

A5 

A7 

VTG 

A7 

A6 

A5 

A4 

A3 

A2 

A1 

A0 

A7 

A6 

A5 

A4 

A3 

A2 

A1 

A0 

D7 

D6 

D5 

D4 

D3 

D2 

D1 

D0 

PA7 

PA6 

PA5 

PA4 

PA3 

PA2 

PA1 

PA0 

PORTA 

2.5.2 SRAMEN The SRAMEN pin on the PORTG/AUX connector is connected to the Chip-enable (CE) 

pin of the SRAM. This signal controls if the SRAM should be enabled or not. To enable 

the SRAM, a low level should be applied to this pin. This pin is pulled high by default, 

through a 10 kΩ resistor. Figure 2-10 shows a simplified block schematic on how the 

SRAM interface is implemented. Figure 2-11 shows how to enable the SRAM by shorting 

SRAMEN and GND on the PORTG/AUX connector using one of the supplied 

jumpers. 

This signal can also be controlled by software or by some external control logic. 



Figure 2-11. SRAMEN Connected to GND 

2.6 Ram High 

Address 

Jumpers 

When External Memory is enabled in an AVR, all Port C pins are by default used for the 

high address byte. If the full 60 KB address space is not required to access the external 

memory, some, or all, Port C pins can be released for normal port pin function as 

described in the ATmega128(L) datasheet. AT90S/LS8515, ATmega103(L) and 

ATmega161 do not have this feature, and all jumpers should be connected if using the 

XRAM interface with these devices. 

If some or all of the Port C pins are released for normal port pin functions, the corresponding 

“RAM High Address” jumper should be removed to avoid any Port C activity to 

reach the SRAM address pins thus corrupting the address. 

If a jumper is removed, the corresponding address line will be pulled low giving a logic 

zero on that address bit on the SRAM. See the block schematic on Figure 2-10. 

2.7 A[7:0] Connector The connector marked A[7:0] contains the 8 least-significant bits of the external SRAM 

address bus. The purpose of the connector is to provide easy access to the address 

bus. The 8 most significant bits can be found on the “Ram High Addresses” jumpers or 

the Port C connector. 

The connector is placed after the latch as shown in Figure 2-10. 

This connector is handy when using the SRAM interface to interface external devices. 

2.8 Using the SRAM 

Interface with 

AT90S/LS8515 

and ATmega161 

When using the SRAM interface with devices placed in the STK500 board, some additional 

straps are required. The reason is that the RD, WR, and ALE signals are not on 

the same port pins for the AT90S8515/ATmega161(L) and ATmega103(L)/ 

ATmega128(L), so these signals must be routed manually using two of the 2-wire 

cables. 

Table 2-2. Signal Routing Required for AT90S8515A and ATmega161(L) 

Connections STK500 STK501 Description 

Write Signal WR PD6 PG0 Connect PD6:STK500 to PG0:STK501 

Read Signal RD PD7 PG1 Connect PD7:STK500 to PG1:STK501 

Address Latch Enable ALE PE1 PG2 Connect PE1:STK500 to PG2:STK501 



Figure 2-12. Enabling SRAM Interface for Devices in STK500 

2.9 TOSC Switch On the ATmega128(L) the TOSC1 and TOSC2 lines are shared with Port G (PG4 and 

PG3). The TOSC switch select if the 32 kHz crystal, or the Port G connector pins should 

be connected to the pins on the device. 

Figure 2-13 shows a simplified block schematic on how this is implemented. 

Note: Port G is not available on the ATmega103(L), the switch will thus only select if 

the 32 kHz crystal should be connected or not. 

Figure 2-13. TOSC Block Schematic 

AVR 

32 kHz 

PG3/TOSC2 

PG4/TOSC1 

TOSC 

Switch 

PG3 

PG4 

To 

PORT G/AUX 

Connector 

2.10 RS-232C Port The ATmega128(L) has an additional UART compared to the ATmega103(L). The RS- 

232 port on the STK501 board has in addition to the RXD and TXD lines support for 

RTS and CTS flow control. Figure 2-14 shows a simplified block schematic on how this 

is implemented. 

Note: 

The UART in ATmega128(L) does not support hardware RTS or CTS control. If 

such functionality is needed, it must be implemented in software. 



Figure 2-14. UART Block Schematic 

RS232 SPARE2 

4 

6 

2 

3 

7 

8 

5 

RS-232/Logic Level 

Converter 

RxD 

CTS 

TxD 

RTS 

This UART can also be used from devices placed in the STK500 board. Simply connect 

the appropriate port pins to RXD and TXD on the STK501 board. 

Note: 

If no software RTS/CTS flow control is implemented, a jumper shorting RTS and 

CTS will ensure correct communication with an external application that uses 

such flow control. 


Section 3 

Troubleshooting Guide 

Table 3-1. Troubleshooting Guide 

Problem Reason Solution 

SRAM does not work 

properly. 

SRAM does not work when 

used by devices on the 

STK500 board. 

After doing a High-voltage 

Programming of the AVR, the 

SRAM does not work 

properly. 

The SRAM is not connected. 

SRAMEN is not mounted. 

XRAM interface is not 

enabled in the AVR device. 

Some of the ADDRESS 

HIGH BYTE jumpers may be 

set incorrectly. 

WR, RD and ALE signals 

must be strapped using two 

2-wire cables. 

The SRAM might be 

damaged due to the Highvoltage 

needed to program 

the AVR. 

Verify all solderings, and 

make sure the Pin1 on the 

SRAM matches the one on 

the footprint. Make sure the 

SRAM pinout is correct. 

Make sure that the SRAMEN 

is connected to GND on the 

AUX connector. 

Verify that the code actually 

enables the XRAM interface. 

Connect some or all of 

ADDRESS HIGH BYTE 

jumpers. 

Use two 2-wire cables, and 

connect these signals to the 

appropriate pins. 

Make sure the SRAM 

handles 5V, if High-voltage 

Programming mode should 

be used. 


Troubleshooting Guide 


Section 4 

Technical Specifications 

System Unit 

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 x 119 x 27 mm 

Weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 g 

Operating Conditions 

Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V - 5.5V 

Connections 

Serial Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-pin D-SUB female 

Serial Communications Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 kbps 


Technical Specifications 


Section 5 

Technical Support 

For Technical support, please contact avr@atmel.com. When requesting technical support, 

please include the following information: 

Which target AVR device is used (complete part number) 

Target voltage and speed 

Clock source and fuse setting of the AVR 

Programming method (ISP or High-voltage) 

Hardware revisions of the AVR tools, found on the PCB 

Version number of AVR Studio. This can be found in the AVR Studio help menu. 

PC operating system and version/build 

PC processor type and speed 

A detailed description of the problem 


Technical Support 


Section 6 

Complete Schematics 

On the following pages the complete schematics and assembly drawing of the STK501 

revision B are shown. 



Figure 6-1. Schematics, 1 of 3 

D 

C 

B 

A 

1 

2 

3 

4 

5 

6 

7 

8 

TQFP Footprint 

ZIF Socket 

GND VTG 

GND VTG 

PAT[7..0] 

PAT[7..0] 

PFT[7..0] PFT[7..0] 

PAT[7..0] 

PFT[7..0] PFT[7..0] 

PAT[7..0] 

PET[7..0] PET[7..0] PET0 

PET1 

PET2 

PET3 

PET4 

PET5 

PET6 

PET7 

PBT0 

PBT1 

PBT2 

PBT3 

PBT4 

PBT5 

PBT6 

PCT[7..0] 

PCT[7..0] 

PBT7 

TOSC2 

PDT[7..0] 

PBT[7..0] PBT[7..0] TOSC2 

PDT[7..0] 

TOSC1 

TOSC1 

TOSC1 

XT1 

TOSC1 

XT1 

RESET RESET XT2 

RESET RESET 

XT2 

PGT[4..0] PGT[4..0] 

STK501 Page of 1 3 

A9903.3.1010.B 

Rev. B 

19-Jun-2001 

Copyright Atmel Corporation 2001 

1 2 3 4 5 6 7 8 

D 

C 

B 

A 

PAT0 

PAT1 

PAT2 

PAT3 

PAT4 

PAT5 

PAT6 

PAT7 

PCT7 

PCT6 

PCT5 

PCT4 

PCT3 

PCT2 

PCT1 

PCT0 

PGT2 

PGT1 

PGT0 

PDT0 

PDT1 

PDT2 

PDT3 

PDT4 

PDT5 

PDT6 

PDT7 

PFT0 

PFT1 

PFT2 

PFT3 

PFT4 

PFT5 

PFT6 

PFT7 

AREFT AREFT 

AREFT 

AREFT 

PEN 

PEN 

PEN GND 

PEN 

GND 

PAT0 

PAT1 

PAT2 

PET[7..0] PET[7..0] PET0 

PET1 

PET2 

PET3 

PET4 

PET5 

PET6 

PET7 

PBT0 

PBT1 

PBT2 

PBT3 

PBT4 

PBT5 

PBT6 

PAT3 

PAT4 

PAT5 

PAT6 

PAT7 

PCT7 

PCT6 

PCT5 

PCT4 

PCT3 

PCT2 

PCT1 

PCT0 

PCT[7..0] 

PCT[7..0] 

PGT2 

PGT1 

PGT0 

AVTG 

C108 

100N_16V_X7R 

PBT7 

TOSC2 

PDT[7..0] 

PBT[7..0] PBT[7..0] TOSC2 

PDT0 

PDT1 

PDT2 

PDT3 

PDT4 

PDT5 

PDT6 

PDT7 

PFT0 

PFT1 

PFT2 

PFT3 

PFT4 

PFT5 

PFT6 

PFT7 

AVTG 

1 

PEN 

2 

3 

PE0/PDI/RXD 

PE1/PDO/TXD 

4 

PE2/AC+ 

5 

6 

PE3/AC- 

PE4/INT4 

7 

PE5/INT5 

8 

9 

PE6/INT6 

10 PE7/INT7 

11 PB0/SS 

12 PB1/SCK 

13 PB2/MOSI 

14 PB3/MISO 

15 PB4/OC0 

PB6/OC1B 

16 PB5/OC1A 

AD3/PA3 48 

AD4/PA4 47 

AD5/PA5 46 

AD6/PA6 45 

AD7/PA7 44 

ALE/PG2 43 

A15/PC7 42 

A14/PC6 41 

A13/PC5 40 

A12/PC4 39 

A11/PC3 38 

A10/PC2 37 

36 

A9/PC1 

35 

A8/PC0 

RD/PG1 

34 

33 

WR/PG0 

PDT[7..0] 

VTG GND 

VTG GND 

PGT[4..0] PGT[4..0] 

VTG AVTG 

1 L101 2 

BLM-21A102S 

2 

1 

1 

1 

1 

1 

1 

C101 

100N_16V_X7R 

C102 

100N_16V_X7R 

C105 

100N_16V_X7R 

C106 

100N_16V_X7R 

2 

2 

2 

17 

18 

19 

20 

21 

22 

23 

24 

25 

26 

27 

28 

29 

30 

31 

32 

PB7/OC2 

PG3/TOSC2 

PG4/TOSC1 

RESET 

VCC 

GND 

XTAL2 

XTAL1 

PD0/INT0 

PD1/INT1 

PD2/INT2 

PD3/INT3 

PD4/IC1 

PD5 

PD6/T1 

PD7/T2 

AVCC 

AGND 

AREF 

ADC0/PF0 

ADC1/PF1 

ADC2/PF2 

ADC3/PF3 

ADC4/PF4 

ADC6/PF6 

ADC6/PF6 

ADC7/PF7 

GND 

VCC 

AD0/PA0 

AD1/PA1 

AD2/PA2 

64 

63 

62 

61 

60 

59 

58 

57 

56 

55 

54 

53 

52 

51 

50 

49 

U101 

ATMEGA128 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

48 

47 

46 

45 

44 

43 

42 

41 

40 

39 

38 

37 

36 

35 

34 

33 

17 

18 

19 

20 

21 

22 

23 

24 

25 

26 

27 

28 

29 

30 

31 

32 

49 

50 

51 

52 

53 

54 

55 

56 

57 

58 

59 

60 

61 

62 

63 

64 

ST101 

TQFP64 ZIF SOCKET 

C103 

100N_16V_X7R 

C104 

100N_16V_X7R 

2 

2 

2 

1 

1 

C107 

100N_16V_X7R 

2 

GND 

GND 

GND 




D 

C 

B 

A 

8 

2 

3 

4 

5 

6 

7 

1 

PET[7..0] 

PET[7..0] 

XT1 

XT2 

RESET 

VTG 

GND 

RESET 

PET1 

PCT7 

PCT5 

PCT3 

PCT1 

PAT7 

PAT5 

PAT3 

PAT1 

AREFT 

PET2 

PET0 

PCT6 

PCT4 

PCT2 

PCT0 

PAT6 

PAT4 

PAT2 

PAT0 

GND 

AREFT 

GND 15 16 

GND VTG 

XT1 

17 18 XT2 

VTG 

19 20 

21 22 

PBT7 

23 24 PBT6 

VTG 

GND 

PBT5 

25 26 PBT4 

C202 

PBT3 

27 28 PBT2 

100N_16V_X7R 

PBT1 

29 30 PBT0 

PDT7 

31 32 PDT6 

PDT5 

33 34 PDT4 

GND 

PDT3 

35 36 PDT2 

PDT1 

37 38 PDT0 

39 40 

GND 

GND EXPAND0 GND 

GND EXPAND1 GND 

PAT[7..0] 

PDT[7..0] 

PAT[7..0] 

PDT[7..0] 

PCT[7..0] PCT[7..0] 

PBT[7..0] PBT[7..0] 

PET1 

PET0 

VTG 

GND 

2 

4 

6 

J206 

VCC 

MOSI 

GND 

1 

MISO 

SCK 3 

5 

RESET 

ISP_CONNECTOR 


A9903.3.1010.B 

Rev. B 

19-Jun-2001 


1 2 3 4 5 6 7 8 

D 

C 

B 

A 

PBT1 

2 

2 

1 

1 

C201 

100N_16V_X7R 

R203 

0R 

PFT4 

PFT6 

PFT5 

PFT7 

VTG 

J204 

1 2 

3 4 

5 6 

7 8 

9 10 

JTAG 

RESET 

GND 

1 

GND 

VTG 

VTG 

C203 

100N_16V_X7R 

2 

2 

1 

GND 

RESET 

VTG 

GND 

C204 

100N_16V_X7R 

PFT[7..0] 

PGT[4..0] 

A[7..0] 

PFT[7..0] 

PGT[4..0] 

A[7..0] 

J203 

J205 

J208 

J207 

PFT0 1 2 PFT1 

PET0 1 2 PET1 

PGT0 1 2 PGT1 

A0 1 2 A1 

PFT2 3 4 PFT3 

PET2 3 4 PET3 

PGT2 3 4 PGT3 

A2 3 4 A3 

PFT4 5 6 PFT5 

PET4 5 6 PET5 

PGT4 5 6 

A16 

A4 5 6 A5 

A16 

PFT6 7 8 PFT7 

PET6 7 8 PET7 

SRAMEN 

7 8 

A6 7 8 A7 

SRAMEN 

GND 

9 10 

VTG 

GND 

9 10 

VTG 

GND 

9 10 

VTG 

VTG 

GND 

9 10 

VTG 

PORTF PORTE 

JS201 JS202 

PORTG/AUX LATCHED ADDRESS 

R201 

10K 

Port G special features 

PG0: nWR 

PEN 

PG1: nRD 

PEN 

PG2: ALE 

1 2 

1 2 

NOT MOUNTED 

1 2 

GND 

R202 

0R 

J201 

1 2 

3 4 

5 6 

7 8 

9 10 

11 12 

13 14 

15 16 

17 18 

19 20 

21 22 

23 24 

25 26 

27 28 

29 30 

31 32 

33 34 

35 36 

37 38 

39 40 

J202 

1 2 

3 4 

5 6 

7 8 

9 10 

11 12 

13 14 

PG3: TOSC2 

PG4: TOSC1 




D 

C 

B 

A 

8 

2 

3 

4 

5 

6 

7 

1 

A[7..0] 

A[7..0] 

U301 74AHC573PW 

1 

OE 

11 

LE Q0 19 

Q1 18 

2 

D0 Q2 17 

3 

D1 Q3 16 

4 

D2 Q4 15 

5 

6 

D3 Q5 14 

D4 Q6 13 

7 

D5 Q7 12 

8 

9 

D6 

D7 


A9903.3.1010.B 

Rev. B 

19-Jun-2001 


1 2 3 4 5 6 7 8 

D 

C 

B 

A 

10 

GND 

VCC 

20 

PCT[7..0] 

PGT[4..0] 

PCT[7..0] 

PGT[4..0] 

GND 

PAT0 

PAT1 

PAT2 

PAT3 

PAT4 

PAT5 

PAT6 

PAT7 

VTG 

GND 

A0 

A1 

A2 

A3 

A4 

A5 

A6 

A7 

PCT0 

PCT1 

PCT2 

PCT3 

PCT4 

PCT5 

PCT6 

PCT7 

VTG 

A0 

A1 

A2 

A3 

A4 

A5 

A6 

A7 

A8 

A9 

A10 

A11 

A12 

A13 

A14 

A15 

A16 

PAT0 

PAT1 

PAT2 

PAT3 

PAT4 

PAT5 

PAT6 

PAT7 

PGT0 

PGT1 

PGT2 

A16 

VTG 

C301 

100N_16V_X7R 

A16 

JS301 JS302 JS303 JS304 JS305 JS306 JS307 JS308 

PAT[7..0] 

PAT[7..0] 

VTG 

VTG 

2 

1 

16 

2 1 

J301 

10 

GND 

1 

6 

2 

7 

3 

8 

4 

9 

5 

11 

C303 

100N_16V_X7R 

2 

1 

1 2 

2 

1 

GND 

JP301 

1 2 

3 4 

5 6 

7 8 

9 10 

11 12 

13 14 

15 16 

VTG 

C302 

100N_16V_X7R 

1 2 

R301 

10K 

R302 

10K 

R303 

10K 

R304 

10K 

R305 

10K 

R306 

10K 

R307 

10K 

R308 

10K 

R309 

10K 

GND 

1 2 

1 2 

1 2 

1 2 

1 2 

1 2 

1 2 

1 2 

1 2 

2 

1 

SRAMEN 

SRAMEN 

GND 

R310 

10K 

U302 

1 

2 A0 

3 A1 

4 A2 

13 A3 

14 A4 

15 A5 

16 A6 

17 A7 

18 A8 

19 A9 

20 A10 

21 A11 

29 A12 

30 A13 

31 A14 

32 

A15 

A16 

5 

28 

CE 

12 OE 

WE 

I/O0 

I/O1 

I/O2 

I/O3 

I/O4 

I/O5 

I/O6 

I/O7 

128Kx8 SRAM 

VTG 

2 R312 1 

10K 

VTG 

2 R313 1 

10K 

6 

7 

10 

11 

22 

23 

26 

27 

VCC 8 

VCC 24 

GND 9 

GND 25 

VTG 

GND 

2 

14 

13 

7 

8 

6 

U303 

C1+ 1 

V+ C1- 3 11 

T1 

12 

R1 

10 

T2 

9 

R2 

V- C2+ 4 

XC301 

C305 

3 2 

100N_16V_X7R 

4 1 

SW301 

TOSC 

32kHz 

1 

TOSC2 

2 

TOSC2 

3 

PGT3 

6 

J302 

TOSC1 

5 

TOSC1 

RXD 1 2 TXD 

4 

PGT4 

CTS 3 4 RTS 

KF22-E-9-S-N 

GND 

C304 

100N_16V_X7R 

RS232 SPARE2 

C306 

GND 

100N_16V_X7R 

JS309 

7 

VCC 

C2- 5 

MAX3232ECAE 

15 

GND 

2 

1 

1 R311 2 

33R 

C308 

10P_50V_NP0 

GND 

RAM HIGH 

ADDRESS 

GND 

GND 

PGT[4..0] PGT[4..0] 

VTG 

C307 

1 2 

GND 

100N_16V_X7R 



Figure 6-4. Assembly Drawing, 1 of 1 




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Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty 

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors 

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does 

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AVRÂ® STK501 User Guide - Atmel Corporation

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