3D Wafer-Level - Yole Developpement

3D 

ISSUE N°20 

SEPTEMBER 2011 

Packaging 

Magazine on 3DIC, TSV, WLP & Embedded die Technologies 

FEATURE STORIES 

Derivative packaging 

roadmaps and 

applications 

Courtesy of awaiba - Printed on recycled paper 

COMPANY INSIGHT 

3D-IC challenges: 

design with test 

(Part 1/2) 

200μm 

WHAT’S INSIDE 

3D Wafer-Level- 

Packaging of MEMS 

gyroscope sensor 

with VTI’s CMR3000 

Free subscription on www.i-micronews.com

Technology and supply chain challenges 

for fabless semiconductor companies 

Fabless semiconductor companies constantly face the challenge of designing 

competitive products which can easily be manufactured by their manufacturing 

partners with good yields. Comprehensive access for their design, test and 

quality engineers to the design rules and guidelines is key to implement the 

required design for manufacturability (DfM) practices. 

This becomes even more critical with the ever widening array of IC packaging 

technologies and solutions: how to make the right package platform choice for 

a given product What is the most optimized trade-off between electrical and 

thermal performance, power consumption, reliability, size, manufacturability 

and cost of the packaged integrated circuit How to find the right manufacturing 

partners for the chosen technology to minimize risks and costs Should the 

technology choices influence the choice of the manufacturing partners, or should 

it be the other way round How to access the latest 3D and wafer level packaging 

technologies with controlled risks and without cost penalties How can fabless 

companies also influence the evolution and road mapping of the semiconductor 

packaging and test industry 

These are the hot questions Serma Technologies and Yole Développement 

propose to debate through a dedicated event jointly organized in Paris 

on November 8 to 10, 2011 with invited presentations by worldwide 

industrial players of both large global companies and SMEs. 

For more information, please contact: 

• S. Leroy, Yole Développement (leroy@yole.fr) 

• B. Crouillère, Serma Technologies (b.crouillere@serma.com) 

Successful 

Semiconductor 

Fabless 2011 

November 8 to 10 

Crowne Plaza, Paris, France

S E P T E M B E R 2 0 1 1 I S S U E N ° 2 0 

E D I T O R I A L 

Innovation and technology diversity management 

in semiconductor packaging 

Back from the Semicon West show in San Francisco, it has now become crystal clear 

that 3D is the number one topic and concern in most semiconductor executives’ 

minds. I said “semiconductor executives”, not “semiconductor packaging executives”! 

Of course, the development of 22nm-CMOS is moving forward and 450mm diameter wafers 

are back on the agendas. But no other topic scored even close to 3D silicon integration in 

terms of numbers of dedicated workshops, presentations or exhibition booth totems with the 

“3D” and “TSV” keywords at Semicon West July 12-14 in San Francisco. 

…More surprisingly 

3D interposers 

made of silicon or 

glass are confirmed 

as a high potential 

and expected lasting 

trend… 

3D Integration of memory stacks by means of through silicon vias is a confi rmed big trend. 

Same is true for integration of the same stacks on top of a logic IC to enable the so-called 

“wide I/O interface” concept for high bandwidth data transfers between the logic part and 

the DDR memories. Maybe more surprisingly are 3D interposers made of silicon or glass 

confi rmed as a high potential and expected lasting trend of the industry by several prominent 

speakers, whereas one year ago, they were still only considered as a stepping stone to “full 

3D integration” and accordingly referred to as “2.5D integration”. 

The “why’s” of 3D now all return consensual positive answers and many “how’s” are being 

answered with ready-for-production solutions. However some challenges still need to be 

addressed, and many agree that more alignment is needed between the industrial players so 

as to defi ne standards. Such consortia or standardization committees as Sematech, Semi or 

Jedec call for standard wafer thinning, design and test technologies or procedures and they 

work toward this goal so as to industrialize solutions with good yields in the future. 

Does this mean that all industrial solutions should result from agreed standards to succeed 

Nothing would be so untrue, especially concerning the historically and still currently super 

wide array of technology options in the semiconductor packaging industry. Whereas some 

of the past issues of “3D Packaging” focused on the need for standardization, we decided to 

focus this August issue to those application areas where diversity and differentiation through 

innovation still prevail. Welcome to the diverse packaging and assembly world of MEMS, 

LEDs, camera modules and high power chips… a world, which by the way, once invented 

“Through Silicon Vias”! 

E V E N T S 

• Semicon Taiwan 

September 7 to 9, 2011 – Taipei, Taiwan 

• Itnl Wafer Level Packaging Conference 

October 3 to 6, 2011 – Santa Clara, CA - USA 

Jean-Marc Yannou 

Project Manager 

Yole Développement 

yannou@yole.fr 

• Semicon Europa 

October 11 to 13, 2011 – Dresden, Germany 

PLATINUM PARTNERS: 

3 D P a c k a g i n g 3


C O N T E N T S 

INDUSTRY REVIEW 6 

• Off-roadmap’ apps show natural affinity for 3D packaging 

COMPANY INSIGHT 12 

• Tong Hsing Electronic Industries: Carving out a ‘niche’ in custom 

microelectronics packaging 

• Excico ultra-fast laser annealing solutions reach thermal constraint 

specifications for BSI and 3DIC 

• Unisem: Cavity packages for volume MEMS applications 

• Cadence & GSA Global: 3D-IC challenges: design with test (Part 1/2) 

ANALYST CORNER 24 

• Lower costs targeted for HB LED Packaging 

• Smartphones morph into sophisticated sensing platforms 

WHAT’S INSIDE 28 

• 3D Wafer-Level-Packaging of MEMS gyroscope sensor 

with VTI’s CMR3000 

EVENT REVIEW 30 

• Advanced Packaging: leading edge technologies bring challenges 

and opportunities 

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INDUSTRY REVIEW 

2 axis MEMS accelerometer 

to ASIC module assembly 

(Courtesy of Freescale) 

Some ‘off-roadmap’ apps show 

natural affinity for 3D packaging 

Off-roadmap applications like MEMS, image sensors, power components, and LEDs 

are outpacing the growth of traditional ICs. As a result, this may usher in a bold new 

era of innovation in creating packaging solutions to meet the needs of off-roadmap 

apps. This, in turn, will likely prove to be beneficial for more ‘traditional’ ICs too. 

Opportunities are clearly emerging in offroadmap 

applications, if you take a look 

at forecasts in this area. Yole estimates 

for 2015 put the MEMS market in excess of $17B; 

the CMOS image sensor/camera module market at 

$13B; the power module market at $4.4B; and the 

packaged LED market at $21.6B. 

Affinity for 3D packaging 

Some off-roadmap applications appear to have a 

natural affinity for 3D packaging technologies. A close 

look at MEMS, in particular, reveals an undeniable 

tie to 3D packaging. As Tomas Bauer, vice 

president of sales and business development at Silex 

Microsystems, sums it up: 3D packaging technologies 

are “genetically close” to MEMS technologies. 

“We’ve seen a lot of the 3D pioneering work done 

by the MEMS manufacturers,” notes Bauer. TSV, for 

example, is a key component of the 3D technologies, 

and Silex began supplying commercial parts with 

integrated full-wafer-thickness TSVs to a leading 

mobile phone manufacturer as early as 2006. 

MEMS devices inherently need 3DIC capabilities to 

marry MEMS + IC, explains Peter Himes, Silex’s 

vice president of marketing and strategic alliances. 

As a result, MEMS companies began implementing 

these technologies many years in advance of CMOSonly 

foundries. 

But the first to actually turn 3D packaging into a 

practice and make volume products was image 

sensor packaging, points out Martin Wäny, CEO 

6 

3 D P a c k a g i n g

I S S U E N ° 2 0 S E P T E M B E R 2 0 1 1 

decreases, we can go build BGAs instead. It 

just makes more sense in terms of capex and 

the flexibility of the production lines.” 

need for substrate preparation work—separate 

from the IC manufacturing, which enables 3D 

packaging. 

Fly on NanEye (Courtesy of Awaiba) 

and head of CMOS design at Awaiba. Image 

sensors have a natural gravitation to 3D 

packaging technologies too. 

Ultimately, whoever takes the product to 

market and interfaces with the end customer 

and understands their needs will define the 

packaging ideas of 3D or its alternatives, says 

Heinz Ru, vice president of Marketing and 

Innovation at Tong Hsing Electronic Industries, 

a company that specializes in a wide range of 

off-roadmap applications. “3D is a new trend, 

but in microelectronics packaging, the market 

is very competitive and no one can afford 

to have ideas or solutions that don’t revolve 

around cost. Technologies must be selected 

out of necessity—not just because it’s a sexy 

new idea—to justify choosing it.” 

Focus on cost/flexibility/existing 

solutions 

Cost and flexibility are two of the most 

critical factors for off-roadmap apps. Both are 

extremely important but, in this down economy 

and increasingly competitive landscape, the 

focus is on keeping costs as low as possible. 

And it’s important to note that not everyone is 

rushing to 3D packaging, but rather focusing 

on making modifications to existing platforms. 

Amkor is also focusing on cost and flexibility. 

“The recent explosive adoption of MEMS 

and sensors in consumer handheld products 

has required a transition to lower-cost 

MEMS package and test solutions. Amkor 

is responding to this market transition by 

providing low-stress and cavity package 

derivative solutions that borrow from existing 

high-volume leadframe and laminate-based 

package platforms,” says Russell Shumway, 

senior manager of MEMS & Sensor Products at 

Amkor. 

Impact on business 

models/supply chain 

A wide variety of business models are being 

used for off-roadmap packaging applications— 

everything from MEMS foundries to packaging 

houses. And the associated supply chains are 

also undergoing an evolution of sorts. 

Looking at the big picture, Ru cautions that this 

is an “emerging, dynamic market,” one that 

requires a flexible mindset. He recommends 

taking advantage of proven technologies. 

“Don’t try to create everything yourself; it isn’t 

possible. Look at the resources available in the 

market and connect the dots.” 

Silex sees a trend emerging in which IC players 

are considering pursuing some share of the 

evolving market in the ‘mid-end’ segment, 

capturing larger share of the total value chain. 

“At the same time, we’ve seen a continued 

separation of manufacturing and IC packaging. 

MEMS players already have 3D genes and 

should be in a good position to capture some 

share of this evolving market,” says Bauer. 

Another trend, Himes points out, is that the 

MEMS foundries are filling a ‘mid-end foundry’ 

Wäny expects specialty foundries to take over 

the lead in the future. “Currently, only a few 

packaging houses are active in this area— 

mainly in image sensor packaging and for 

relatively standardized work,” he says. “A lot of 

the substrate work will eventually come from 

the specialty foundries that need to supply a 

one-stop shop also for power electronics or 

MEMS. LED manufacturers will likely set up 

large-scale productions for TSV 3D-like LED 

packaging.” 

From an OSAT perspective, business model 

innovation is critical when integrating devices 

from different suppliers in 3D packages for highvolume 

applications. “We’re seeing a strong 

fabless MEMS industry emerge because MEMS 

foundries and MEMS package assembly and 

test can be cost-effectively outsourced in high 

volumes—meeting aggressive time-to-market 

requirements,” says Lee Smith, vice president 

of marketing and business development at 

Amkor. He expects the trend to fabless and fab 

light business models to continue to escalate, 

because application-specific device design and 

integration are differentiating factors, and 

critical mass is required to develop and invest 

in these capital-intensive wafer-level process 

technologies. 

And not surprisingly, for LEDs, in terms of their 

supply chain, much like the rest of the offroadmap 

apps, everything remains undecided 

and has yet to unfold. “There are several 

companies mastering the complete LED supply 

chain, including Samsung, Cree, Nichia, 

Sharp, OSRAM, and Philips Lumileds. But there 

is little standardization in this industry, and a 

lot of surprising things can happen down the 

road—especially if bold technology choices are 

Key components of a packaged LED 

(Yole Développement, LED Packaging 2011 report) 

Right now, most companies aren’t investing 

in costly capital equipment for new processes 

unless it’s absolutely necessary, says Alan 

Evans, Unisem Europe’s head of engineering. 

“The idea is that it’s better to do variations on 

a theme, so we have MEMS packaging that 

can run down QFN and BGA processing lines,” 

he explains. “As MEMS volumes increase, it’s 

easy to increase the capacity because we have 

a lot of that equipment already. If volume 

3 D P a c k a g i n g 

7


“Right now nonstandard 

apps are 

growing faster 

than the traditional 

IC market,” 

explains Lee Smith, 

Amkor Technology. 

Integrating Silex Microsystems’ 

TSV technology into MEMS systems 

enables reduced form factor and 

true wafer-level packaging solutions 

(Courtesy of Silex) 

made,” notes Yole’s Jean-Marc Yannou, technology 

and market expert in the field of advanced packaging. 

“Innovation is needed to provide differentiation and 

drive costs down. Companies who dare to invest, 

to reduce costs, need to be bold. Established 

companies likely won’t be the ones pushing it, since 

they’re happy with the market as it is. We’ll probably 

see challengers attempt to take over market share, 

especially based on packaging technologies.” 

Off-road apps impact on 3DIC packaging 

roadmaps 

What roles are companies seeing off-roadmap apps 

play in driving the semiconductor IC packaging 

roadmap for 3DICs/WLP 

As Smith points out: Right now non-standard apps 

are growing faster than the traditional IC market, 

so the result is that more attention is being paid 

to look at ways to apply 3D packaging platform 

technologies. 

Wäny views off-roadmap markets as still being 

important technology drivers, since they have a 

real added value in 3D packaging and most of the 

standard (memory) applications see the cost benefit. 

In terms of MEMS, there’s an inherent need for 

heterogeneous integration, so the market drivers 

are different than standard ICs, according to 

Himes. “That said, IC needs are driving toward a 

different plateau in terms of density, complexity, 

and technology (wafer thickness, number of vias, 

etc.),” he adds. “So while the applications in MEMS 

are different than ICs and the resulting topography 

may look different, much of the development being 

driven by MEMS will benefit CMOS in the long run.” 

The overall off-roadmap market is evolving at a 

rapid pace, notes Ru. “The typical approach to 3D 

packaging is too dynamic for MEMS,” he adds. “But 

you can still use the different 3D processes such as 

TSVs or other packaging solutions like stacked die by 

flip chip—there are many avenues. People can pick 

and choose to create their own custom packages.” 

Off-roadmap apps and volumes take off 

Standard ICs have a clear path: 3D. “If you drive the 

technology node another 10 years, it will probably 

reach its physical limits,” explains Ru. “3D is 

necessary to increase performance. Intel, Samsung, 

and TSMC are all investing heavily in R&D. They have 

equipment suppliers who help out and—especially 

for legacy processes that are no longer considered 

leading-edge—like to promote alternative uses.” He 

recommends that emerging applications in MEMS or 

power devices or image sensors look at processes 

maybe 3 to 5 years behind the leading-edge 

companies and then try to leverage it to create new 

package ideas. 

From Wäny’s perspective, at the moment, the cost 

calculation for the standard electronics is a difficult 

challenge for 3D packaging, but for image sensors it 

appears there might be some functional advantages 

to using 3D stacking or packaging. 

Unisem hasn’t seen 3D packaging emerge yet as a 

requirement for MEMS, according to Evans, although 

he believes it’s a technology MEMS will use. “Systemin-package 

is what we’re using now for pressuresensor-type 

MEMS,” he explains. “What’s new is 

we’re using embedded passives in substrates and 

embedded silicon substrates to reduce the footprint 

and cost of the overall application. We view MEMS 

packaging as a key growth area for the future, so 

if demand for 3D technologies picks up, we’ll jump 

on it. We’ll take a serious look at it when there’s 

some volume and legitimate business to go after, but 

right now we’re not seeing any customer demand for 

anything too exotic.” 

Off-road convergence with 3D/WLP 

Wondering how off-road applications are converging 

with WLP/3D or how they’re diverging with exotic 

substrates such as ceramics and metals 

Smith believes the greatest convergence is with 

emerging wafer-level processing for 3D package 

architectures with TSV interconnects—in which new 

wafer-level processes are critical to achieving high 

volumes and cost-effective components. 

Evolution is going in both directions, notes Bauer. 

“The wafer-based technologies available today— 

glass or silicon—come at a cost that’s difficult to 

justify and they might have problems competing 

with non-silicon alternatives,” he explains. “Waferbased 

processing, however, holds a heritage of 

offering repeatable production at high yield for smallfeature-size 

structures. As the race for smaller form 

factor continues, these technologies may eventually 

become the preferred choice for commercially viable 

implementation into their respective markets.” 

Himes views substrate and packaging choices as 

decoupled decisions in technology development. 

“What services the customers’ needs in base 

technology may not be what drives decisions in 

terms of packaging,” he explains. “That said, end 

applications may dictate both package and substrate 

requirements. In the end it’s application driven and 

the substrate and package are part of the same 

technology platform decision.” 

For LEDs, old IC packaging technologies were 

initially adopted. “But they weren’t efficient in terms 

of performance or cost,” notes Yannou. “Innovation 

was needed. This is being done with substrates and 

assembly processing techniques—interconnects, 

phosphor deposition, and lens formation. In the 

8 



SSB Wirebond 

(optional) 

SSB Wirebond 

(optional) 

Std. Wirebond 

Die 1 (MEMS) 

Die 2 (ASIC) 

Metal Shield 

Std. Wirebond 

Laminate Substrate 

MEMS Die Cap 

(optional) 

Top Die (stack) 

Bottom Die 

Metal 

Shield 

Laminate Substrate 

Example of what’s inside 3D MEMS 

(Courtesy of Amkor) 

long run this will greatly benefit the entire 

IC industry. While it looks like a very offroad 

market, it’s integrated into the complete 

picture of the semiconductor industry, in which 

there are exchanges back and forth between 

LED packaging and IC packaging.” 

Ru and Yannou both point out an emerging LED 

trend: A shift from leadframes and alumina 

substrates to aluminum nitride substrates for 

greater conductivity. “We’re seeing leadframes 

used less and less for LED substrates, because 

they’re bulky and don’t provide the lowest 

possible thermal resistance,” says Yannou. “For 

the same reason alumina is being phased out 

by another material for ceramics: Aluminum 

nitride, which only a year ago was reserved for 

high-end devices.” 

Final test and calibration 

Like nearly everything else, final test and 

calibration remains largely up in the air in 

terms of who’s going to do what and how. 

There are many different options. 

Silex expects final test and calibration for 

MEMS to follow a path parallel to that of the IC 

industry. “The wafer fab will do wafer-level die 

testing and ship the known good die for final 

package and test,” says Bauer. 

Amkor says that it’s pursuing the final test 

and calibration space. According to Shumway, 

the unique challenge of MEMS testing is 

introducing controlled environmental or 

mechanical stimulus. “For example, inertial 

sensors require shaker or flip systems. Optical 

stimulus, pressure, acoustic generators, and 

magnetic fields are applied to various sensors 

independently—more recently tied together for 

the emerging integrated sensor products,” he 

says. “We can offer competitive solutions when 

the stimulus can be implemented into mature 

tester and handler systems.” 

Previously, MEMS test was considered an 

integral and proprietary part of the total product 

solution that it was protected strongly at the 

IDM level. But that trend is changing, Shumway 

notes, and it’s being driven by economics. 

“You can see from the favored packaging 

platforms that there’s a shift from ceramicbased 

hermetic low-volume-type platforms to 

these very-high-volume QFN and fine-pitch 

BGA platforms,” he adds. “Both exceeded 20 

billion units in the market last year, so it’s a 

huge scale. More MEMS suppliers are looking to 

OSATs for the package technology, as well as 

turnkey assembly and test.” 

Other emerging off-roadmap apps 

Microfluidics and solar apps are also two 

key emerging areas, with many companies 

expressing an interest in them. 

Unisem is one of these companies. “We have 

some interesting projects involving microfluids 

and solar-type packaging,” says Evans. 

“They’re a little like MEMS in that they’re 

not a conventional package, but they are die 

attached and wire bonded or flip chipped, so 

can be constructed on a variation of a theme. 

Interest is escalating in these two newer areas 

and we’re excited about packages we’re being 

asked to design.” 

Innovation 

In the grand scheme of things, there’s plenty of 

room for innovation in packaging solutions for 

off-road apps—both using existing platforms 

and eventually 3D—and it appears that it will 

take time to sort out the chaos surrounding the 

supply chain and to determine who’s going to 

do what. 

Cost will play a definitive role in off-roadmap 

packaging, replacing performance as the most 

critical driver. This should help spur innovation 

in all areas. In terms of 3D packaging, it seems 

likely that we’ll see MEMS and image sensors 

head in that direction ahead of other offroadmap 

apps like LEDs, which seem a little 

less inclined to 3D integration. 

Broad Range of Package Solutions 

Focused Platforms 

and Applications 

Transition from 

Custom MEMS Packaging to 

High Volume Manufacturing 

MicroLeadFrame ® Cavity 

ChipArray ® Cavity 

MicroLeadFrame ® Molded 

Digital Light Processing 

Photo courtesy of Texas Instruments 

ChipArray ® Molded 

MEMS transition: this figure shows Amkor’s transition from custom MEMS packaging to high-volume manufacturing (Courtesy of Amkor) 


9


Most interesting, perhaps, is how it’s all tied together: Any innovation 

that takes place in packaging for off-roadmap apps can ultimately 

benefit other more “traditional” ICs as well. 

Sally Cole Johnson for yole Développement 

Tomas Bauer, Vice President of Sales and Business 

Development, Silex Microsystems 

He is responsible for deploying strategies in the sales of 

complex technical solutions and manufacturing services. 

Joining Silex in 2004, Bauer has played a key role in 

shaping its global foundry business strategy, as well as making significant 

contributions to the overall growth of the company. 

Alan Evans, Head of engineering, Unisem Europe 

He has worked in semiconductor assembly and test for 

more than 20 years. He is responsible for all package and 

process development activities at Unisem. Evans has set 

up various production lines, such as BGA and QFN, and for 

the last 4 years has been working on the design and implementation of 

MEMS packaging production capability. He earned a degree in Electrical & 

Electronic Engineering from the University of the West of England. 

Peter Himes, Vice President of Marketing and Strategic 

Alliances, Silex Microsystems 

He has more than 25 years’ experience in the semiconductor 

and technology fields, both in IC and MEMS industries. Prior 

to his last position as president of QuickSil, a specialty 

provider of semiconductor and MEMS foundry services, he held executive 

and leadership positions in sales, marketing, and business development 

at National Semiconductor, Winbond, SiTime, and a number of Silicon 

Valley startups. 

Heinz Ru, Vice President, Tong Hsing Electronic 

Industries 

He has been with the company for more than 30 years. 

He started in 1976 and an engineer and has worked 

in engineering, operations, sales, marketing, and new 

business development. Ru holds an MBA degree from National Chiao Tung 

University, and a bachelors degree in electrical engineering from National 

Taiwan University. 

Russell Shumway, Senior Manager of MEMS & Sensor 

Products, Amkor Technology. 

He is responsible for product platform and business 

development of MEMS & Sensor assembly and test 

solutions. 

Lee Smith, Vice President of Marketing and Business 

Development, Amkor Technology. 

He’s responsible for new business development, product and 

strategic marketing at Amkor. Smith is an industry expert in 

3D packaging, with nearly 30 years of diverse technology 

and market development experience. 

Martin Wäny, CEO and head of CMOS design 

and Founder, Awaiba. 

Awaiba holds key IP in advanced packaging and optics 

technologies that enable the world’s smallest digital image 

sensors. Wäny earned a degree in microelectronics and 

physics at the University of Neuchâtel, Switzerland in 1997. 

Jean-Marc Yannou, Project Manager of Advanced 

Packaging, Yole Developpement. 

He joined Yole in 2009 as a technology and market expert 

in the fields of advanced packaging and system integration. 

Yannou worked for Texas Instruments and Philips, where he 

served as Innovation Manager for System-in-Package technologies. He is 

also the president of IMAPS in France. 

10 


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Carving out a ‘niche’ in custom 

microelectronics packaging 

Tong Hsing Electronic Industries Ltd. knows a little something about the custom 

microelectronics manufacturing business. In fact, it’s spent the past 35 years 

amassing a wide array of IP building blocks, which the Taiwan-based company 

leverages to tailor special “recipes” for the widely varied and specific needs of its 

customers. 

Heinz Ru, Vice President, 

Tong Hsing Electronic 

Industries 

Tong Hsing is known primarily for its contract 

manufacturing of microelectronic packaging 

and fabrication of thick- and thin-film 

ceramic substrates. However, Tong Hsing has a 

wide range of other special technology solutions 

and capabilities that include module substrates 

for LEDs, RF modules for cellphones, system-inpackage 

(SiP) technologies, unique packaging 

solutions for MEMS and CMOS image sensor 

devices, reconstructed semiconductor wafers, chip 

probing and final test, PCB assembly, automotive 

hybrids, thin film on alumina and aluminum nitride 

(AlN), and thick film on alumina. 

Tong Hsing’s strategy is to pursue niche markets 

with high barriers to entry, markets where they 

can create a unique solution, “custom fitting the 

shoe to the customer,” so to speak. Working with 

startups is a key part of their business strategy. 

While far and away the majority of these startups 

fails (80 to 90%), as is unfortunately common in 

the niche areas, the investment in the 10 to 20% 

that succeed has enabled the company to grow 

along with them. 

Heinz Ru, vice president of Marketing and 

Innovation says: “Our strategy is to avoid very 

mature or commoditized technologies. For 

commercial projects there’s always a narrow time 

window for implementation—6 to 18 months. But if 

you’re a startup trying to put all the pieces together 

in this timeframe, you have no chance. We’ve been 

gathering the core technology building blocks, 

have the experience and reliability data, and have 

already learned the difficult lessons. Tong Hsing 

knows its ‘building blocks’ inside and out and can 

reorganize and reassemble them quickly—greatly 

increasing the odds of our startup partners being 

among that 10 to 20%.” 

The company doesn’t work exclusively with startups, 

it also works with industry giants such as Texas 

Instruments, Delphi, National Semiconductor, 

Skyworks, and many more. 

Headquartered in Taipei, Taiwan, Tong Hsing has 

manufacturing facilities located both in Taiwan and 

the Philippines. Ru is quick to point out that having 

a very capable, stable workforce such as theirs 

helps ensure quality. And the company’s resources 

“Tong Hsing’s 

strategy is to 

pursue niche 

markets with 

high barriers 

to entry,” 

says Heinz Ru, 

THEIL. 

HB LED ceramic substrate (Courtesy of Tong Hsing Electronics Industries) 

12 



are always prepared in advance; for example, 20% 

more capacity is always available just in case it’s 

needed. 

High power LED 

RF communication 

Off the roadmap trends 

As the company is involved in many “off the 

roadmap” technologies, Tong Hsing offers a unique 

perspective on emerging trends and areas of 

future growth. 

CERAMICS REVIVAL 

One of the most interesting trends Tong Hsing 

is witnessing now is a ceramics revival. “Ceramic 

substrates used to be a big industry for us, but it 

shrank rapidly after the 1990s,” says Ru. “Surprisingly, 

we’re seeing many industries beginning to switch 

over from mainstream technologies to ceramics. For 

example, LEDs are now using ceramic substrates as a 

Level 1 packaging solution to interface with the chip. 

About 8 years ago we thought our ceramic business 

was dying, but now all kinds of new applications are 

popping up. Another example is solid oxide fuel cells, 

where the heart of the cell operates at 800° to 850°C 

to reach the desired efficiency. What material can 

reduce that temperature Ceramic. It’s extremely 

fortunate for us that we didn’t decide to shut down 

that business.” 

LEDS 

Among the trends emerging in the LED area are: 

a shrinking substrate size; a shift in high growth 

market segments experiencing growth; a shift from 

lower thermal performance alumina substrates 

to higher thermal performance aluminum nitride 

substrates; and strong market pressure to reduce 

cost, similar to what happened in PA modules for 

handsets. 

These PA modules that used to be 10x10 mm 

are shrinking down to 6x6, 4x4, and 3x3 mm, 

so the substrates are shrinking as well. The LED 

substrates are taking the same path to shrink the 

size to reduce the cost, explains Ru. 

He’s also seeing the backlight market flattening 

out. “Growth, especially for LED TV segments 

has slowed quite a bit,” he adds. “Even though 

the penetration rate is greater, because of the 

efficiency and other material improvements, fewer 

units are being used in each LED TV. The next area 

of growth we’re expecting is for general lighting, 

and for this growth we need to drive more power 

into the die and chip.” 

Thermal performance also needs to improve, so 

there’s a fast-paced trend of moving from alumina 

substrates to aluminum nitride substrates. Last 

year, a mere 1% of Tong Hsing’s substrate sales 

were for aluminum nitride, while 99% were for 

alumina. Now, they’re seeing a big change: 20% 

Solar cell 

Electrical vehicule 

Application of DPC substrate (Courtesy of Tong Hsing Electronics Industries) 

aluminum nitride, 80% alumina. Ru expects this is 

a trend that will continue. 

Another trend is that customers are looking for ways 

to reduce LED costs quickly, because the current 

pricing of LED light fixtures is too expensive. Even 

with the shift to aluminum nitride substrates, the 

cost remains prohibitively high. “Aside from the 

LED area, the aluminum nitride industry was built 

on high-power, high-frequency communication 

applications, as well as laser diodes,” says Ru. 

“Neither of these require many aluminum nitride 

substrates, so they can afford the high cost— 

based on the volume they use. But for LEDs it’s 

different. Today, the standard thermal conductivity 

of aluminum nitride is 170, while alumina is only 

20. Our customers are telling us that they need 

conductivity in the range of 120 to 140. They can 

only afford a solution that costs much less than 

they’re currently paying now. We believe that with 

this volume increasing, someone will come up with 

a good solution.” 

MEMS 

As for MEMS trends, stress is still a big issue 

for certain applications, so ceramics are used in 

pressure sensors. Many MEMS devices are used in 

automotive applications, which are highly corrosive 

environments, so ceramic is preferred for that too. 

CAMERA MODULES 

In camera modules, to shrink the thickness, flip 

chip is the solution. Many of the high-resolution 

smartphone camera modules are using goldto-gold 

interconnects (GGI) and ceramics. “The 

reason for this is that the GGI puts high pressure 

on the substrate at a high temperature. PCBs 


13


become soft at high temperatures and aren’t reliable, so they’re 

going back to the reliable ceramics,” explains Ru. 

PACKAGING TRENDS 

One interesting packaging trend Tong Hsing is watching emerge 

is how the business models are changing in the off-the-roadmap 

packaging market. “It’s still largely a question of who’s going to 

play Who’s going to win marketshare Which technologies will 

prevail” points out Ru. For now, he says it’s difficult to guess and 

that having a flexible mindset is necessary since nothing is set in 

stone yet. “We work closely with the product, and discover who 

owns the IP, who understands the market, and who has the best 

connections with end-customers—we essentially figure out who can 

help put us in the driver’s seat. In offering custom-made services, 

we share some of the profits.” 

Ru believes that basically, if you’re a packaging house just focusing 

on a narrow segment of the process, for example, such as focusing 

on die attach wire bond or plastic bonding, you can certainly survive, 

but the future won’t be as bright. “To really thrive, it is critical to 

look at emerging requirements,” he adds. “We see potential in LEDs 

and concentrated photovoltaic, which we expect to grow. We also 

expect power modules for motor drives or inverters to grow.” 

Growth ahead 

Tong Hsing is viewing a rapid increase in activity going on in power 

electronics right now, so the company plans to direct more resources 

into that area. The company is also interested in fuel cells, as well 

as biomedical devices, and is actively working on related projects in 

these areas. “These are relatively new technologies,” Ru notes. “The 

markets are still quite small and it may take several years to evolve, 

but we’re willing to make the investment now.” 

Among Tong Hsing’s top goals for this year are: becoming the 

leading foundry service provider of RF modules, SiP, and MEMS 

packaging in Asia Pacific; continued expansion of the production 

scale of thin-film DPC substrates used in HB LEDs, solar cells, and 

electric vehicles; a ramp-up in production of ultraHB LEDs used in 

projectors; an expansion into the commercial aircraft industry; an 

expansion into fuel cells; a ramp-up of medical electronic circuit 

production; and a continued expansion in the production scale of 

image sensors, which includes chip probing, wafer reconstruction, 

assembly and final test. 

As Tong Hsing has discovered, finding and embracing these off-theroadmap 

niches can really pay off. 

www.theil.com 

Heinz Ru, Vice President, Tong Hsing Electronic Industries 

He has been with the company for more than 30 years. He started in 

1976 and an engineer and has worked in engineering, operations, sales, 

marketing, and new business development. Ru holds an MBA degree 

from National Chiao Tung University, and a bachelors degree in electrical 

engineering from National Taiwan University. 

14 




Excico ultra-fast laser annealing 

solutions reach thermal constraint 

specifications for BSI and 3DIC 

Increasing complexity of 3D stacks as well as BSI CMOS Image Sensors has haled 

equipment manufacturers to develop new solutions to provide fast annealing 

without degrading active layers and interconnects. In this new issue, Julien 

Venturini, Marketing Director of Excico, presents the benefits of Laser Thermal 

Annealing (LTA) especially for BSI application and shares his feelings about drivers 

and motivations for this emerging technology in semiconductor wafer processing. 

Yole Développement: Could you present to our 

readers the activity and products of Excico 

Julien Venturini: Excico is a European company 

supplying annealing equipment to the semiconductor 

and photovoltaic industry. Today organized globally 

with support with a worldwide footprint, our company 

supplies the semiconductor industry with the most 

scalable annealing technologies and solutions. The 

company activity and mission is to fulfill a gap in the 

ultrafast annealing solutions required in present and 

future process flows of semiconductor foundry and 

IDM’s. 

wafers backside annealing. This was the first time 

that a semiconductor fab was processing wafers with 

a melt-mediated annealing process. We enabled a 

process where one renders a very thin layer of silicon 

at the liquid state and recrystallize this layer over 

few tens to hundreds of nanometers (>1400°C) while 

remaining at room temperature (20°C) at the other 

side of the wafer. Excico provided this industrial 

process solution first to Power Devices Fabs but has 

today extended its application portfolio to CMOS 

Image Sensors and is also developing solutions for 

Memories, Processors, LED and Solar Cells Markets. 

Julien Venturini, 

Marketing Director, 

Excico 

The value of our Laser Thermal Annealing (LTA) 

platform and process solutions is the capability to 

improve thin layers implemented in semiconductor 

fabs at the nanometer scale without affecting buried 

functional layers and with a very homogeneous 

process across the whole device area. 

This improves and locks-in the electrical surface 

properties of a semiconductor with an ultra-low 

thermal budget with no damage of the device 

underneath. A historic step in the “diffusion” 

vendor’s industry was achieved few years ago 

when Excico installed production equipment for thin 

Yole Développement: According to you, what 

are the main key features and advantages 

of BSI sensors compared to standard FSI 

CMOS image sensors How do you explain 

the different motivations for BSI technology 

to enter the high-end video camera imaging 

versus the low-end consumer / mobile type of 

CMOS imaging applications 

Julien Venturini: The key advantage of Backside 

Illuminated CMOS imaging sensors technology 

is a Fill Factor in each pixel of 100%, while this is 

impossible to achieve with the front side illumination 

device where transistors are shading the incoming 

light to be detected. Therefore the sensitivity is 

improved allowing manufacturers to reduce pixel 

size without damaging the device performance. 

“The first market 

segment requiring 

BSI technology in 

volume is obviously 

the mobile phone” 

says Julien Venturini. 

LTA annealing platform for BSI CIS manufacturing 

(Courtesy of Excico) 


There were several niche developments and 

productions of BSI sensors the last years, mainly 

for low volume high end scientific, military and 

aerospace applications. But the first market segment 

requiring BSI technology in volume is obviously the 

mobile phone where the market is still driven by a 

strong pixel number appeal while requiring a small 

embedded imaging sensor. But adoption of the 

technology in mass production is only possible if one 

can master the process on 200 and 300 mm wafers. 

There are other reasons for BSI adoption in still 

imaging device like DSLR camera and one of them is 

the large acceptance angle range of the pixel which 

is an interesting asset when it is required to change 

the imaging lens of the camera. 

15


High level technology roadmap 

of BSI-CIS implementation 

(Courtesy of Excico) 

The sensitivity increase can also be used for the 

exposure duration reduction at constant pixel size. 

This comes to your second question where there is 

a clear application of this feature for video camera. 

This is even more useful in the case of high resolution 

applications. 

There were technology roadblocks preventing rolling 

out the BSI technology for consumer applications 

at a relevant cost, but they are today mastered by 

most of our customers. In a nutshell we can say that 

the BSI CIS technology can theoretically be used 

on most of the imaging application. A strong driver 

of BSI adoption is also the use of 3D stacking and 

TSV processes. The additional cost of BSI processes 

can be compensated by increasing the number 

of die per wafer by using TSV technologies, and 

stacking vertically functionalities that were originally 

occupying areas aside the sensor itself on the die. 

Yole Développement: In our last Power Dev’ 

magazine, you presented the needs for 

backside laser annealing in power devices 

manufacturing. Could you tell us more about 

the use of this technique for BSI type of CMOS 

image sensors 

Julien Venturini: You are right that the concept 

of the process is very close to the one of backside 

annealing of IGBTs. The goal is to anneal the flat 

backside surface of the device while not damaging 

the buried front side. The main difference between 

the two applications is that the device thickness is 

only a couple of μm in BSI while it is 40 to 100 μm 

for IGBTs. The thermal constraint of BSI CIS means 

that the temperature has to be below 400°C at 2 to 

5 μm under the top surface (actually backside) of the 

device not to damage metallic lines of the front side 

process. The other difference is in the very strong 

sensitivity of the device to defects and to dopant 

profile. We went through several adjustments of the 

process parameters with our partners to optimize the 

device performances. The process integration has 

been facilitated by some thermal simulations which 

are also a knowhow that Excico provides today. 

The role of the Laser annealing is to improve the 

backside passivation by forming a shallow electrical 

junction and there are many ways to optimize that. 

The challenge is to keep the blue sensitivity of the 

device and to void any other recombination center 

formation. 

Yole Développement: Could you comment on 

the intrinsic advantages of Excico’s excimer 

laser tool versus the more common Green YAG 

laser tools available on the market 

Julien Venturini: Excico platform is today supported 

by a very specific Excimer laser technology which 

delivers a very large area (several cm²) which covers 

one or several devices in a single shot, while 308 nm 

enables a very thin absorption depth. 

That is why the 532 nm wavelength of YAG lasers 

cannot be easily implemented in a tight vertical 

control (few tens of nanometer junctions) of 

a semiconductor annealing process. The main 

bottleneck is that the wavelength is absorbed deeper 

in the semiconductor. The other issue is the small 

energy of the laser which requires having stitching 

areas between two consecutive pulses across the 

device. Consequences are 3 fold: 1- It induces more 

heat at the other side of the wafer and 2- the process 

variability and the control of the junction thickness 

are four times higher due to a slower gradient of heat 

16 



close to the targeted temperature window, 3- 

the performance and uniformity of the device 

is not matching the market expectations. 

We don’t see today the green laser to be able 

to reach high added value processes like those 

required in BSI CIS or in other mainstream 

Semiconductor market like LOGIC or Memories. 

Nevertheless there are probably other 

applications, when the thermal budget is not 

a constraint, where this laser technology 

can also be implemented. Although we own 

a very specific Excimer technology, Excico is 

not a ‘single laser technology’ company. As an 

annealing equipment vendor, and given our 

extended expertise in laser semiconductor 

interactions and processes, we are very 

carefully looking at other laser technology 

that could be integrated in an Excico existing 

platform provided it can serve our customer 

needs and roadmaps. 

Yole Développement: Who are the leading 

players of the BSI imaging landscape 

(IDM’s versus foundries) What it the 

status of 200mm versus 300mm in the 

today’s BSI landscape 

Julien Venturini: 300mm wafer capability 

appears to be a critical asset to penetrate the 

mobile phone market. But 200mm fabs have 

in front of them a couple of very attractive BSI 

market segment as well, including DSC and 

video Cameras which account for a significant 

volume (wafers and $) as well. Today both 

IDMs and foundries are dominating the BSI 

landscape which is a good thing for the market. 

As you know different BSI technologies are 

today implemented in different IDMs and 

foundry fabs with different process flows 

and cost models. It provides flexibility to the 

end customers while allowing a wide span of 

potential applications and market segments to 

be further developed. 

Yole Développement: Excico laser 

annealing equipment is also applicable 

to future “Monolithic 3DIC integration”. 

Could you comment on the drivers 

and motivation to use such process in 

future semiconductor IC processing 

Julien Venturini: Our customer’s technology 

roadmaps are adding more functionality 

per unit area to semiconductor devices. This 

requires more complexity of the device’s 

design illustrated by what is called the “More 

than Moore” 3D stacking law. It pushes the 

introduction of more materials requiring 

improving their properties through annealing 

while controlling vertical 3D processing tightly. 

This approach is mandatory to increase yield 

or just simply to enable the manufacturing of 

the device. Low thermal budget provided by 

LTA combines a high performance and a cost 

saving approach preserving process integrity 

along the complete manufacturing cycle. 

‘3D More than Moore’ illustrates itself in 

standard wafer level packaging but also in 

what is called 3D IC’s where several stack of 

core devices are homogeneously stacked at 

the device scale level. This concept is today 

developed by our customer and the LTA 

specifications are enabling them to accelerate 

their roadmap development. 

We can identify three main drivers for ultrafast 

annealing added value in 3D manufacturing 

approaches: 

1. First, the need to reach metastable thermal 

processes is identified for instance in dopant 

activation for silicon-based devices, but 

also in specific defect control processes 

where the short duration of the heat pulse 

can selectively cure defects. The melting 

phase is here key to induce such specific 

‘out of equilibrium’ processes that standard 

processes are unable to reach. 

2. Second, LTA tools typically deposit a very low 

thermal budget which represents in average 

the equivalent power of a 40 Watt light bulb 

on the wafer. By balancing the laser process 

parameters, the LTA equipment enables : 

i. Negligible thermal stress compared to 

other classical annealing tools: breakage 

or yield issues due to wafer warpage after 

the heat wave are then totally avoided. 

ii. Improvement and locking-in the electrical 

surface properties of a semiconductor 

without affecting layers and/or devices 

buried underneath. This is a key asset to 

all present and future developments of 3D 

device stacking. 

1. Third but not least, the cost and yield 

of manufacturing. Advanced 3D devices 

processes are complex and costly when 

using standard low thermal budget 

processes available today. 

i. The cost per wafer and per move of a low 

temperature epitaxial layer growth process 

is several tens of % higher than the LTA’s 

one 

ii. LTA process cancels several manufacturing 

steps of the process flow by saving forth 

and back move between Front End of Line 

and Back end of Line areas. This is valued 

even more recently with the thin wafer 

approaches of the 3D Memory markets 

where yield, breakage rates and number of 

moves are closely correlated. 

iii. The third contribution to cost reduction is 

the capability to increase the parametric 

yield over the wafer. The capability to 

cover a single or several die in a single 

shot enables a very high reproducibility of 

the process performance over the whole 

wafer. The step and repeat LTA process 

doesn’t shows the temperature gaps 

between the edge and the center of the 

wafer reported in standards annealing 

processes. 

The future of the microelectronic lies also in 3D 

and Excico is today an enabling actor. 

www.excico.com 

Cross section of a BSI CMOS image sensor. Top area must be annealed while buried 

metal levels must not (Courtesy of Excico) 

Julien Venturini, Marketing Director, Excico 

He received his PhD degree from Pierre and Marie 

Curie University (Paris) in 1999, in the field of Optics 

and Photonics and was completed lately by a MBA 

from HEC (Paris). He spent few years in SOPRA Laser 

Business Unit as Marketing and Application manager 

where he qualified and developed several Laser 

based processes for semiconductor and photovoltaics 

markets. He co-founded Excico in 2007 where he is 

today head of Marketing. 


17



Cavity packages for volume MEMS 

applications 

MEMS is a dynamic and fast growing market segment that has a broad landscape 

of packaging needs with not many agreed upon industry standards. 

There are many reoccurring requirements that the 

MEMS manufacturer demands from a high volume 

cavity package. First the cavity package must 

protect fragile MEMS features from external forces 

while still allowing them access to the external 

atmosphere. 

Other options include the additions of passives and 

other components used for system-in-package 

(SIP) solutions. 

Chris Stai, 

Senior Manager 

of Marketing 

Communications, 

Unisem 

The cavity package is used to de-couple the MEMS 

die from the thermal and mechanical effects of the 

second level assembly and the final application. 

The solution must be flexible in design and allow 

System in Package concepts. While having these 

attributes, the cavity package must be able to 

meet rigorous reliability standards as per JEDEC 

and others. And of course the constant challenge 

for any volume package solution, this all must 

be accomplished while at the same time be cost 

effective and competitive. 

LGA FLP with multi die and top port. 

(Courtesy of Unisem) 

LGA FLP system-in-package with bottom port 


“The two most 

common types of 

semiconductor 

packages used 

for MEMS cavity 

packaging are 

the leadframe 

based QFN and the 

laminate substrate 

based,” 

says Chris Stai, 

Unisem. 

The two most common types of semiconductor 

packages used for MEMS cavity packaging are the 

leadframe based QFN and the laminate substrate 

based Ball Grid Array (BGA) / Land Grid Array 

(LGA). One direction that has begun to take a 

foothold in the industry’s push for a high volume 

solution is the use of the LGA style package as the 

foundation for the MEMS cavity package. 

Three LGA based solutions have been introduced 

to the industry as high volume solutions for MEMS 

cavity packaging. The basic formats are the LGA 

Formed Lid Package (LGA-FLP), the LGA Molded 

Cavity Package (LGA-MCP) and the LGA Molded Lid 

Package (LGA-MLP). Each has unique attributes 

that make them strong solutions for specific 

MEMS devices and applications. The assembly 

and test infrastructure for LGA based packages 

is very mature and the processing in strip format 

provides improved volume throughput and the cost 

savings associated with high volume processing. 

The accepted standard material sets are also 

very mature and are used by many subcontract 

assembly and test services (SATS) providers in 

many countries and regions worldwide. 

The LGA-molded cavity package uses a BGA 

style molding system with a cavity vacuum tool to 

create a custom package where die can be either 

molded or placed into a cavity created by the mold 

and enclosed by a flat metal, plastic or glass lid. 

For multiple die applications, each die can have 

a custom environment. Options for the LGA-MCP 

package are multiple and/or stacked die, wirebond 

or flip chip, passive components for SIPs, full die 

coat and top or bottom ports. 

LGA-MCP System-in-package with customer cavity 

and top port (Courtesy of Unisem) 

LGA-MCP stacked die with custom cavity 

and bottom port (Courtesy of Unisem) 

The LGA-formed lid package has a stamped 

metal lid that may or may not have a pressure port 

depending on the specific application. Options for 

this package include multiple die and stacked die 

designs, standard wirebond or flip chip die bonding. 

The LGA-molded lid package has a custom 

molded lid that can be more complex than a 

metal stamped lid. Also unlike the LGA Metal Lid 

Package, this finished package has square sides. 

Similar to the other two cavity package solutions, 

18 



this package can have multiple and/or stacked die, 

wirebond or flip chip die connection, passives for 

SIPs, ports on the top and bottom of the package. 

The three LGA based cavity packages described 

can all meet the stringent requirements of the 

common reliability tests for standard package 

types. 

They pass moisture sensitivity level 2a which is 

a pre-bake for 24 hours at 125°C, TH at 60/60 for 

120 hours and three reflows at 260°C. They pass 

Temperature Humidity and THB 85/85 for 1000 

hours as well as Temperature Cycle from -65 to 

+150 degrees (500 cycles). The test for High Temp 

Storage at 150°C is also able to be passed at 1000 

hours. However, because of the nature of these 

types of packages, they are not able to pass Thermal 

Shock – Liquid to Liquid. 

LGA-MLP stacked die package with customer cavity 

and top port (Courtesy of Unisem) 

LGA-MLP System-in-package with bottom port 


www.unisemgroup.com 

Chris Stai is the senior manager 

of marketing communications and 

oversees all external communications 

for Unisem Group. Prior to his 

appointment with Unisem, Stai 

held various positions at Advanced 

Interconnect Technologies (AIT) 

which was acquired by Unisem in 

2007. Stai started at AIT in 1996 

as a senior marketing specialist and 

quickly rose in the ranks to his current 

position. Prior to AIT, Stai held brand 

marketing and event management 

positions with Hi-Tec Sports, a global 

sporting goods manufacturer. 

Stai has a bachelor’s degree in 

business administration from the 

California State University, Stanislaus. 

The 

62nd ECTC 

Call for Papers 

is now open! 

Conference Sponsors: 

The Electronic Components and Technology Conference 

(ECTC) invites you to submit an abstract for presentations 

and/or Professional Development Courses (4 hours). As 

the premier event in the semiconductor assembly industry, 

ECTC addresses new developments, trends and applications 

in integrated systems packaging. 

We welcome previously unpublished, non-commercial 

abstracts in areas including, but not limited to: 

Advanced Packaging 

Applied Reliability 

Assembly & Manufacturing Technology 

Electronic Components & RF 

Emerging Technologies 

Interconnections 

Materials & Processing 

Modeling & Simulation 

Optoelectronics 

Abstract submissions and Professional Development Course 

proposals for the 62nd ECTC are due by October 10, 2011. 

To submit, visit: 

www.ectc.net 


19



3D-IC challenges: 

design with test (Part 1/2) 

With numerous product announcements and technological advancements in 

the past 12 months, 3D-ICs using through-silicon vias (TSVs) have emerged 

as a proven, viable technology that offers compelling advantages in power, 

performance, form factor, and time-to-market. 

Samta Bansal leads 

3D-IC efforts among 

others for Applied Silicon 

Realization, Cadence 

Design Systems, Inc 

By making it possible to stack analog, digital, 

logic, and memory dies at different process 

nodes, 3D-ICs offer what may be the best 

alternative to the skyrocketing costs of advanced 

process nodes. 

There are multiple design challenges in 3D-IC 

Silicon Realization, as noted in a recent whitepaper 

and Chip Design Magazine article. However, design 

for test (DFT) is one of the most challenging areas. 

3D-IC stacks will be deployed only if they are costeffective, 

and they will be cost-effective only if 

they’re testable and offer reasonably good yields. 

Innovation is ongoing both in design for test (DFT) 

and in tester and probe card technology. 

This article provides a general overview of 3D-IC 

test challenges, and describes a DFT architecture 

developed at the imec research institute in cooperation 

with Cadence Design Systems. The 

architecture enables the modular testing of dies 

and TSV-based interconnects by using die-level 

wrappers that isolate the individual dies from the 

stack. A subsequent article will focus on needed 

improvements and technical progress in tester and 

probe technology. 

While wire-bonded systems-in-package (SiPs) 

may have a few hundred interconnects, 3D-ICs 

may have thousands if not tens of thousands of 

interconnects. Even a single defective TSV can 

render an entire stack unusable. If individual TSVs 

have 99.9% yield, at least one defective TSV can 

be expected in a stack with 1,000 TSVs. 

3D-IC test challenges – Test flows 

According to Erik Jan Marinissen, principal scientist 

at imec, 3D-IC test challenges can be understood 

in terms of test flows (what to test when), test 

content (what test data is needed for likely 

defects), and test access (how to probe and access 

test signals). 

Herb Reiter, 

Chair of the GSA’s 

3D-IC Working Group 

and consultant 

for the GSA 

“Current probe 

technology cannot 

access TSVs or 

micro-bumps,” 

says Santa Bansal, 

Cadence. 

20 

A sound test methodology for 3D-ICs is necessary 

in order for IC designers to have the confidence 

to design them. Designers will not start 3D 

designs without knowing how to make them fully 

testable. Likewise, test equipment manufacturers 

and assembly houses cannot plan a production 

test environment without knowing which failure 

mechanisms to look for, how to cost-effectively 

assure known-good die (KGD) prior to stacking, 

how to thoroughly test stacks during the assembly 

process, and how to best perform exhaustive final 

tests. 

Some obvious questions around 3D-IC DFT are: 

Who tests what portion of a 3D stack, and when 

Are there new fault types associated with TSVs 

and micro-bumps How can testers access TSVs 

and micro-bumps, since they are too small for 

today’s probe technology Will transistor behavior 

change due to the wafer thinning process How is 

it possible to control and observe individual dies, 

even though the only access to test signals is 

usually on the bottom die in the stack 

Fortunately, solutions are starting to emerge. 

A number of papers and tutorials at recent 

conferences and workshops have addressed 

challenges and potential solutions for 3D-IC test. 

A conventional 2D test flow is proven and 

straightforward. It involves wafer probe, and, 

after packaging, final test. In the 3D world a 

disaggregated flow is much more likely. The 

individual dies are likely to come from different 

wafer fabs, and there are many questions about 

what should be tested when. Should dies be tested 

before stacking, and do they need KGD final-test 

quality, which includes at-speed testing and burnin 

Should interconnects be re-tested every time 

a new die is added to the stack, or not until the 

entire stack is assembled What will the final test 

include and who will do it 

At one extreme, it is possible to spend too much 

time and money on continual re-testing. At another 

extreme, not testing enough may result in a “penny 

wise and pound foolish” approach that results in 

low yields, Marinissen said. He noted that careful 

cost and yield modeling is needed to determine 

what steps the test flow should include for any 

given 3D-IC. 

Pre-bond testing is done on the original or 

thinned-down wafer before stacking. It can be 

challenging for any die that will not be the bottom 

die in the stack. These “upper” dies receive all 

functional signals (power, clocks, control, data) 



through TSV interconnects, which are too 

small for current probe technology to handle. 

One workaround is for the IC designer to 

bring test signals out to larger, dedicated 

pre-bond test pads. 

Unless yields for the individual dies are very 

high, pre-bond testing is probably costeffective. 

If individual dies are likely to have 

only a 90% yield, and four dies are placed 

in a 3D stack, the yield of the completed 

stacks will only average around 66%. It is 

less expensive to find a defective die at the 

pre-bond level than during post-bond testing. 

wafer fab 1 wafer fab 2 wafer fab 3 

Pre-Bond 

Test 1 

stacking 

1 + 2 

Mid-Bond 

Test 1 + 2 

Pre-Bond 

Test 2 

Pre-Bond 

Test 3 

stacking 

(1 + 2) + 3 

Mid-Bond 

Test 1 + 2 + 3 

assembly & 

packaging 

Final Test 

The 3D-IC test flow includes many different 

steps that may be spread out among different 

suppliers. (Courtesy of imec) 

Post-bond testing is done on a partial or 

complete stack. It assesses the quality of 

TSV-based interconnects between stacked 

dies, and checks for additional defects that 

may have occured due to stacking. Probe 

access is available only on the external I/Os of 

the stack, which are typically located on the 

bottom die only. Fortunately, the bottom die 

external I/Os lead to conventional wire-bond 

pads or flip-chip bonds that do not provide 

major test access challenges. However, the 

DFT architecture needs to propagate test 

data from the external I/Os up and down 

through the stack. 

Post-packaging (or final) testing serves 

as the final check that determines the 

outgoing product quality to the customer. 

The designer should be able to test any die 

and TSV-based interconnect layer in the 

stack. Test access will not require wafer 

probing, but will instead be based on sockets. 

Ultimately, board-level interconnect test and 

board-level hardware/software debug will 

also be needed. For board test, the 3D-IC 

should be as transparent as possible to the 

board designer, and board testers should only 

need to access the boundary scan interface 

of the stack. 

3D-IC test challenges – Test 

content 

All manufacturing defects that can occur 

in conventional 2D chips are relevant when 

these chips are in 3D stacks, including 

stuck-at, transition, delay, and IDDQ faults. 

However, the designer needs to provide new 

test content because there are new types of 

potential defects, particularly those due to 

added 3D processing steps and TSV-based 

interconnects. 

One 3D processing step that can cause new 

defects is wafer thinning. TSV processing 

only allows limited heights and aspect ratios. 

If a TSV has a 5μm diameter and 1:10 aspect 

ratio, this would dictate a height of 50μm. 

To expose the TSVs, the wafer must be 

thinned to 50μm from an original thickness of 

750μm. Wafer thinning may change transistor 

performance, degrade I-V characteristics, and 

cause yield losses. 

Defects may also be due to thermal 

expansion and thermo-mechanical stress. 

Dies in the middle of a stack are especially 

prone to higher temperatures, and excessive 

heat can change the performance of devices 

or even lead to damage. Test itself can be a 

danger, as at-speed test may cause dies to 

heat up excessively. Designers must ensure 

adequate power to all dies in a stack, and 

avoid excessive noise or voltage drop. 

TSV-based interconnects may introduce 

defects during fabrication (liners, barriers, 

plating) or interconnect bonding (oxidation/ 

contamination, height variation, misalignment). 

Opens, shorts, and timing faults are possible. 

Imec and Cadence have worked together 

to develop an interconnect fault model and 

automatic test pattern generation (ATPG) 

capability to detect such defects. 

3D-IC test challenges – Test 

access 

Current probe technology cannot access TSVs 

or micro-bumps. TSVs typically have diameters 

around 5μm and a 10μm pitch, while microbumps 

may have diameters of 25 μm and a 

40μm pitch. The minimum in-line pitch for 

today’s advanced wafer probe technology 

is well over 50μm. Further, probes may 

leave scrub marks or cause pad damage. 

The industry is working to improve probe 

technology, but in the meantime, the IC 

designer should plan on adding dedicated 

pads in the DFT architecture. 

Should pre-bond testing be done before or 

after wafer thinning, or perhaps both Before 

wafer thinning (top below), handling is easier, 

but TSVs are buried in thick substrate and 

access is available only on the front side. After 

wafer thinning (bottom), the wafer is placed 

on a temporary carrier wafer, and there is no 

front side access, so it’s necessary to probe 

on the back side of the thinned wafer. Probes 

can easily damage the thinned wafer. 

face 

face 

carrier 

wafer 

A carrier wafer blocks probe access to the 

front side of a thinned wafer - bottom picture. 

(Courtesy of imec) 

A modular 3D-IC test architecture 

In modular testing, chip modules such as 

embedded cores are tested as standalone 

units. Modular system-on-chip testing also 

enables heterogeneous circuit structures, 

“divide and conquer” ATPG, and test reuse. 

Modular testing of 3D-ICs can provide these 

capabilities as well as easy yield monitoring, 

first-order fault diagnosis, and the ability to 

flexibly optimize the 3D-IC test flow. 

A 3D-IC DFT architecture, originally created 

at imec, was further developed and refined in 

co-operation with Cadence. The architecture 

has been proposed as a standard test-access 

architecture through the IEEE P1838 3D 

Test Working Group, which represents EDA, 

IP, ATE, and semiconductor vendors. “In 

the end, we feel it needs to be an industry 

solution,” Marinissen said. 

In this DFT architecture, wrappers provide 

isolation and boundary-scan access for the 

internal testing of individual dies as well as 

interconnect between dies. The architecture 

supports pre-bond, mid-bond, and post-bond 

testing. It allows and complements any test 

structures that may be used on the individual 

dies, such as scan or BIST. “The architecture 

provides a way to get test data from any 

of the chips in the stack without overly 


21


consuming a lot of test signals,” said Brion 

Keller, senior architect at Cadence. 

The architecture supports both IEEE 1500 

(Embedded Core Test) and IEEE 1149.1 

(JTAG) wrappers, but most of the initial 

work has focused on IEEE 1500. While the 

wrappers perform similar functions, there’s 

a difference. IEEE 1149.1 uses a singlebit 

instruction/data interface, two or three 

control inputs, and a Test Access Port (TAP) 

controller. IEEE 1500 also provides a singlebit 

serial interface but allows a scalable n-bit 

parallel data interface, along with six or 

seven control inputs. 

The architecture also adds several 3D 

enhancements to test wrappers. One is called 

a “test elevator.” As previously stated, postbond 

test access is typically available only from 

the bottom die in the stack. A test elevator 

is needed to pass test data to and from dies 

above the bottom die, using dedicated TSVs. 

A design with 1,000 functional TSVs may only 

require 20 or so of these special test TSVs. 

Another wrapper enhancement allows “test 

turns” that return the test signals within a die, 

rather than passing signals on to the next die. 

Enhancements also provide additional probe 

pads for pre-bond test, and add registers to 

provide a clean timing interface to output 

paths. A hierarchy of instruction control 

registers makes it possible to selectively test 

higher-level die. 

A 3D-IC DFT architecture will only succeed if 

it can be implemented in EDA tools. For this 

reason, Cadence and imec have collaborated 

to develop a wrapper generation flow using 

the Cadence Encounter RTL Compiler, and an 

innovative ATPG solution using interconnect 

fault modeling for TSVs and micro-bumps in 

Cadence Encounter Test. This interconnect 

ATPG is very efficient – a design with a 

million interconnects may require just tens of 

dedicated patterns. The solution uses what is 

called a “boundary skin” model that provides 

just enough information about the die to 

generate ATPG patterns. 

Conclusion 

3D-IC test is challenging, but it does not 

need to become a bottleneck. If design 

and manufacturing teams understand the 

challenges and work together, they can 

develop an appropriate test flow by doing 

cost modeling, adding test content for new 

3D failure mechanisms, and using dedicated 

probe pads so long as probe technology 

cannot provide full access. A modular 3D-IC 

DFT architecture, such as the one described 

here, can alleviate many test challenges while 

providing controllability and observability 

for individual dies and TSV interconnects. 

A standardized DFT architecture through 

IEEE P1838 will simplify a 3D-IC design, 

manufacturing and test flow supported by 

multiple industry providers. 

To be continued in the November issue of 

3D Packaging 

www.cadence.com 

www.gsaglobal.org 

Samta Bansal leads 3D-IC efforts among 

others for Applied Silicon Realization 

at Cadence Design Systems, Inc. 

She has more than 12 years of experience 

working with semiconductor leaders including 

both 2D and 3D-IC design space. Prior to 

Cadence, Samta worked at Synopsys looking 

into the front end technologies. With hands on 

experience on front end for 8 years and moving to 

Back end, Samta has a very good understanding 

of the evolution and challenges the industry has 

been going in terms of design requirements and 

is very passion ate in driving this shift of the 

industry from 2D to 3D-IC within Cadence and 

working with the ecosystem partners. Samta 

has Masters in Physics, Bachelors in EEE from 

Birla Institute of Technology and Science(BITS), 

Pilani and MBA from Santa Clara University. 

The DFT architecture suggests the addition of die-level test wrappers to the existing test structures 

in individual dies. (Courtesy of imec) 

22 

Herb Reiter, Chair of the GSA’s 3D-IC 

Working Group and consultant for the GSA 

since 2008. 

He founded eda2asic Consulting in the spring 

of 2002 to increase cooperation between 

EDA suppliers and semiconductor vendors. 

In this role Herb introduced many EDA tools, 

flows and methodologies to reduce IC design 

time for the semiconductor vendors and to 

lower power dissipation and unit cost for their 

products. Previously Herb worked for 5 years 

in business development roles at Barcelona 

Design, Synopsys and Viewlogic. The PrimeTime 

sign-off wave and the TSMC reference flow # 

1 are highlights of Herb’s accomplishments at 

Synopsys. From 1980 to 1997 Herb worked 

in both business and technical roles at VLSI 

Technology and National Semiconductor to 

market ASICs and ASSPs. Herb earned an MBA 

at San Jose State University and Master Degrees 

in Business and in Electrical Engineering at the 

University and at the Technical College in Linz/ 

Austria, respectively. 


www.iwlpc.com 

SAN TA 

CLARA, CALIFORN IA 

O CTO B E R 

3-6, 

2011 

8th Annual 

International Wafer-Level Packaging 

Conference & Tabletop Exhibition 

October 3-6, 2011 

Marriott Hotel, Santa Clara, CA 

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©2010 Solid State Corporation


ANALYST CORNER 

Lower costs targeted for HB LED 

packaging 

The packaged LED market is expected to hit $12B in 2011, and then nearly double to 

$21.5B by 2015. For this rapid growth to take place, bold innovation is desperately 

needed to drive down the costs of LED packaging. 

Jean-Marc Yannou 

Project Manager, 

Advanced Packaging 


High-brightness (HB) LEDs involve LED 

packages that consume more than 200mW. 

High-power HB LEDs include those above 

800 mW, and they have serious challenges to 

overcome. This is the application area for general 

lighting, which has the potential to become a very 

big deal if, and only if, cost can be broken by a 

factor of 10—essentially an order of magnitude. 

That’s the biggest challenge this industry is 

facing, although a close second is that these LEDs 

have stringent challenges to address for heat 

dissipation. So the industry is pursuing lower-cost, 

better performing packages at the same time. 

How can lower costs be achieved for LEDs now 

that all of those borrowed from IC packaging have 

been tried and none were able to drop the cost low 

enough Innovation. This will be a new direction, 

because innovation in IC packaging traditionally 

has only been done to achieve greater performance 

and when there’s no other way than developing 

a new platform, which usually costs more in the 

beginning, until it can benefit from the scaling 

effect. It will be different with LEDs, because of the 

expected huge volumes involved, and the scaling 

effect can be almost immediate if someone comes 

along with a differentiating technology at a low 

enough cost. 

An area expected to help lower costs is coming 

from the front-end manufacturing side’s move to 

larger wafer sizes—to 6 in.—and lower-cost backend 

assembly and packaging technologies. 

One way to potentially reduce costs is in the 

various assembly steps of LED packaging. 

Until recently, LEDs had always been mounted 

onto a substrate. Now some manufacturers are 

building LED modules without substrates between 

the die itself and the fixture, which is known as 

the chip-on-board (COB) trend. Eliminating the 

substrate enables both a cost reduction and a 

thermal resistance from the LED to the fixture. 

Bingo—higher thermal performance with a lower 

cost! Why isn’t everyone rushing to embrace this 

trend Because it limits the amount of possible 

fixture designs and requires thorough assembly 

capabilities by the fixture manufacturer. In other 

words, this solution will be limited to those lighting 

appliance designers and manufacturers who 

master LED assembly techniques—and it doesn’t 

LED packaging strategies 


24 



result in a flexible enough solution for mainstream 

lighting. 

Fixture substrates (main boards) include ceramic 

(aluminum nitride ceramic is already preferred over 

the traditional alumina substrate) or the “metalcore 

PCB,” a.k.a. “MCPCB,” which is already being 

used in LED fixtures for high thermal conductivity. 

High power (>1W) LED substrate market shares 

by substrate type 


There are several key changes emerging in the 

LED substrate field. Initially the two most popular 

substrates were leadframes made of copper or 

ceramic substrates made with alumina. Leadframes 

are bulky, and although they offer high thermal 

conductivity, their thicknesses induce relatively high 

thermal resistances to the fixture boards. Alumina 

substrates are very low cost but don’t provide an 

adequate thermal conductivity, so they’re being 

phased out and replaced with aluminum nitride 

substrates with greater thermal conductivity—at 

nearly the same cost today, because they benefitted 

from a very fast volume scaling effect. The top 

supplier of these aluminum nitride substrates, by 

the way, is Taiwan-based Tong Hsing. 

In other changes, glass companies have developed 

glass ceramic substrates, which are essentially 

ceramic substrates with high glass content. Silicon 

is also being considered as an interesting substrate 

for the future, and it’s being proposed by a number 

of companies because it has a high thermal 

conductivity. A drawback is that it’s expensive, 

so it’s a question of how cost effective silicon 

substrates can be. In the future, combining silicon 

substrates with wafer-scale operations and batch 

processing may lead to other cost breaks. 

Phosphors are another area that could potentially 

drive down costs. This is a material that is 

deposited onto blue LEDs to make them white. 

It’s one of those secretive areas where there’s no 

standardization and no one knows what material 

others are using or how it’s being deposited. But if 

it is used at the wafer-level, it could enable greater 

throughput and lower costs. 

In terms of the interconnection, there are several 

ways to interconnect LEDs to the package substrate 

or the fixture itself when using COB: wire bonding, 

flip chip, or flip chip bonding by bumping. LEDs 

need to be manufactured differently, depending on 

if they’re wire bonded or bumped. There are also 

two ways to manufacture them when they’re wire 

bonded. Vertical LEDs only need one wire, while 

horizontal LEDs need two wire bonds (one for the 

anode, one for the cathode). And there’s a wide 

range of technology diversity to attach the bottom 

side of vertical LEDs (the ones with only one wire 

bond on the top). Their bottom side can be glued 

or gold-tin soldered onto the substrate. No solder 

is needed if using flip chip, which is something 


Lumileds is doing, because the preferred material 

is gold. Gold bumps are bonded to the substrate 

by thermo-ultrasonic bonding. Our forecast is that 

flip chip technology will be increasingly used in 

the future, because it offers a higher performance 

over cost ratio. This is the lead metric for LEDs. 

Performance is “luminance,” and each technology 

choice in the field of HB LEDs comes down to 

“dollars per lumen”—regardless of how expensive 

the technology is, it’s of high interest as long as it 

lowers the dollar per lumen ratio. 

The last step in LED packaging is placing the optical 

lens on top of the LED so that light is diffused in the 

right direction. These lenses can be made of either 

glass or silicone, and can be placed in several ways. If 

this is done on a silicon wafer substrate, in which case 

it’s wafer-level optics, we’ll see lower costs through 

the scaling effect—thanks to batch processing. 

On the business end, the supply chain is chaotic. 

Some companies are making everything from 

the LED devices, doing design, and the front-end 

and back-end themselves—they’re mastering the 

complete supply chain. This includes Samsung, 

Cree, Nichia, LG Innotek, Sharp, OSRAM, Philips 

Lumileds, and many others. Some rare companies 

are specializing in packaging, for example. Others 

are working exclusively on the front-end side. 

There is little standardization as of today on either 

the technology side or the supply chain structure, 

and we expect to see some bold technology choices 

and attempts to take over market share. 

Innovation is desperately needed to lower costs of 

LED packaging—especially since it now accounts 

for 25 to 55% of LED manufacturing costs. Before 

the market can really take off, the cost needs to 

drop to a price that consumers are willing to pay. 

www.yole.fr 

Jean-Marc Yannou joined Yole 

Developpement as technology and 

market expert in the fields of advanced 

packaging and Intergrate Passive 

Devices. He has 15-years of experience 

in the semiconductor industry. He 

worked for Texas Instruments and 

Philips (then NXP semiconductor) where 

he served as Innovation Manager for 

System-in-Package technologies. 

25 

“Our forecast 

is that flip chip 

technology will 

be increasingly 

used in the 

future, because 

it offers a higher 

performance over 

cost ratio,” says 

Jean-Marc Yannou, 

Yole Développement.


ANALYST CORNER 

Smartphones morph into sophisticated 

sensing platforms 

Smartphones are morphing into sophisticated sensing platforms, with increasing 

MEMS and sensor content. More than 300 million smartphones, each containing 

at least 4 to 8 MEMS sensors, are shipped annually. Standardization is becoming 

increasingly critical to decrease costs associated with MEMS and sensor packaging. 

Jérôme Baron, 

Market Analyst, 

Advanced Packaging, 


MEMS and sensors are currently experiencing 

explosive growth, with the latest smartphones 

needing to be able to sense how fast 

you’re moving and if you change direction, as well 

as pinpoint your exact location and even recognize 

your face. Clearly, smartphones are becoming 

serious sensing platforms. As a result, there’s a 

need to develop packaging solutions to protect all 

of the MEMS and sensors involved. 

There are plenty of MEMS and sensors to be 

found in recent smartphone designs, for example: 

accelerometers, gyroscopes, pressure sensors, an 

electronic compass, silicon microphones, a CMOS 

image sensor, a MEMS micromirror, BAW filters, 

BAW duplexers, RF switch, and TCXO oscillators. 

The future is looking very bright for MEMS and 

sensors, with mobile phone makers like Nokia are 

working on projects to integrate as many 

as 8 silicon MEMS microphone sensors per cell 

phone to provide noise cancellation and video 

conferencing features. 

Other industry trends include improved camera 

image sensors, which are equipped with up to 3 

image sensors capable of sensing the external 

world. 

Motion sensors are also being upgraded, relying on 

MEMS accelerometers, gyroscopes, magnetometers, 

and pressure barometers to enable positioning 

services on smartphones—providing your exact 

location, direction, and altitude for pedestrian GPS 

applications. In the future, this shows potential for 

social networking related applications. 

MEMS & Sensor content in emerging smartphone platforms 

(Yole Développement, MEMS & Sensors for Smartphones 2010 report) 

Standard IC / passive content 

MEMS & Sensor content 

BAW filters & duplexers 

RF switch / variable capacitor 

TCXO oscillators 

MEMS micro-mirror 

 

 

 

 

CMOS Image Sensor 

Auto-Focus actuator 

Silicon microphones 

Front camera 

ALS & Proximity sensor 

MEMS Microdisplay 

26 



Indeed, smartphones are rapidly becoming an 

integral part of our everyday lives—as a device 

that gives us 24/7 access to information (via 2G, 

3G, LTE on the network) and other people—and 

it’s arguably one of our most useful possessions. 

Adding more sensing features will, in the near 

future, also enable communication of all of our 

personal body parameters for medical monitoring 

purposes, which can link to direct and permanent 

connections to hospitals, doctors, or home 

computers. 

In terms of involved packaging, it’s always about 

protecting and orchestrating the assembly of the 

sensing module. But this is costly—packaging, 

assembly, and test of MEMS accounts for nearly 50 

to 60% of a module’s cost. This type of packaging 

is more complex than that of ICs, because it 

requires a system-in-package type of assembly. 

Much of the packaging for sensors is also bulky 

and has very specific constraints. For example, 

if you have an optical type of sensor, an optical 

window is required. And since most MEMS need 

hermeticity, this means making a vacuum and 

providing hermeticity at the wafer level. The waferto-wafer 

bonding and wafer-level capping steps are 

also very specific—as are final test and calibration. 

Historically, ceramic cavity substrates were used 

in MEMS packaging configurations to create the 

vacuum cavity environment, since many MEMS 

require operations under full hermeticity. An issue 

with this is that ceramic hermetic packages are 

still bulky and quite expensive solutions—ranging 

from US$0.5 to $2/package. Recently, wafer-level 

capping and wafer-level packaging technologies 

have started to change this situation, because they 

enable the required hermeticity and protection at 

the sensor die level, while the final assembly can 

be done using proven, high-volume, low-cost, and 

more standard assembly techniques such as QFN 

packages (leadframe-based) or BGA/LGA packages 

(based on organic PCB substrate technology). 

We’re also seeing a few MEMS companies such 

as Avago, VTI, and Discera taking the lead on 

“substrateless” assembly techniques, in which 

they successfully implemented 3D wafer-level 

packaging concepts by using TSV/TGV vertical 

feedthrough, redistribution layers, and bumping 

processes to directly connect the silicon part of the 

MEMS/sensor to the final motherboard—without 

using a ceramic, leadframe, or plastic package. 

is growing at a faster rate than the rest of the IC 

industry. There’s a huge amount of effort being 

directed toward developing MEMS packaging 

solutions for smartphones. 

ST, Bosch, and Freescale are IC companies that 

aren’t new to the MEMS industry, but each has a 

goal of becoming a one-stop shop MEMS sensor 

supplier. What’s especially interesting here is 

that this is becoming more important, and many 

companies like Texas Instruments and Maxim are 

trying to catch up in this area. For example, Maxim 

recently acquired SensorDynamics, a MEMS gyro 

company. The IC players are all seeing a need to 

move into the MEMS space. We’ll also likely see 

Qualcomm and Samsung go after this area. All of 

them are interested in the MEMS sensor market 

because it’s growing fast and it’s becoming more 

critical to be involved in it. 

Final test and calibration is another area of the 

business that OSATs are interested in pursuing. 

Calibration is very important, so it’s only when 

companies reach high volume that they consider 

outsourcing. 

Another trend worth noting is the shift to 8” 

wafer fabs. It just makes sense to use wafer-level 

packaging, because as soon as you can add more 

dies on a wafer it becomes more cost effective. 

In response to increasing demand (greater than 

3,5 billion units of MEMS and sensors shipped 

annually in the mobile space) and complexity, 

MEMS packaging landscape is changing rapidly. 

The number of MEMS and sensors going into 

smartphones is expected to continue to skyrocket, 

driving integration of an incredibly high number 

of MEMS and sensor devices. So standardization 

is critical to implement to help get packaging, 

assembly, and test costs under control. There are 

many different players with different designs, and 

it’s not likely we’ll see one solution adopted by all 

the players. Expect to see a blooming of several 

standards in the future, driven by the biggest and 

most successful players. 

Ultimately, the MEMS pioneer players engineered 

and made 3D technology a reality, and MEMS 

foundries and fabs have the toolboxes necessary 

to move quickly into 3D, if and when they want to! 

“Mobile phone 

makers like Nokia 

are working 

on projects to 

integrate as 

many as 8 silicon 

MEMS microphone 

sensors per 

cell phone to 

provide noise 

cancellation and 

video conferencing 

features,” says 

Jérôme Baron, 

Yole Développement. 

In the beginning, when the MEMS industry was still 

quite small, the mantra was: “One product, one 

process, one package.” This will be an interesting 

market to watch, because it’s growing in units 

and complexity. Large OSAT companies such as 

ASE, SPIL, and Amkor are also eyeing this market 

because right now the MEMS and sensor content 

www.yole.fr 

Jerome Baron is leading the advanced 

packaging market research at Yole 

Developpement. He has been following 

the 3D packaging market evolution 

since its early beginnings at device, 

equipment and material levels. He was 

granted a Master of Science degree 

from INSA-Lyon in France 


27


W H A T ’ S I N S I D E 

3D Wafer-Level-Packaging of MEMS 

gyroscope sensor with VTI’s CMR3000 

Introduced at the end of 2010, VTI new consumer gyro targeting mobile phones 

and gaming devices is now in volume production. Whereas the gyroscope 

consumer market is strongly dominated by 5 players (InvenSense, Epson Toyocom, 

STMicroelectronics, Panasonic and Sony), only 2 of them (InvenSense and STM) 

have released an integrated 3-axis sensor. However VTI Technologies is also 

playing a significant part in this expanding market. 

VTI CMR3000 

Featuring a 4.1x3.1x0.83mm size, the CMR3000 

becomes the smallest 3-axis gyroscope. These 

small footprint and height are obtained by using of 

a wafer-level packaging approach. 

MEMS manufacturing 

The MEMS gyroscope is manufactured using three 

bonded Silicon wafers. The two first wafers are 

used to build the sensor elements (seismic mass, 

capacitive combs…). Indeed, the sensor elements 

are patterned by DRIE on a c-SOI substrate (fusion 

bonding of two silicon wafers one of which contains 

buried cavities). The third wafer (the cap wafer) 

allows sealing hermetically the sensor elements. It 

is realized with a silicon wafer where via and cavities 

are etched by DRIE and filled with borosilicate glass. 

The glass allows to insulate silicon contacts with the 

sensor and to seal hermetically the component with 

an anodic bonding process. 

Underfill 

ASIC 

VTI CMR3000 3-axis MEMS gyroscope 

(Courtesy of VTI Technologies) 

MEMS 

Solder 

Ball 

Wafer 1 



Cavity SOI, MEMS and TGV substrates wafer bonding 

(Courtesy of System Plus Consulting) 

Wafer-Level-Packaging 

The component is wafer-level packaged using a 

two redistribution layers (RDL) technology. First, 

two Aluminum RDL (M1, M2) and two Inter-Metal 

Dielectric (IMD) are added in order to realize the 

electrical connections between MEMS/ASIC and 

ASIC/solder balls. Then an UBM layer is added 

before dropping the solder balls on the wafer. The 

ASIC die (previously thinned and bumped) is then 

flip-chipped on known good MEMS (VTI Chip-on- 

MEMS technology) and an underfill is applied for 

passivation and reliability enhancement. Finally, 

the stack can be diced and tested. VTI is coming 

up here with an impressive “Via first” type of TGV 

– Through Glass Via technology which is actually 

using doped silicon to drive the electrical current 

from the MEMS part through the hermetic glass / 

silicon compound wafer down to the ASIC die part. 

M2 

Underfill 

M1 

ASIC 

MEMS 

Solder bump 

(Sn, Ag) 

ASIC to MEMS wafer micro-bumping 


Supply chain scenarios 

Regarding the supply-chain of manufacturing 

such an impressive 3D WLCSP device, several 

different scenarios are possible. According to press 

releases published by VTI, the manufacturing of the 

CMR3000 wafers is outsourced in an 8-inch foundry 

in Asia. VTI keeps the manufacturing of automotive 

and medical sensors in-house on 6-inch wafers 

but will outsource in Asia the manufacturing of the 

sensors for consumer market. 

We know that the ASIC wafer is being manufactured 

by Texas Instruments. The cavity SOI wafer is likely 

to be provided by Okmetic (FI) or could alternatively 

being processed at a MEMS foundry partner such 



Si 

Titanium 

Aluminum 

Si 

Oxide 

Oxide 

Oxide 

Si 

Glass 

Aluminum 

UBM 

Solder Ball 

IMD 

Bump 

Underfill 

ASIC 

CMR3000 Schematic Construction (Courtesy of System Plus Consulting) 

as TI, Silex Microsystems, tMt or possibly foundry 

giants TSMC and Global Foundries which are eyeing 

at entering the MEMS manufacturing business by 

leveraging depreciated and aging 200mm mature 

wafer fabs in Asia. The Glass interposer substrate 

part could actually being manufactured by the 

MEMS foundry partner as well under the license 

of VTI technology which has developed for years 

multiple 3D via technologies in glass substrates. 

One other possibility would be that such structured 

glass substrate interposers could be provided 

directly by PlanOptik (Germany), a glass processor 

company operating under the TGV technology 

license from Fraunhofer-ISIT institute (also in 

Germany). Regarding the “Middle-end” or “Wafer- 

Level Back-end” process, the ASIC wafer part is 

flip-chipped including a passivation layer and wafer 

bumping processes that could be realized either at 

TI’s ASIC wafer fab or al ternatively outsourced to 

wafer bumping subcontractors such as FCI - Flip- 

Chip International (USA) or Unisem (ML) in Asia. 

The MEMS stack sandwich of three wafers (Glass 

+ Si + Glass sandwich) part is finally processed 

with a polymer passivation, metallization RDL, 

repassivation, UBM and thin bump pad plating 

that is also likely to be maufactured either at TI 

or FCI and Unisem. The back-end assembly & test 

“die level processing” part which consists in wafer 

probing, chip-to-wafer bonding, balling, underfilling 

and inspection is certainly realized at Unisem in 

Malaysia while the final test and calibration of 

the 3-axis MEMS gyroscope sensor is likely to be 

processed at VTI in Finland. 

Whatever the supply chain scenario has been 

selected, the latest 3-axis MEMS gyroscope of 

VTI is a real achievement in regards to the use of 

engineering substrates (with cavity-SOI and TGV 


glass interposer wafers) and prove once again that 

MEMS manufacturers have been early adopters of 

3D TSV and Wafer-Level-Packaging technologies 

as size and cost matter a lot in the area of MEMS 

Packaging. Indeed, packaging, assembly & test 

often accounts about > 60-70% of the total cost of 

nowadays MEMS modules. We estimate that in the 

case of the VTI’s 3-axis MEMS gyroscope module, 

the smart implementation of 3D TGV and Wafer- 

Level-Packaging concepts enabled the company 

to maintain the cost of the module packaging, 

assembly & test to a reasonably low 40-45% in total 

along with a real size reduction and performance 

breakthrough. 

VTI CMR3000 manufacturing cost 

breakdown 

ASIC 

Manufacturing 

Cost 

23% 

Back-End: 

Final test, Calibration 

& Yield losses cost 

16% 

MEMS Mid-End: 

Yield losses 

(Probe+Dicing) 

16% 

MEMS 

Front-End: 

c-SOI 

Manufacturing 

Cost 

11% 

MEMS 

Mid-End: 

Wafer-level 

Packaging 

Cost 

13% 

MEMS 

Front-End: 

Sensor+Cap 

Manufacturing 

Cost 

21% 


Romain Fraux, System Plus Consulting, 

and Jérôme Baron, Yole Développement 

VTI CMR3000 3-axis MEMS gyroscope (Courtesy of VTI Technologies) 

Romain Fraux, 

Electronics Cost 

Engineer, 

System Plus 

Consulting 

Romain Fraux is 

Project Manager 

for Reverse Costing 

analyses at System Plus Consulting. 

Since 2006, Romain is in charge of 

costing analyses of MEMS devices, 

Integrated Circuit and electronics 

boards. He has significant experience 

in the modeling of the manufacturing 

costs of electronics components. 

Romain has a BEng from Heriot-Watt 

University of Edinburgh, Scotland and 

a master’s degree in Microelectronics 

from the University of Nantes, France. 

29


E V E N T R E V I E W 

Advanced Packaging: leading edge technologies 

bring challenges and opportunities 

The SEMICON Europa is well known for the excellent conferences and courses. Year by year, top-speakers inform 

about the latest trends, new techniques and ideas as well as coming processes and systems. 

In October 2011 SEMICON Europa will be again 

the place-to-be for all experts with in-depth 

knowledge and for decision makers who want 

to be a step ahead. 

Tuesday, 11 – 12 October: 

Advanced Packaging Conference 

Top-speakers from Infineon, STMicroelectronics, 

ASE, Fraunhofer IZM, MSG Lithoglas, OSRAM, 

Heraeus or NANION are teaching about: 

(extract) 

• New Trends in Power Electronics Packaging 

• Fine Cu Wire Bonding in High Volume 

Manufacturing 

• 3D Wafer Level Packaging - Requirements & 

Technical Approaches 

• Sinter Glue – New Horizons for Semiconductor 

Packaging 

• Low Temperature Glass-Thin-Films for use in 

Power and Sensor Applications 

• Using Wafer Applied Underfill for 3D Packaging 

• Flip Chip Copper Pillar for Advanced CMOS : 

How to Anticipate a New Package Platform 

More topics and speakers on 

www.semiconeuropa.org 

Thursday, 13 October: 

3D IC perspectives and challenges: 

from R&D concept to manufacturing 

Everywhere in the world, the most advanced 

research labs and R&D institutes are working 

in this amazing architectural innovation on 

chips and wafers. This session will specifically 

review 3D perspectives and challenges as 

well as existing applications including design 

solutions. With speakers from CEA-Leti, IMEC, 

STMicroelectronics and Atrenta. 

Tuesday, 11 October: 

Packaging exhibitor presentation 

With Jan Vardaman, President of TechSearch 

International, Andy Langford from PandA 

Europe and Steffen Kröhnert from NANIUM. 

• “More than Moore” – Heterogeneous Integration 

on Wafer Level, enabled by fan-out WLP 

• Premolded QFN packages for RF&MEMS 

application 

With more than 350 exhibitors from 30 countries 

SEMICON Europe is the largest show for the 

semiconductor industry in Europe. Be part of it! 

For more information and registration visit 

www.semiconeuropa.org 

3-D Architectures for Semiconductor 

Integration and Packaging 

Today’s Manufacturing Advances, Tomorrow’s Impact and Opportunity 

Make plans to 

attend today ... 

This conference provides a unique perspective 

of the techno-business aspects of the emerging 

commercial opportunity offered by 3-D integration 

and packaging—combining technology 

with business, research developments with 

practical insights—to offer industry leaders the 

information needed to plan and move forward. 

12–14 DECEMBER 2011 

Hyatt Regency 

San Francisco Airport Hotel 

Burlingame, California 

For more information visit: 

http://techventure.rti.org 


All over the World, 

stay connected 

Our readers, 

your business... 

Become 

a sponsor 

today! 

In-depth Market & Technology Analysis 

Combined reach to over 16,000 subscribers 

For more information, please visit www.i-micronews.com 

Editorial, Advertising & Subscriptions: S. Leroy (leroy@yole.fr)


About Yole Développement 

Beginning in 1998 with Yole Développement, we have grown to become a group of companies providing market research, technology analysis, 

strategy consulting, media in addition to finance services. With a solid focus on emerging applications using silicon and/or micro manufacturing 

Yole Développement group has expanded to include more than 40 associates worldwide covering MEMS and Microfluidics, Advanced Packaging, 

Compound Semiconductors, Power Electronics, LED, and Photovoltaic. The group supports companies, investors and R&D organizations worldwide 

to help them understand markets and follow technology trends to develop their business. 

CONSULTING SERVICES 

• Market data, market research and marketing analysis 

• Technology analysis 

• Reverse engineering and reverse costing 

• Strategy consulting 

• Corporate Finance Advisory (M&A and fund raising) 

CONTACTS 

For more information about : 

• Services : Jean-Christophe Eloy (eloy@yole.fr) 

• Reports: David Jourdan (jourdan@yole.fr) 

• Media : Sandrine Leroy (leroy@yole.fr) 

REPORTS 

• Collection of market & technology reports 

• Players & market databases 

• Manufacturing cost simulation tools 

• Component reverse engineering & costing analysis 

More information on www.yole.fr 

MEDIA 

• Critical news, Bi-weekly: Micronews, the magazine 

• In-depth analysis & Technology Magazines: MEMS Trends – 3D Packaging – PV Manufacturing – iLED - Power Dev’ 

• Online disruptive technologies website: www.i-micronews.com 

• Exclusive Webcasts 

• Live event with Market Briefings 

Editorial Staff 

Managing Editor: Jean-Christophe Eloy - Editor in chief: Jérôme Baron - Editors : Lionel 

Cadix, Phil Garrou, Jean-Marc Yannou, Sally Cole Johnson - Manager: Sandrine Leroy - 

Assistant: Camille Favre - Production: atelier JBBOX

3D Wafer-Level - Yole Developpement

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