FPGA-Based Search Acceleration for Big Data Networks - Ethernet ...

FPGA-Based Search Acceleration
for Big Data Networks
Dr. John W. Lockwood
CEO, Algo-Logic Systems, Inc.
April 3, 2013
Ethernet Technology Summit : Session A-103.
Accelerating Big Data with High-Speed Ethernet
(System Acceleration Track)
Santa Clara, CA USA
April 2013 1

FPGA Acceleration for Big Data
• Benefits of Hardware Acceleration
• Combines the benefits of programmability
– Soft implementation of key features
– Lower time to market
• With
– Ability to search and process packets at full line rate
– Wire-speed, deterministic processing of Packets
• FPGA Gateware
• Logic cores implemented in programmable logic
• Enables wire-speed 100 Gbps packet processing
• Performs customized associative search for traffic
groups and exact matching for individual flows

• Function
• Matches input
fields
– To values
– With mask
• Returns highest
priority match
• Exact Match
Big Data Search and Packet
Classification with Ternary CAMs
• Fields exactly matches value in CAM
• Typically used to match TCP/IP flows
• Associative Match
CAM_MASK_1
CAM_VALUE_1
Prt
Src IP
CAM_VALUE_2
CAM_MASK_2
Dest IP
• Wildcards allow comparison of certain fields
• Typically used for Access Control Lists (ACLs)
Src
Port
Dest
Port
…
Match

Gateware Defined Networking®
for Big Data
• Gateware
• Algorithms in Field Programmable Gate Array (FPGA)
devices process large volumes of data in logic
Hardware
Gateware
Software
• Gateware Defined Networking® (GDN)
• Programmable logic in a network system providing
ultra low latency (sub-µs), 100% deterministic,
high throughput processing of (100 Gbps+) Ethernet
and Internet Protocol (IP) packets
ASIC Switch
Hardware
GDN Cores
(Algo-Logic)
SDN Controllers
(Openflow…)
Gateware Defined Networking is a registered trademark of Algo-Logic Systems, Inc.

GDN Use-Case Applications
for Big Data
• GDN enables 100 Gbps+ Packet Search
• Access Control List (ACL) filters
• Firewalls
• Routers
• Flow Controllers
• VOIP switches
• Quality of Service classifiers
• Load Balancers
• L2-L7 Content Matching
• Using soft IP blocks implemented in
Programmable Logic

• Pre-built soft IP cores
Algo-Logic’s GDN Library
• Algorithms implemented in programmable Logic
• Runs in FPGA hardware
• Connects to SDN switch ASIC
• Augment features of existing SDN hardware
• Library Includes new
• 2 nd Generation Algorithmic Ternary Search Engine
(TSE2)
– Associative Ternary Search Engine (ATSE-2)
– Searches Access Control List rule list with wildcards
– Exact Match Search Engine (EMSE-2)
– Matches Ethernet hosts and TCP/IP Network Flows

Ternary Search Engine (TSE2)
• Processes data from Client device
• Search field extracted
from Ethernet, IPv4, &
IPv6 packet headers
• Supports
• { search, insert,
modify, deletion }
of TCAM rules
• Response Interface
• Identifies matching rule
• Also returns user-defined result
– Eliminating need for extra SRAM

TSE-2 Features
• High Search Rate
• Up to 156.25 Million Searches Per Second
(MSPS)
– per soft IP core
• Up to 625 MSPS
– with four cores on one device
• Highly configurable cores
• Width of key between 80 to 640 bits
• Table sizes from 768 to 12M entries
• Flexible interface to software
• Provides simple registers that are
read and written from software
• Auto invalidation of aged out entries
• Provides notification for aged out

Logical Interface to Core
• Algorithmic Search Engine provides same type of
I/O interface as traditional TCAM
• As soft logic that fits in programmable chip

TSE2’s Multiple Configurations
• Associative Match (ATSC-2) and/or
• Exact Match Search (EMSE-2)
• Hybrid / Off-chip DDR3 for up to 12M Flows

About Algo-Logic Systems
Algo-Logic specializes in mapping algorithms into
logic. Algo-Logic engineers are experts in
developing, prototyping, and deploying hardwareaccelerated
networking systems with FPGAs and
reprogrammable hardware.
Algo-Logic has extensive expertise in building FPGA
circuits that power Gateware Defined Networking
(GDN) used in Software Defined Networks
(SDNs), Packet processing, Embedded systems
and Accelerated Finance
Algo-Logic is led by John W. Lockwood, PhD, a
professor who developed the FPX platform at
Washington University and managed the
NetFPGA team at Stanford University.
Web
http://Algo-Logic.com
Email
Solutions@Algo-Logic.com
Office Address
2255-D Martin Ave.
Santa Clara, CA 95050
Phone
(408) 707-3740