Packaging Effect on Reliability for Cu/Low k Damascene ... - Sematech

<strong>Packaging</strong> <strong>Effect</strong> on Reliability for
Cu/Low k Damascene Structures*
Guotao Wang and Paul S. Ho
Laboratory of Interconnect & <strong>Packaging</strong>
The University of Texas at Austin, TX 78712
* Work supported by SRC through the CAIST Program
TRC 2003
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1. Introduction
<strong>Packaging</strong> requirements and processes
<strong>Packaging</strong> impact on reliability for Cu interconnect
2. Multilevel sub-modeling technique
3D Modeling with Modified Virtual Crack Closure
(MVCC) method
3. Simulation results
Results for TEOS and low k structures
Line dimension scaling effect
Parametric study for package level components
- Material and size effect for underfilled packages
- <strong>Effect</strong> of solder reflow without underfill in plastic
packages
4. Recent fracture studies on low k structures
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Single-chip <strong>Packaging</strong> Technology Requirements
Year of Production
2001
2002
2003
2004
2005
2006
2007
Chip Size (mm 2 )
Hand-held
57
59
61
63
65
65
65
High-performance
310
310
310
310
310
310
310
Power: Single Chip Package (Watts)
Hand-held
2.4
2.6
2.8
3.2
3.2
3.5
3.5
High-performance
130
140
150
160
170
180
190
Package Pin Count Maximum
Hand-held
100-420
112-464
122-508
134-560
144-616
160-680
176-748
High-performance
1700
1870
2057
2263
2489
2738
3012
Sub-threshold Leakage Current, I sd,leak
(@25C)
Nominal low-power NMOS
(pA/μm)
100
100
100
300
300
300
700
Nominal high-performance
NMOS (μA/μm)
0.01
0.03
0.07
0.1
0.3
0.7
1
Int. Semicond. Tech. Roadmap Update 2002
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Flip-Chip <strong>Packaging</strong>
Die
Solder bumping
Substrate
Solder reflow
183ºC 37Pb/63Sn
High stress in the package during
cooling down to room temp.
Underfilling
125º to 180ºC
Thermal cycling
-55 o C-125 o C
High stress can be introduced during
thermal cycling.
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Wire-bond <strong>Packaging</strong>
Die
Substrate
Die attach
150º to 300ºC
High stress at bond pad
during wire bonding.
Wire bonding
Encapsulation
140º to 160ºC
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Oxide → low k
Low k dielectrics have
Weak mechanical strength
Large coefficient of thermal
expansion
Poor adhesion to cap and
barrier layers
Interfacial delamination is a
serious reliability concern for
Cu/low k interconnects
~10mm
Active Side
Silicon Chip
Passivation
Metal
Dielectric
Device Level
Interfacial delamination
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Interfacial Delamination
Interfacial delamination
The crack driving force can be evaluated from the
energy release rate (ERR) using finite element
analysis.
For a stand-alone Cu/low k interconnects,
ERR has been calculated to be about 1 J/m 2 during
cooling from 400 o C to room temperature.
The fracture energy, or the critical ERR, is usually
about 4-5 J/m 2 for low k interfaces (lower for porous
ILD) and considerably higher for TEOS interfaces.
(Y. Du et al., Proceedings of ECTC, 2002)
Sub-critical crack growth instead of critical fracture will be
more of concern for stand-alone Cu/low k structures
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Solder bump
Die
BT substrate
Underfill
Solder bump
Underfill
BT substrate
Through hole via
Die
High density
signal layer
Material mismatch and processing can induce thermal
deformation and stress concentration in flip-chip packages:
<strong>Packaging</strong> effect on low k interconnect reliability
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Verification with Moiré Interferometry
0
Package cross-section
U Field
Displacement (um)
-1
-2
-3
-4
-5
-6
Moire result
FEA result
0 0.5 1 1.5 2 2.5 3 3.5 4
Distance from neutral point (mm)
Package warpage
V Field
High resolution moiré interferometry was used to measure the
thermal deformation in the flip-chip package and verified the
modeling results at the package level.
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High resolution U phase map (208nm per fringe)
U
Thermal load 20°C to 102°C
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High resolution V phase map (208nm per fringe)
V
Thermal load 20°C to 102°C
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Displacement distribution
(U field, 52nm per contour)
U
Thermal load 20°C to 102°C
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Displacement distribution
(V field, 52nm per contour)
V
Thermal load 20°C to 102°C
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Shear strain γ xy distribution at the solder bump
A
B
C
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Normal strain ε y distribution at the solder bump
A
B
C
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Impact from <strong>Packaging</strong>
For a chip attached to a board,
Large thermal stresses are induced due to thermal
mismatch between package level components.
In a plastic underfilled flip-chip package,
Large peeling stress at chip/solder bump or
chip/underfill interface due to thermal mismatch
between solder and underfill.
Large shear and tensile stress at die corner due to
thermal mismatch between die and PCB.
(M.R. Miller et al., Proceedings ECTC, p.979, 1999)
<strong>Effect</strong> of thermal stress induced by packaging on
structural reliability of Cu/low k interconnects
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Finite Element Analysis
To study packaging impact on interconnect reliability
In FEA model, details for both packaging and
interconnect levels have to be considered.
Modeling challenges
Maximum dimension at package level: 10 to 30mm
Minimum dimension at interconnect level: 20nm or
less for barrier layer
The ratio can be as high as 10 6 . It is impossible to
consider the details of interconnect structures when
modeling a whole package.
Solution: multilevel sub-modeling technique
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Multilevel Sub-model
A 4-level 3D sub-model was developed to analyze
Cu interconnects in flip-chip packages
Starting from the packaging level, sub-modeling
was conducted one level of detail at a time to
reach the interconnect level.
ANSYS built-in cut boundary technique was used
at each sub-modeling level.
At the final interconnect level, a crack with fixed
length was introduced at various relevant
interfaces. A Modified Virtual Crack Closure
(MVCC) method was used to calculate the crack
driving force (energy release rate).
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Hierarchical Levels of Submodeling
Level 1: Package level
Level 2: Critical Solder Region
Level 3: Die-Solder Interface
Level 4: Detailed Interconnect
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Level 1: Flip-chip Package
Die
Underfill
PCB
PCB
Die
At the package level, a quarter section of the package was modeled
based on symmetry. Details of the interconnect structure was not
considered because of its small dimension.
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Verification with Moiré Interferometry
0
Package cross-section
U Field
Displacement (um)
-1
-2
-3
-4
-5
-6
Moire result
FEA result
0 0.5 1 1.5 2 2.5 3 3.5 4
Distance from neutral point (mm)
Package warpage
V Field
High resolution moiré interferometry was used to measure the
thermal deformation in the flip-chip package and verified the
modeling results at the package level.
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Level 2: Critical Solder Region
Die
Critical solder bump
Underfill
PCB
With underfill shown
Without underfill shown
The sub-model focused on the critical solder bump region
with a uniform ILD layer at the die surface but no detailed
interconnect structure included.
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Level 3: Die-Solder Interface
Die (Si)
BPS
G
ILD
PASS
Solder pad
This sub-model focused on the die-solder interface region
containing a portion of die, ILD layer and a portion of solder
bump but included only a uniform ILD layer for the interconnect.
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Level 4: Detailed Interconnects
Si
Metal Line
BPSG
Metal 1
ILD
PASS
Solder pad
Metal 2
This sub-model focused on the die-solder interface taking into account
the detailed interconnect structure. A crack with fixed length was
introduced along various interfaces to calculate the crack driving force.
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z
y
x
MVCC Technique
(Modified Virtual Crack Closure)
∆A
2 1
3
∆A
FEA elements and nodes near crack tip
(2)
δ z
2
G
3
(1)
F z
1
(1)
F z
Mode 1 component
I
= F δ
(1)
z
(2)
z
/(2∆A)
(2)
δ x
2
3
(1)
F x
1
(1)
F x
Mode 2 component
G
II
= F δ
(1)
x
(2)
x
/(2∆A)
G
(2)
δ y
Total energy release rate:
2
(1)
F y
1
(1)
F y
3
Mode 3 component
III
= F δ
(1)
z
(2)
z
/(2∆A)
G = G + G +
I
II
F X , F y and F z are nodal forces at
node 1 along x,y and z direction,
respectively.
δ X , δ y and δ z are relative
displacements between node 2
and 3 along x,y and z direction,
respectively.
G
III
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Interconnect Interfaces
BPSG
M1
Via
ILD
Crack 6
Crack 5
Crack 1 Crack 4
PASS
M2
Solder pad
Crack 4, 5 and 6 are at the horizontal cap and barrier layer
interfaces. Crack width is taken to be the line width.
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Interconnect Interfaces (cont’d)
BPSG
ILD
ILD
Metal 1
Crack 3
Crack 2
Barrier
TiN
Crack 2 and 3 are at the vertical barrier interfaces.
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Material Properties
Materials
Al
Cu
TEOS
SiLK
Underfill
PCB
E ( GPa )
72
122
66
2.45
6.23
Anisotropic
ν
0.36
0.35
0.18
0.35
0.40
elastic property
CTE (×10 -6 /C)
24
17
0.57
66
40.6
16 (in plane)
84 (out of plane)
Thermal loading: for stand-alone wafer structure from 400 o C to
25 o C and for packaging from –55 o C to 125 o C.
All materials are taken to be linear elastic.
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ERR (J/m^2)
1.2
1
0.8
0.6
0.4
ERR for Stand–alone Wafer Structures
(from 400 o C to 25 o C)
Al/TEOS Structure
Cu/TEOS Structure
Cu/SiLK Structure
0.2
0
crack 1 crack 2 crack 3 crack 4 crack 5 crack 6
The SiLK/barrier interface in Cu/SiLK structure has the highest
energy release rate (about 1.16 J/m 2 ). Fracture mode is
primarily mode I driven by the high CTE of SiLK.
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<strong>Packaging</strong> effect (-55 o C to 125 o C)
ERR (J/m^2)
18
15
12
9
6
Al/TEOS Structure
Cu/TEOS Structure
Cu/SiLK Structure
3
0
crack 1 crack 2 crack 3 crack 4 crack 5 crack 6
<strong>Packaging</strong> has little effect on energy release rate for Al/TEOS or
Cu/TEOS structure, but is significant for Cu/SiLK structure. Mixedmode
delamination with both peeling and shear stresses contributing.
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Why energy release rate is much higher in
Cu/low k structure than in Cu/TEOS structure
Assuming that the thermal stress induced from package level
deformation is σ, the strains for low k ILD and TEOS will be
σ
σ
ε
SiLK
= , εTEOS
=
for simple 1-D case
E
E
SiLK
TEOS
The strain energy densities for SiLK and TEOS are
ξ
ξ
SiLK
TEOS
1
= σε
2
1
= σε
2
SiLK
TEOS
=
=
1
2
1
2
σ
E
2
SiLK
σ
E
2
TEOS
E SiLK is about 30 times lower than E TEOS , hence the strain energy
density in SiLK will be about 30 times higher, leading to a much higher
energy release rate in the Cu/SiLK structure.
Confinement effect due to the damascene structure also affects the
stress driving force and deformation behavior of the interconnect.
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Scaling <strong>Effect</strong>
Cu/SiLK Structure, SiLK/PASS Interface
1.2
1
Normalized ERR
0.8
0.6
0.4
0.2
wafer level only (400--25oC)
<strong>Packaging</strong> effect (-55--125oC)
0
0.1 0.2 0.3 0.4 0.5
Line width (um)
The driving force for interface fracture increases slightly with
decreasing line width at Cu SiLK/PASS interface.
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<strong>Effect</strong> of Die Attach Process
A critical process step in flip-chip packaging is the solder
reflow step before underfilling the package. Without
underfill serves as a stress buffer, thermal mismatch
between the die and substrate can generate large thermal
stress at the solder/die interface near the die corner.
Solder reflow temperatures are different for Pb-based and
Pb-free solders. Thermal loads used in our simulation:
• High lead solder: 300 o C-25 o C
• Eutectic solder: 160 o C-25 o C
• Lead free solder: 250 o C-25 o C
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Parametric Study of Die Attach Process
1. Substrate effect
Plastic vs. ceramic substrate
2. Die size:
7x8mm vs. 13.4x14.4mm die
3. Solder materials:
High lead solder
Eutectic solder
Lead free solder
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Material Properties
E(GPa)
v
CTE(x10 -6 )
Die
162
0.28
2.6
Plastic substrate
Anisotropic elastic
property
16(in plane)
84(out of plane)
Ceramic substrate
300
0.3
5.0
High lead solder
50.81-0.102*T
0.35
29.7
Eutectic solder
75.84-0.152*T
0.35
24.5
Lead free solder
88.53-0.142*T
0.40
16.5
Underfill 1
8.40
0.40
28.0
Underfill 2
7.10
0.40
34.0
Underfill 3
6.23
0.40
40.6
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ERR(J/m^2)
36
30
24
18
12
Solder Materials <strong>Effect</strong>
(Plastic substrate, 7x8mm die)
High lead solder package
Eutectic solder package
Lead-free solder package
6
0
crack 1 crack 2 crack 3 crack 4 crack 5 crack 6
Solder reflow before underfill increases the driving force
for interfacial delamination in Cu/SiLK structures,
particularly for lead-free solders.
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Substrate <strong>Effect</strong>
(Eutectic solder, 7x8mm die)
8
Plastic substrate
6
Ceramic substrate
ERR (J/m^2)
4
2
0
crack 1 crack 2 crack 3 crack 4 crack 5 crack 6
Solder reflow reduces significantly the driving force for
interfacial delamination in Cu/SiLK structure for packages with
ceramic substrate compared to plastic substrate.
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Die Size <strong>Effect</strong>
(Plastic substrate, Eutectic solder)
10
8
8x7mm Die
14.4x13.4mm Die
ERR (J/m^2)
6
4
2
0
crack 1 crack 2 crack 3 crack 4 crack 5 crack 6
During reflow, the driving force for interface fracture
increases with increasing die size. The effect is larger for
high lead solders due to a higher reflow temperature
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Summary
Maximum energy release rate (J/m 2 ) for
0.5 mm line width
Interfaces
ILD/PASS
ILD/BARR
Metal/PAS
S
Metal/BARR
Wafer level
0.0076
0.3854
0.2044
0.4375
Al/TEOS
<strong>Packaging</strong>
0.2086
0.0845
0.0630
0.0716
Wafer level
0.0072
0.3669
0.2079
0.4287
Cu/TEOS
<strong>Packaging</strong>
0.2095
0.0865
0.0617
0.0702
Wafer level
0.2908
1.1556
0.1718
1.0476
Cu/SiLK
<strong>Packaging</strong>
8.3392
11.1109
16.7080
7.5216
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Conclusions
3D multilevel sub-modeling technique was developed to investigate
the packaging effect on interfacial fracture for TEOS and low k
interconnect structures.
For stand-alone interconnects, the crack driving force for interfacial
delamination is usually lower than the critical fracture energy, so
subcritical crack growth and fatigue crack growth are important in
controlling structural reliability.
<strong>Packaging</strong> effect can significantly increase the energy release rate
to cause critical crack growth in Cu/low k structures, particularly at
the interfaces parallel to the chip surface.
Interfacial chemical bonds are important in controlling interfacial
adhesion. Residual stress can enforce thermal stress to drive crack
growth, particularly in a humid environment. The effect on low k
interconnect reliability has to be investigated.
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