ITG-3050 Product Specification Revision 1.3 - InvenSense
ITG-3050 Product Specification Revision 1.3 - InvenSense
ITG-3050 Product Specification Revision 1.3 - InvenSense
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<strong>ITG</strong>-<strong>3050</strong> <strong>Product</strong> <strong>Specification</strong><br />
Document Number: PS-<strong>ITG</strong>-<strong>3050</strong>-00<br />
<strong>Revision</strong>: <strong>1.3</strong><br />
Release Date: 08/25/2011<br />
4.4 Recommended Power-on Procedure<br />
VDD<br />
All Voltages at 0V<br />
T VDDR<br />
10%<br />
90%<br />
Power-Up Sequencing<br />
1. T VDDR is VDD rise time: Time for VDD to<br />
rise from 10% to 90% of its final value<br />
2. T VDDR is ≤5ms<br />
3. T VLGR is VLOGIC rise time: Time for<br />
VLOGIC to rise from 10% to 90% of its<br />
final value<br />
90%<br />
T VLGR<br />
4. T VLGR is ≤1ms<br />
5. T VLG-VDD is the delay from the start of<br />
VDD ramp to the start of VLOGIC rise<br />
VLOGIC<br />
10%<br />
6. T VLG-VDD is ≥0ms; VLOGIC amplitude<br />
must always be ≤VDD amplitude<br />
T VLG - VDD<br />
7. VDD and VLOGIC must be monotonic<br />
ramps<br />
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