ITG-3050 Product Specification Revision 1.3 - InvenSense
ITG-3050 Product Specification Revision 1.3 - InvenSense ITG-3050 Product Specification Revision 1.3 - InvenSense
ITG-3050 Product Specification Document Number: PS-ITG-3050-00 Revision: 1.3 Release Date: 08/25/2011 3.6 Absolute Maximum Ratings Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for extended periods may affect device reliability. Absolute Maximum Ratings Parameter Rating Supply Voltage, VDD -0.5V to +6V VLOGIC Input Voltage Level -0.5V to VDD + 0.5V REGOUT Input Voltage Level (CLKIN, AUX_DA, AD0, FSYNC, INT, SCL, SDA) CPOUT (2.1V ≤ VDD ≤ 3.6V ) Acceleration (Any Axis, unpowered) Operating Temperature Range Storage Temperature Range Electrostatic Discharge (ESD) Protection Latch-up -0.5V to 2V -0.5V to VDD + 0.5V -0.5V to 30V 10,000g for 0.3ms -40°C to +105°C -40°C to +125°C 1.5kV (HBM); 200V (MM) JEDEC Class II (2),125°C Level B, ±60mA 14 of 42
ITG-3050 Product Specification Document Number: PS-ITG-3050-00 Revision: 1.3 Release Date: 08/25/2011 4 Applications Information 4.1 Pin Out and Signal Description Pin Number Pin Name Pin Description 1 CLKIN External reference clock input. Connect to GND if not used. 6 AUX_DA 7 AUX_CL Interface to a 3 rd party accelerometer, SDA pin. Logic levels are set to be either VDD or VLOGIC. See Section 6 for more details. Interface to a 3 rd party accelerometer, SCL pin. Logic levels are set to be either VDD or VLOGIC. See Section 6 for more details. 8 VLOGIC Digital I/O supply voltage. VLOGIC must be ≤ VDD at all times. 9 AD0 I 2 C Slave Address LSB 10 REGOUT Regulator filter capacitor connection 11 FSYNC Frame synchronization digital input. Connect to GND if not used. 12 INT Interrupt digital output (totem pole or open-drain) 13 VDD Power supply voltage and Digital I/O supply voltage 18 GND Power supply ground 19 RESV Reserved. Do not connect. 20 CPOUT Charge pump capacitor connection 21 RESV Reserved. Do not connect. 22 CLKOUT 1MHz clock output for 3 rd -party accelerometer synchronization 23 SCL I 2 C serial clock 24 SDA I 2 C serial data 2, 3, 4, 5, 14, 15, 16, 17 NC Not internally connected. May be used for PCB trace routing. RESV CPOUT RESV CLKOUT SCL SDA 24 23 22 21 20 19 CLKIN 1 18 GND NC 2 17 NC +Z NC NC 3 4 ITG-3050 16 15 NC NC ITG-3050 NC 5 14 NC AUX_DA 6 7 8 9 10 11 12 13 VDD +Y +X INT FSYNC REGOUT AD0 VLOGIC AUX_CL QFN Package (Top View) 24-pin, 4mm x 4mm x 0.9mm Orientation of Axes of Sensitivity and Polarity of Rotation 15 of 42
- Page 1 and 2: ITG-3050 Product Specification Docu
- Page 3 and 4: ITG-3050 Product Specification Docu
- Page 5 and 6: ITG-3050 Product Specification Docu
- Page 7 and 8: ITG-3050 Product Specification Docu
- Page 9 and 10: ITG-3050 Product Specification Docu
- Page 11 and 12: ITG-3050 Product Specification Docu
- Page 13: ITG-3050 Product Specification Docu
- Page 17 and 18: ITG-3050 Product Specification Docu
- Page 19 and 20: ITG-3050 Product Specification Docu
- Page 21 and 22: ITG-3050 Product Specification Docu
- Page 23 and 24: ITG-3050 Product Specification Docu
- Page 25 and 26: ITG-3050 Product Specification Docu
- Page 27 and 28: ITG-3050 Product Specification Docu
- Page 29 and 30: ITG-3050 Product Specification Docu
- Page 31 and 32: ITG-3050 Product Specification Docu
- Page 33 and 34: ITG-3050 Product Specification Docu
- Page 35 and 36: ITG-3050 Product Specification Docu
- Page 37 and 38: ITG-3050 Product Specification Docu
- Page 39 and 40: ITG-3050 Product Specification Docu
- Page 41 and 42: ITG-3050 Product Specification Docu
<strong>ITG</strong>-<strong>3050</strong> <strong>Product</strong> <strong>Specification</strong><br />
Document Number: PS-<strong>ITG</strong>-<strong>3050</strong>-00<br />
<strong>Revision</strong>: <strong>1.3</strong><br />
Release Date: 08/25/2011<br />
4 Applications Information<br />
4.1 Pin Out and Signal Description<br />
Pin Number Pin Name Pin Description<br />
1 CLKIN External reference clock input. Connect to GND if not used.<br />
6 AUX_DA<br />
7 AUX_CL<br />
Interface to a 3 rd party accelerometer, SDA pin. Logic levels are set to be<br />
either VDD or VLOGIC. See Section 6 for more details.<br />
Interface to a 3 rd party accelerometer, SCL pin. Logic levels are set to be<br />
either VDD or VLOGIC. See Section 6 for more details.<br />
8 VLOGIC Digital I/O supply voltage. VLOGIC must be ≤ VDD at all times.<br />
9 AD0 I 2 C Slave Address LSB<br />
10 REGOUT Regulator filter capacitor connection<br />
11 FSYNC Frame synchronization digital input. Connect to GND if not used.<br />
12 INT Interrupt digital output (totem pole or open-drain)<br />
13 VDD Power supply voltage and Digital I/O supply voltage<br />
18 GND Power supply ground<br />
19 RESV Reserved. Do not connect.<br />
20 CPOUT Charge pump capacitor connection<br />
21 RESV Reserved. Do not connect.<br />
22 CLKOUT 1MHz clock output for 3 rd -party accelerometer synchronization<br />
23 SCL I 2 C serial clock<br />
24 SDA I 2 C serial data<br />
2, 3, 4, 5, 14,<br />
15, 16, 17<br />
NC<br />
Not internally connected. May be used for PCB trace routing.<br />
RESV<br />
CPOUT<br />
RESV<br />
CLKOUT<br />
SCL<br />
SDA<br />
24 23 22 21 20 19<br />
CLKIN<br />
1<br />
18<br />
GND<br />
NC<br />
2<br />
17<br />
NC<br />
+Z<br />
NC<br />
NC<br />
3<br />
4<br />
<strong>ITG</strong>-<strong>3050</strong><br />
16<br />
15<br />
NC<br />
NC<br />
<strong>ITG</strong>-<strong>3050</strong><br />
NC<br />
5<br />
14<br />
NC<br />
AUX_DA<br />
6<br />
7 8 9 10 11 12<br />
13<br />
VDD<br />
+Y<br />
+X<br />
INT<br />
FSYNC<br />
REGOUT<br />
AD0<br />
VLOGIC<br />
AUX_CL<br />
QFN Package (Top View)<br />
24-pin, 4mm x 4mm x 0.9mm<br />
Orientation of Axes of Sensitivity<br />
and Polarity of Rotation<br />
15 of 42
Change language