QDK PIC24/dsPIC-C30 - Quantum Leaps
QDK PIC24/dsPIC-C30 - Quantum Leaps
QDK PIC24/dsPIC-C30 - Quantum Leaps
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<strong>QDK</strong><br />
<strong>PIC24</strong>/<strong>dsPIC</strong>-<strong>C30</strong><br />
www.state-machine.com/pic<br />
1.2 About the QP Port to <strong>PIC24</strong>/<strong>dsPIC</strong><br />
Figure 3 shows the architecture of the QP port to <strong>PIC24</strong>/<strong>dsPIC</strong>. The port takes advantage of the<br />
<strong>PIC24</strong>/<strong>dsPIC</strong> interrupt priority level (IPL) management hardware. In both cooperative and preemptive QP<br />
ports the hardware priority levels are allocated as follows:<br />
1. All QP tasks (active objects) as well as the QP idle loop execute at the lowest IPL of zero.<br />
2. IPL levels 1 through 6 are used for maskable interrupts. These maskable interrupts (IPL 1..6) can call<br />
QP services, such as QF_tick(), QActive_postFIFO(), QF_publish(), and Q_NEW(). The<br />
maskable interrupts can nest on each other, which is the default in <strong>PIC24</strong>/<strong>dsPIC</strong>.<br />
3. This QP port never disables the IPL level 7, which is the Non-Maskable Interrupt (NMI) level. The<br />
NMI-level interrupt(s) cannot call any QP services. But the NMI can trigger a maskable interrupt, as<br />
shown by the dashed arrow in Figure 3. This triggered interrupt of IPL 1..6 can call QP services for<br />
signaling the QP tasks (active objects).<br />
Figure 3: Architecture of the <strong>PIC24</strong>/<strong>dsPIC</strong> port<br />
(IPL = 7) Non-Maskable Interrupt (NMI)<br />
IPL Level 7<br />
(NMI level)<br />
(IPL = 6) User interrupt<br />
(IPL = 5) User interrupt<br />
(IPL = 4) User interrupt<br />
IPL Levels 1-6<br />
(interrupt level)<br />
(IPL = 3) User interrupt<br />
(IPL = 2) User interrupt<br />
(IPL = 1) User interrupt<br />
(QP prio = n) User task (active object)<br />
(QP prio = n-1) User task (active object)<br />
. . .<br />
(QP prio = 2) User task (active object)<br />
IPL Level 0<br />
(task level)<br />
(QP prio = 1) User task (active object)<br />
(QP prio = 0) Idle task<br />
This layered software architecture fits very naturally with the <strong>PIC24</strong>/<strong>dsPIC</strong> hardware. The QP ports (both<br />
cooperative and preemptive) allow nesting of interrupts, which is the default in <strong>PIC24</strong>/<strong>dsPIC</strong>. Both<br />
cooperative and preemptive QP ports can work with the interrupt service routines (ISRs) generated by the<br />
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