QDK PIC24/dsPIC-C30 - Quantum Leaps
QDK PIC24/dsPIC-C30 - Quantum Leaps
QDK PIC24/dsPIC-C30 - Quantum Leaps
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<strong>QDK</strong><br />
<strong>PIC24</strong>/<strong>dsPIC</strong>-<strong>C30</strong><br />
www.state-machine.com/pic<br />
(6) The system clock tick ISR must invoke QF_TICK(), and can also perform other actions, if<br />
necessary. The function QF_TICK() cannot be reentered, that is, it necessarily must run to<br />
completion and return before it can be called again. This requirement is automatically fulfilled,<br />
because the same interrupt priority cannot preempt the running priority in <strong>PIC24</strong>/<strong>dsPIC</strong>.<br />
3.3.1 PSV Usage in ISRs<br />
This QP port to <strong>PIC24</strong>/<strong>dsPIC</strong> can work with ISRs that preserve the PSVPAG register as well as ISRs that<br />
don’t. The preserving of the PSVPAG register is controlled by the attributes auto_psv and no_auto_psv<br />
that the MPLAB <strong>C30</strong> compiler supports for this purpose (see Listing 4(2)).<br />
If an ISR references const variables or string literals using the constants-in-code memory model, the<br />
auto_psv attribute should be added to the ISR definition. This attribute will cause the compiler to<br />
preserve the previous contents of PSVPAG and set it to section .const. Upon exit, the previous value of<br />
PSVPAG will be restored. Alternatively, if the ISR does not access the PSVPAG access, the attribute<br />
no_auto_psv can be used (see Section 8.10 in [MPLAB <strong>C30</strong>] for more details). The no_auto_psv<br />
attribute results in slightly faster ISR with one register less saved on the stack.<br />
3.3.2 Shadow Registers Usage in ISRs<br />
The non-preemptive “vanilla” QP port to <strong>PIC24</strong>/<strong>dsPIC</strong> can work with ISRs that preserve the context in the<br />
shadow registers available in the <strong>PIC24</strong>/<strong>dsPIC</strong> CPU. To request the compiler to use the fast context save<br />
(using the push.s and pop.s instructions), tag the function with the __shadow__ attribute. For example:<br />
void __attribute__((__interrupt__, __shadow__)) _T2Interrupt(void);<br />
NOTE: Generally, shadow registers should be used at one IPL level only (typically the highest).<br />
When interrupt nesting is allowed, which is the default in the <strong>PIC24</strong>/<strong>dsPIC</strong> architecture, the shadow<br />
registers can get corrupted if they are used by interrupts of two or more different IPL levels.<br />
3.3.3 Assigning/Changing Interrupt Priorities in Software<br />
Each ISR in <strong>PIC24</strong>/<strong>dsPIC</strong> runs at a pre-configured IPL level. The default IPL level assigned to all ISRs out<br />
of reset is 4. It is strongly recommended, however, to assign priority to each used interrupt explicitly<br />
before enabling the interrupt. For example, the highlighted code in Listing 5 shows assigning the priority<br />
to the Timer2 interrupt in function QF_onStartup():<br />
Listing 5: Configuring interrupts in function QF_onStartup() (file bsp.c)<br />
#define TIMER2_ISR_PRIO 4<br />
. . .<br />
void QF_onStartup(void) { /* entered with interrupts locked */<br />
T2CON = 0; /* Use Internal Osc (Fcy), 16 bit mode, prescaler = 1 */<br />
TMR2 = 0; /* Start counting from 0 and clear the prescaler count */<br />
PR2 = BSP_TMR2_PERIOD - 1; /* set the timer period */<br />
_T2IP = TIMER2_ISR_PRIO; /* set Timer 2 interrupt priority */<br />
_T2IF = 0; /* clear the interrupt for Timer 2 */<br />
_T2IE = 1; /* enable interrupt for Timer 2 */<br />
T2CONbits.TON = 1; /* start Timer 2 */<br />
}<br />
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