QDK PIC24/dsPIC-C30 - Quantum Leaps

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PIC24/dsPIC-C30
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(9) The QF_CRIT_STAT_TYPE macro is not defined, which means that the simple policy of “unconditional
interrupt disabling and enabling” is applied (see Section 7.3 in [PSiCC2]).
(10) The critical section entry macro disables interrupts (see step (7)).
(11) The critical section exit macro unconditionally enables interrupts (see step (8)).
3.3 ISRs in the Non-Preemptive “Vanilla” Configuration
The MPLAB C30 compiler supports writing interrupts in C. In the non-preemptive “vanilla” port, the ISRs
are identical as in the simplest of all “superloop” (main+ISRs), and there is nothing QP-specific in the
structure of the ISRs. The only QP-specific requirement is that you provide a periodic system clock tick
ISR and you invoke QF_tick() in it. The ISRs are located in the bsp.c file found in the application
directory.
NOTE: The non-preemptive “vanilla” kernel allows interrupts nesting, as the interrupt preemptions
are handled entirely by the PIC24/dsPIC hardware.
Listing 4: The system tick interrupt calling QF_tick() function to manage armed time events.
(1) void __attribute__((__interrupt__,
(2) auto_psv))
(3) _T2Interrupt(void)
{
(4) _T2IF = 0; /* clear Timer 2 interrupt flag */
#ifdef Q_SPY
(5) l_tickTime += BSP_TMR2_PERIOD; /* account for TMR2 overflow */
#endif
(6) QF_TICK(&l_T2Interrupt); /* handle all armed time events in QF */
}
/* perform other work, if necessary */
(1) In the MPLAB C30 The ISR must be declared with the attribute __interrupt__.
(2) The auto_psv attribute will cause the compiler to preserve the previous contents of PSVPAG and
set it to section .const. Upon exit, the previous value of PSVPAG will be restored. Alternatively, if
the ISR does not access the PSVPAG access, the attribute no_auto_psv can be used (see Section
8.10 in [MPLAB C30] for more details).
NOTE: If you don’t explicitly specify the no_auto_psv attribute, the compiler will err on the safe side
and will implicitly insert the auto_psv atribute.
(3) Every ISR must be a void (void) function.
(4) Most ISRs in the PIC24/dsPIC architecture must explicitly clear the interrupt flag for the interrupt
source.
(5) When software tracing is enabled, the ISR updates the 32-bit time stamp at tick, which is used to
provide a 32-bit time stamp for the trace events.
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