QDK PIC24/dsPIC-C30 - Quantum Leaps

QDK
PIC24/dsPIC-C30
www.state-machine.com/pic
[PSiCC2]), because PIC24/dsPIC can mask interrupt groups (INT1 - INT12) and individual interrupts in
the Peripheral Interrupt Expansion (PIE) module. Listing 3 shows the qf_port.h header file for
PIC24/dsPIC.
Listing 3: The qf_port.h header file for PIC24/dsPIC.
/* The maximum number of active objects in the application, see NOTE01 */
(1) #define QF_MAX_ACTIVE 8
(2) #define QF_EVENT_SIZ_SIZE 1
(3) #define QF_EQUEUE_CTR_SIZE 1
(4) #define QF_MPOOL_SIZ_SIZE 1
(5) #define QF_MPOOL_CTR_SIZE 1
(6) #define QF_TIMEEVT_CTR_SIZE 2
/* QF interrupt disable/enable, see NOTE02 */
(7) #define QF_INT_DISABLE() __asm__ volatile("disi #0x3FFF")
(8) #define QF_INT_ENABLE() __asm__ volatile("disi #0x0000")
/* QF critical section entry/exit, see NOTE02 */
(9) /* QF_CRIT_STAT_TYPE not defined: unconditional interrupt unlocking" policy */
(10) #define QF_CRIT_ENTRY(dummy) __asm__ volatile("disi #0x3FFF")
(11) #define QF_CRIT_EXIT(dummy) __asm__ volatile("disi #0x0000")
#include "qep_port.h" /* QEP port */
#include "qvanilla.h" /* "Vanilla" cooperative kernel */
#include "qf.h" /* QF platform-independent public interface */
(1) The QF_MAX_ACTIVE specifies the maximum number of active object priorities in the application.
You always need to provide this constant in the QF port. Here, QF_MAX_ACTIVE is set to 8 to
conserve some RAM, but you can increase this value up to 63 inclusive.
(2-5) These object sizes in QF are all set to 1, meaning that uint8_t will be used to represent the various
object sizes.
NOTE: Please refer to Chapter 8 of [PSiCC2] for discussion of all configurable QF parameters.
(6) These time event counter is configured to 2-bytes, meaning that timeouts of up to 65535 clock ticks
can be handled in this QF port.
(7) The interrupt disable macro resolves to the single instruction DISI #0x3FFF, which disables
interrupts for 16383 instruction cycles. The number of cycles is much longer than any actual critical
section in QP.
NOTE: The DISI instruction only disables interrupts with priority levels 1-6. Priority level 7 interrupts
and all trap events still have the ability to interrupt the CPU when the DISI instruction is active. This
means that from the perspective of QP, the level 7 interrupts are treated as non-maskable interrupts
(NMIs). Such non-maskable interrupts cannot call any QP services. In particular, they cannot post
events (see also Section 5).
(8) The DISI #0 instruction is then used to unconditionally unlock the interrupts at the end of the critical
section.
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