AN068 - Design Steps and Results for Changing PCB Layer Thickness

Application Note AN068
AN068
Design Steps and Results for Changing PCB layer
thickness for Low Power Wireless Reference EVMs
By Rea Schmid
Keywords
• Board Stacking for RF Design
• VSWR changes with Stacking
• Bandwidth and Layer Stacking
• PCB for CC25xx Devices
• 062 Mil Layer Stacking
• FR4 Dielectric Material
• EVM for Low Power Wireless
• Board performance for RF Design
• Matching networks for PCB Boards
• Discrete Component Balun Design
• Matching antenna
• RF Filter Design
Introduction
Texas Instruments provides Evaluation
Modules (EVMs) for easy characterization
of the Low Power Wireless (LPW)
products. They provide a means to
understand the device’s operation, and
decrease the product development time.
Often a customer will copy the hardware
layout, and then make small changes that
can cause the performance to change.
The most common changes are modifying
the layer board stacking or changing
component placement. Each of these will
mistune the matching or filter networks
and even the antenna, reducing the
system performance.
Learning how the PCB layer stack causes
a mismatch at the RF connection between
the RF output pins to the antenna is the
scope of this application note.
TI’s Evaluation Boards are designed to be
flexible and easy to use. The boards are
designed to accommodate a range of
VSWR to make them acceptable for wide
range of use. All EVMs are designed for a
maximum VSWR of 2, which translates to
a minimum return loss (RL) of -9.5dB
derived from the S11 s-parameter.
Each TI device specifies a typical load
found in the data sheet that is used to
match and complete the maximum power
transfer. The spec is for a given
frequency of operation. The number is
used as the starting point for designing the
interface to a selected antenna. For many
applications the load is single ended; since
most chips provide a differential
input/output, the circuit often must include
a translation to interface to a single-ended
antenna. Typically these interfaces include
three circuit blocks consisting of a balun, a
filter/matching network, and finally a
connection to the antenna, either through
an SMA connector or directly connected.
A note about the use of discrete
components: values at 2.45GHz are often
small with units on the order of pico-farads
and nano-henries. Therefore, the final
solution performance is often sensitive to
layout traces and pads.
There are several methods used to design
and select the circuit components and
trace lengths. The methods often used
are Smith Charts, Simulation programs,
Circuit Analysis, or copying and scaling
existing designs. But at the higher
frequencies one must recognize the use of
tools greatly increases the accuracy of the
final design.
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Application Note AN068
Because of the high frequencies and the
fact we are using FR4 material, there are
many additional factors to consider; FR4
permittivity, stacking height, magnetic
fields, trace thickness and solder mask.
Not to mention it is difficult to make
measurements at these frequencies
without equipment like VNAs or TDRs.
For this discussion we tried to isolate the
effects of changing the stacking height to
better understand its impact upon the
overall board’s performance as one makes
this change. These results are included at
the end of the application note.
Keywords........................................................................................................................................................ 1
Introduction .................................................................................................................................................... 1
Abbrevations: ............................................................................................................................................. 3
LPW Evaluation Boards ................................................................................................................................. 4
Why RF designs change with Board Layer Stacking.................................................................................. 4
Circuit Schematic of balun/matching Network. .......................................................................................... 6
PCB Layout Techniques for Board Stacking Change..................................................................................... 6
2-Layer Designs.......................................................................................................................................... 6
PCB Traces and Transmission Lines .......................................................................................................... 7
Determine the Source Impedance ............................................................................................................... 8
Inductance from Vias.............................................................................................................................. 9
VCO or Crystal Filter ............................................................................................................................... 10
Figure 7, VCO crystal.............................................................................................................................. 10
Current Loops and Decoupling................................................................................................................. 10
Transmit & Receive Optimization ............................................................................................................ 11
Sample Design for Compact Design......................................................................................................... 12
Balun / Matching Network Measurements................................................................................................ 14
Sensitivity Comparison............................................................................................................................. 15
Power Output Comparison........................................................................................................................ 16
Spectrum of Board Noise Sources............................................................................................................ 17
Summary................................................................................................................................................... 18
RF Layout Tips............................................................................................................................................. 18
References .................................................................................................................................................... 19
General references .................................................................................................................................... 19
Document History......................................................................................................................................... 19
Figure 2, Schematic of Original Layout 6
Figure 3, 062 mil board layout 7
Figure 4, Microstrip line definition 7
Figure 5, Differential Conversion 9
Figure 6, via inductance and Capacitance 9
Figure 8, Placement of Decoupling Caps 11
Figure 9, Single-ended model 12
Figure 10, Differential Balun and Pi Filter 12
Figure 11, Smith Chart Plot of Components Only 13
Figure 12, Component Schematics only 13
Figure 13, 031 mill stacking, Impedance of EVM at Antenna SMA 14
Figure 14, 059 stacking height Impedance measured at SMA 15
Figure 15, Schematic of PCB model 15
Figure 16 Sensitivity Plot of 62mil (1.6mm) board 16
Figure 17, Sensitivity Plot of 31mil (1.0mm) PCB 16
Figure 18, Output Power Plot 1.6mm PCB 17
Figure 19, Original Output Power Plot. 17
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Application Note AN068
Figure 20, Spectrum of CC2500 18
Abbrevations:
VNA - Vector Network Analyzer (test equipment)
TDR - Time Domain Reflectometer (test equipment)
TEM - Transverse Electro - Magnetic Mode
FR4 - PCB board standard
SMA - Coaxial PCB connector
PCB - Printed Circuit Board
LPW - Low Power Wireless
EVM - Evaluation Module
MM - mili-meters
Mil - 1 thousand of an inch
VCO - voltage control oscillator
Balun - balance to unbalance transformer
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Application Note AN068
LPW Evaluation Boards
A LPW evaluation board provides a simple evaluation unit to quickly understand the technical
operation of a Low Power Wireless device from Texas Instruments. As the board is a working
solution to demonstrate both transmit / receive modes, customers can also evaluate a particular
transmit/receive device. They can quickly modify a specific application to gather measurements
related to their product design.
TI’s LPW evaluation boards include the trace layout, component values, the use of FR4 board
materials and board thickness to show typical performance for a device. The board serves also
as a reference design as one makes changes to a prototype board. It also cuts development time
and allows one to become familiar with the device without worrying about optimizing a RF prototype.
A LPW EVM provides a reference design that is tested and measured following many of the same
steps done in a design process as shown below. Using an evaluation unit is good practice and is
an excellent reference to compare or copy in your final design. A TI evaluation unit along with
development tools such as SmartRF platforms make it easier to complete a design with these
devices. The various items verified during EVM development are:
1. Bandwidth Optimized for Channel Data Rates and Power
2. Performance and Sensitivity Measurements
3. Differential to Single-ended Conversion
4. Matching to antenna Dipole, Micro-circuit or Chip
5. Proper routing of Ground and Power Returns
6. Low Electric Magnetic Emissions (EMI)
7. Characterization Measurements
8. Antenna Performance Measurements
Although these parameters are tested on the evaluation unit, one must realize these tests are the
results of the device, PCB board, and all circuit components. Changing a board means verifying
items as shown above prior to final release. The local TI representatives can provide assistance
or suggestions on tools or global standards when designing with TI wireless devices.
For this app note a CC2500 is used, but this report pertains to all devices which require RF layout
or board stacking changes. Keep in mind that different devices do have different output
impedances and/or output stages. Therefore the solutions might be slightly different for those
devices, such as CC110x series.
The stacking height that was chosen for the new evaluation unit using the CC2500 board is 62mil
(1.6mm). (The reference design has 31 mil, or 0.8 mm, layer spacing.) All calculations were
done in mils, but can easily be converted to meters by the following expression.
1
1 mil = ( inch)
= 25.4µ
m
1000
Why RF designs change with Board Layer Stacking
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Application Note AN068
When designing the balun and matching network for a RF device, the lessons to learn is the
component values are small at 2.45GHz, and PCB traces affect the performance. As the
component tolerances and component standard values prevent selection of the exact circuit
values, the components can be combined with the board’s traces/pads inductance and
capacitance values to fine tune a network. Doing this requires fewer components and makes it
easier to achieve VSWR closer to 1. This will work as long as one keeps the total length of
traces less than ¼ wavelength, then the traces are treated as inductors.
Because the component values are small at these frequencies, the trace and pad inductances
and capacitances change with layer stack height. This is easily seen if you work with a micro-strip
over a ground plane with air as one dielectric and the other a FR4 dielectric. The equation below
shows the impedance change with width and height, and includes the dielectric correction for the
FR4 PCB material. This equation below is used when the ratio of width to height is less than 1.
Z
o
60
eff
8 ⋅ h
⋅ln(
w
w
+ )
4 ⋅ h
=
ε
⎥ ⎥⎥⎥ ⎦
Where; h is the board stacking layer spacing
w is the trace width
ε eff is the dielectric correction for FR4 derived from free space dielectric permittivity
Because we working with two different dielectrics, air and FR4, the correction factor for dielectric
is;
ε
eff
⎡
ε
⎢
r
+ 1 ε
r
−1
= + ⋅ ⎢
2 2 ⎢
⎢
⎣
1
12⋅
h
1+
w
⎛ ⎛ w ⎞⎞
+ 0.04⎜1−
⎜ ⎟⎟
⎝ ⎝ h ⎠⎠
Where ε
r
is the permittivity of the FR4 material.
To better illustrate how the impedance changes with the width, height, and FR4 dielectric, a plot
(Figure 1) included shows how much change takes place.
Impedance change with stacking height
2
⎤
Impedance Zo
80
75
70
65
60
55
50
45
40
35
30
59 mil stacking
30 mil stacking
2 2.05 2.1 2.15 2.2
Permitivity Square Root e r
Figure 1, Impedance Plot verses layer stacking height
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Application Note AN068
The permittivity is plotted in square root since the equations uses the square root of the air
permittivity to derive the correct impedance along with the width to height ratio.
Since the areas of the traces are in order of 8 to 12 mils the traces are primarily inductive with a
small distributed capacitance. What is important to point out is that for a given stacking height the
variation of permittivity only changes the impedance slightly. Therefore, it can be seen that board
trace impedance is somewhat constant over manufacturing processes.
Circuit Schematic of balun/matching Network.
The schematic, Figure 2, shows the CC2500 balun, matching filter, and a 50 Ω trace to an SMA.
The schematic shows the values used on this board, and how small the component values are
when working at 2.45GHz.
Figure 2, Schematic of Original Layout
For a network that is well matched (VSWR=1) the values will be an exact match. But as will be
shown in this example the values selected on the 1mm (31mil) board are within the VSWR=2
circle, though slightly mismatched.
PCB Layout Techniques for Board Stacking Change
2-Layer Designs
2-layer designs typically require a little more care with the PCB routing than designs with designs
with dedicated power and ground planes, but can be successfully implemented, as shown in
Figure 3 (layout of the new 62 mil board); the original 30mil (0.8mm) is also on a 2-layer board.
Note that the power supply trace on the 062mil board below shows the component side trace is
made thick so as to present as low as impedance as possible. Large areas of ground on this side
of the board provide a low impedance path for decoupling. Whenever possible include a bottom
(copper) side of the board to allow for a solid plane under the RF circuitry. This design shows a
VSWR of

Application Note AN068
Figure 3, 062 mil board layout
A 2-layer PCB will be cheaper to manufacture than a 4-layer PCB. This paper shows that
microstrip or stripline transmission lines can be implemented on boards with layer spacings
exceeding 0.8mm - 1.00mm (0.031” - 0.039”) without an issue. The balun and filter trace widths
for the transmission line traces are kept short and become part of the tuning network with the final
trace to the SMA set for a 50 Ω impedance to match the antenna input. Note what is not shown
are the vias shorting the top (copper) ground to the bottom ground plane. These are necessary to
force FR4 board TEM resonance to a higher frequency than the CC2500’s 2.45GHz frequencies.
PCB Traces and Transmission Lines
Figure 4 illustrates an example of a PCB trace on the component or top side of the board that is
isolated by the PCB dielectric material (typically FR4) from the ground plane layer. From
knowledge of the physical properties of the PCB it is possible to construct a transmission line
trace with the desired characteristic impedance.
h
ε r
w
l = length of trace (inches)
w = width of trace (mils)
h = height of trace (mils)
t = thickness of trace (mils)
ε r = PCB Permittivity (FR-4 ≈
4.5)
2 ⋅ l
w + h
L(
nH)
= 5.08 ⋅ l ⋅ ln(( ) + 0.5 + 0. 2235⋅
w + h
l
t
2
CL = Z o
0
C(pF) ≈
Figure 4, Microstrip line definition
.67 ( + 1.41)
ln
5.98h
0.8w
+ t
10 mil trace on 0.031”or 0.059” thick PCB (FR4) has:
≈ 1.539nH for 100mil length
≈ 1.35pF / inch length
⎛
⎜
⎝
ε eff
⎞
⎟
⎠
Z o is the characteristic
impedances
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Application Note AN068
To calculate the required width of the PCB trace, W, it is first necessary to calculate the effective
dielectric constant, ε eff , 1 The effective dielectric constant is required because part of the field
generated by the conductor will exist in air ( ε
r
= 1) and part in the dielectric material. Assuming
that the thickness of the trace, T, is small compared to the height of the dielectric (T/H < 0.005),
then ε eff an be calculated using the following formula:
w
h
< 1
Z
o
60
eff
8 ⋅ h
⋅ln(
w
+
w
)
4 ⋅ h
e
eff
⎡
ε
⎢
r
+ 1 ε
r
− 1
= + ⋅ ⎢
2 2 ⎢
⎢
⎣
1
12 ⋅ h
1 +
w
⎛ ⎛ w ⎞ ⎞
+ 0.04⎜1
− ⎜ ⎟ ⎟
⎝ ⎝ h ⎠ ⎠
⎤
⎥
⎥
⎥
⎥
⎦
2
w
h
> 1
Z
o
=
e
eff
⎛w
⋅⎜
⎝ h
=
ε
w
120 ⋅π
w
+ 1.393 + 0.667 ⋅ln(
h
⎞
+ 1.444⎟
⎠
e
eff
ε
r
+ 1 ε
r
−1
= + ⋅
2 2
1
12 ⋅h
1+
Determine the Source Impedance
The equivalent circuit of the RF output is shown in Figure 5 below. The differential circuit is hard
to plot on a Smith Chart, so converting to a single-ended equivalent output source makes it easier
to use a Smith Chart and VNA when designing a balun.
1 I. J. Bahl and D. K. Trvedi, “A Designer’s Guide to Microstrip Line”, Microwaves, May 1977
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Application Note AN068
R diff
2
2 ⋅C diff
2 ⋅C diff
R diff
2
Figure 5, Differential Conversion
From the data sheet parameter spec page the recommended load impedance is given as
80+j74Ω. The conjugate of this number Z=Z* is the source’s impedance which is 80-j74Ω. We
normalize this signal by dividing by 50 Ω.
80 − j74
= 1.6 +
50
j1.48
This conjugate (1.6 – j1.48) would be the differential impedance looking back into the plus and
minus pins of the device. The negative –j implies a capacitance reactance, which we can find at
the frequency of 2.45GHz using the equation that X c is equal to j2πfC and Xc is 74 ohms.
1 −15
C diff
= = 878.0X10
2 πf 74
Inductance from Vias
Inductance in RF board design has the largest effect when changing the matching network, balun
design and antenna loads. Single- and multi-layer boards use vias to connect from one layer or
strip to another. The problem is of increased inductance and capacitance between those paths to
return grounds or signal paths. A typical via that connects a top layer ground plane to a bottom
ground plane results in a small inductance added between layers. This can be approximated by
the following formula in Figure 6.
⎡ ⎛ 4h
⎞ ⎤
L(nH) = 2 ⋅ h⎢ln⎜
⎟ + 1⎥
⎣ ⎝ d ⎠ ⎦
C(pF) =
0.55
d
2
ε
r
h d
− d
1
1
C ⋅L
=
2
Z o
h is thickness of PCB
ε r permittivity of FR4 board
d 1 diameter of the pad surrounding via
d 2 diameter of the pad connecting
ground plane layers.
Figure 6, via inductance and Capacitance
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Application Note AN068
For vias with no relief at the layer connections, d1 is zero, and the capacitance decreases.
Typically for a 1.6mm thickness PCB material, a single via can add 1.2nH of inductance and
0.5pF of capacitance, depending upon the via’s dimensions and PCB dielectric material, although
the effects can be minimized by ensuring that the inter-via spacing is between 1/10 - l/30
wavelengths.
Sometimes the knowledge of the physical properties of the PCB can be used to the advantage of
the design engineer. For example, an inductance derived from a PCB trace will offer much greater
repeatability than a commercially available component.
VCO or Crystal Filter
The external VCO crystal of the CC2500 consists of series external traces (that have inductance)
and parallel capacitors across a differential input. Hence the PCB layout should endeavor to
respect the symmetry of this port. This PCB trace line characteristics change with height and can
cause changes to the oscillator’s frequency of operation. It’s important when minimizing the
radiation from the VCO circuit to keep the traces as short as possible and to re-check the
frequency of oscillation as the traces’ impedances can change the oscillator’s frequency; see
Figure 7.
For a 2-sided layout, maintaining a symmetrical PCB layout with respect to the VCO oscillator is
recommended. Note that in the design illustrated here, the traces are kept as short as possible,
and the entire circuit is enclosed within a ground or guard band. This ground trace both minimizes
radiation from the VCO as well as prevents noise from being injected directly into the VCO circuit
traces.
VCO oscillator
Figure 7, VCO crystal
To minimize the possibility of inductive cross coupling between the VCO and the transmitter and
receiver blocks, it is recommended that the VCO inductor be placed orthogonal to the balun
inductors.
Current Loops and Decoupling
Minimize current loops on PCB layouts by placing decoupling capacitors close to the part’s power
pin with minimum return paths to ground. In order to compensate for the added inductance of the
vias, additional parallel vias help lower the decoupling caps’ ground returns by paralleling the
inductance of the vias. In the circles of Figure 8, below, the decoupling caps are placed in close
proximity to the power pins. Note these caps are C3, C4, C6 and C7 seen in Figure 8. Try to
avoid capacitive coupling by ensuring that each circuit block or power port has its own decoupling
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Application Note AN068
capacitor of value suggested in the data sheet. As a rule of thumb, components should not share
vias. An additional 40 pF was added to this design to lower the analog spurs seen in the
continuous output power spectrum after the stacking height was changed.
VDD
FB1
P600R
C16
1 2
1uF
C3
C1
220pF
C6
220pF
C2
.1uF
C5
.1uF
1
2
3
6
7
17
20
SCLK
SO(GDO1)
GDO2
GDO0
CSn
RBIAS
SI
DVDD 4
5
DCOUPL
DGUARD 18
AVDD 9
AVDD 11
GND(PAD)
GND
GND
0
.1uF
C4
.1uF
C7
220pF
AVDD 14
AVDD 15
U1
RF_P
RF_N
XOSC_Q1
XOSC_Q2
12
13
8
10
CC2500
16
19
Placement of Decoupling Caps
Figure 8,
Transmit & Receive Optimization
The Transmit & Receive matching serves two functions; first, to perform a differential to singleended
conversion, and secondly to attenuate the level of harmonic products generated due to
circuit non-linearities. The easiest method to design the transmitter and receiver matching network
is to use the single-ended source path to derive a matched impedance network. This network is
illustrated below with the dc blocking cap, balun, and pi-matching filter calculated based upon singleended
system; see Figure 9.
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Application Note AN068
Figure 9, Single-ended model
Once L1 and C1 are found, then the PI-Network for the filter is designed to match the impedance
connected to the SMA, which is generally 50Ω. Once this is done, the values of the balun are
divided by two and become the conjugate to create 180 degree phase to make a balun. This is
shown below in Figure 10.
Figure 10, Differential Balun and Pi Filter
The matching network is comprised of the following stages:
• L1, C1: Together with PCB traces and device (packaging) parasitic components forms a resonant
load at the required output frequency.
• The L/2, 2xC's: Are the values needed for a differential balun.
• C provides a DC blocking from the RF Output stage.
• C2, C3, L2: Form a PI low-pass harmonic filter.
Note that these values were optimized on the reference design PCB and will probably not be the
correct values for a different PCB stacking or layout.
Sample Design for Compact Design
First all the impedances are normalized to 50 ohms. Use 2.45GHz, the center of the frequencies for
the device, as the operating frequency. A simple design procedure can be followed in the outlined
below:
1. Starting at the antenna port (which is assumed to be our 50 ohm reference point) design the pisection
harmonic trap and plot on the Smith Chart, as represented in Figure 11, below.
2. Add the series DC block and impedance transformation provided by the series inductor so that the
impedance is transformed from nominally 50 ohms and so that it lies on the same arc as the required
load impedance, as illustrated in Figure 11.
3. Finally, design the tuned load to present the optimum impedance to the transmitter stage. From
Figure 15, it can be observed that the overall Q of the matching network is less than 1.0.
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Application Note AN068
4. Point 5 and 6 shows adding the balun values.
5. The network can be implemented on stage by stage PCB2, enabling the engineer to check the
theoretical results against those of the practical implementation.
Below is a Smith Chart plot of just the component values. As can be seen, this by itself does not
provide the correct load for the CC2500 device. Adding the component values for the traces
alters the impedance matching network to provide the correct match from the output of the device
to the 50Ω load.
Figure 11, Smith Chart Plot of Components Only
DP-Nr. 1(50.0 + j0.0)Ohm Q = 0.0 2.450 GHz
DP-Nr. 2(21.4 - j24.7)Ohm Q = 1.2 2.450 GHz
DP-Nr. 3(21.4 - j5.7)Ohm Q = 0.3 2.450 GHz
DP-Nr. 4(12.7 - j11.4)Ohm Q = 0.9 2.450 GHz
DP-Nr. 5(12.7 + j26.3)Ohm Q = 2.1 2.450 GHz
DP-Nr. 6(67.1 + j0.0)Ohm Q = 0.0 2.450 GHz
Figure 12, Component Schematics only
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Application Note AN068
This shows the source to be 1.34+j0 shown in Figure 12 and doesn’t agree with the original
source impedance of 1.6+j1.48. Therefore to plot the correct match, include the traces’
inductances to achieve a lower VSWR number.
Balun / Matching Network Measurements
As we design the balun and matching network it is important to match the antenna’s feed line. It
is a good idea to check that we accomplished this by observing how close to 50+j0 the system
looks at the SMA while the chip is set to receive mode. Connecting a Vector Network Analyzer
into S11 mode and calibrated for open, short and 50 ohm at connection of the SMA allows one to
measure the input impedance and return loss. Place the CC2500 device in receive mode and
lower the VNA power output to -30 or -40dB so not to saturate the LNA. From the Smith Chart,
Figure 13 & 14 the impedance is shown as viewed from the antenna.
The target value is 50 +j0, creating a perfect match to the antenna with 50Ω at 2.45GHz is shown
in Figure 14. The original 30mil (0.8mm) board showed an impedance of 41.21+j11 and is well
within VSWR circle of 2. But since this is lower in value the power transmitted to the antenna is
slightly low due to the reflected voltage from the mismatch.
Figure 13, 031 mill stacking, Impedance of EVM at Antenna SMA
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Application Note AN068
Figure 14, 059 stacking height Impedance measured at SMA
The closer the match is to 50+j0, the better the efficiency between the SMA and the selected
antenna.
Sometimes the quickest method to use is a good 3-D PCB simulator. Below shows the schematic
and elements using Advanced Design System from Agilent to perform the simulations. This
method provides simulation files and the ability to check the final design’s S21 as well as S11.
Metal-1
Dielectric-1
Metal-2
Metal-i : T[i], COND[i], TYPE[i]
Dielectric-i : ER[i], H[i], TAND[i]
MLSUBSTRATE2
Subst1
Er=4.7
H=59 mil
TanD=0.002
T[1]=1.4 mil
Cond[1]=4.1E7
T[2]=1.4 mil
Cond[2]=4.1E7
LayerType[1]=signal
LayerType[2]=ground
muRata
MURATAInclude
muRata
Disp
Temp
DisplayTemplate
disptemp1
"S_Params_Quad_dB_Smith"
LQG15
L1
Value="1.2[nH]"
S-PARAMETERS
S_Param
SP1
Start=1.0 GHz
Stop=10.0 GHz
Step=0.1 GHz
GRM15
C6
Value="1.8[pF]"
Port
P1
Num=1
ML1CTL_C
TL1
Subst="Subst1"
Length=38.2 mil
W=10.0 mil
GRM15
C8
Value="100[pF]"
ML1CTL_C
TL3
Subst="Subst1"
Length=35.5 mil
W=10.0 mil
ML1CTL_C
TL5
Subst="Subst1"
Length=35.5 mil
W=10.0 mil
GRM15
C4
Value="1[pF]"
MCURVE2
Curve1
Subst="Subst1"
W=30 mil
Angle=90
Radius=30 mil
Nmode=2
ML1CTL_C
TL6
Subst="Subst1"
Length=35.5 mil
W=10.0 mil
LQG15
L3
Value="1.2[nH]"
ML1CTL_C
TL8
Subst="Subst1"
Length=35.0 mil
W=10.0 mil
ML1CTL_C
TL7
Subst="Subst1"
Length=195 mil
W=55 mil
Port
P2
Num=2
GRM15
Port
P3
Num=3
ML1CTL_C
TL2
Subst="Subst1"
Length=38.2 mil
W=10.0 mil
GRM15
C2
Value="100[pF]"
ML1CTL_C
TL4
Subst="Subst1"
Length=35.5 mil
W=10.0 mil
GRM15
C9
Value="1[pF]"
LQG15
L2
Value="1.2[nH]"
MCURVE2
Curve2
Subst="Subst1"
W=30 mil
Angle=90
Radius=30 mil
Nmode=2
C5
Value="1.5[pF]"
Figure 15, Schematic of PCB model
The component values in this simulation were from Murata but equivalent values from Pansonic
and other vendors will work. The component values used in s-parameter simulation were
supplied by the component manufacturers. Selecting the correct types of components requires
careful considerations of the devices’ self-resonances and package parasitics, both of which will
change the performance.
Sensitivity Comparison
The receiver sensitivity is a measurement of the receiver’s input packet error rate. Since noise is
measured in dB or power the noise floor for the board should be at least -3dB or lower than the
input Noise Figure of the receiver. For 2-layer boards reducing the noise is accomplished by
adding ground planes on top and bottom of the board. The plot in Figure 18 and 19 show the
performance improvement over the original board with both the stacking and rules followed in this
discussion to improve the performance.
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Application Note AN068
062 Mil EVM CC2500
-82
-83
-84
250Kbytes / sec data rate
typical should be -89dBM @room temp. (3.0V) boards averaged -89.67
-85
Sensitivity (dB)
-86
-87
-88
-89
-90
-91
-92
-40 -20 0 20 40 60 80
Temperature deg C
1.8 Volts 3.6 volts Max 3.6 Min 1.8
Figure 16 Sensitivity Plot of 62mil (1.6mm) board
Note the variation of packet errors was reduced on this new board layout as shown in Figure
Figure 16 compared to Figure 17, 31mil (1mm board). Across temperature the 31mil (1 mm)
board had 4 dB variations in temperature and voltage while the 62mil (1.6mm) board shows 2.2
dB.
Sensitivity@2440 MHz
Average data
Temperature [°C]
-40 25 85
1.8 -90.3 -89.4 -87.1
VDD [V] 3 -88.5 -89.0 -86.3
3.6 -87.7 -88.2 -85.8
Minimum data Temperature [°C]
-40 25 85
1.8 -91.7 -90.9 -88.3
VDD [V] 3 -90.5 -90.3 -87.7
3.6 -89.9 -89.5 -87.5
Maximum data Temperature [°C]
-40 25 85
1.8 -89.7 -88.5 -86.5
VDD [V] 3 -87.7 -87.5 -84.1
3.6 -84.7 -86.7 -83.5
Standard deviation Temperature [°C]
-40 25 85
1.8 0.8 0.9 0.7
VDD [V] 3 1.2 1.1 1.5
3.6 2.4 1.1 1.5
Power [dBm]
-75.0
-77.0
-79.0
-81.0
-83.0
-85.0
-87.0
-89.0
-91.0
-93.0
-95.0
Sensitivity@2440 MHz
-40 25 85
Temperature [°C]
Figure 17, Sensitivity Plot of 31mil (1.0mm) PCB
Max data
Avg 1.8V
Avg 3V
Avg 3.6V
Min data
Power Output Comparison
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Application Note AN068
Plotting the output power Figure 18 as measured at the SMA (antenna port) was compared to the
31mil (1.0mm) PCB board. The power had a less variation over the total channels viewed.
Worst case deviation was .5 dB compared to the original which has closer to a 1dB variation.
Output Power vs. Freq (25 C, 3.0V
2.0
1.5
1.0
P o w e r ( d B m )
0.5
0.0
Min
Avg
Max
-0.5
-1.0
2 390
2 400
2 410
2 420
2 430
2 440
2450
2460
2470
2480
2490
Freq (MHz)
Figure 18, Output Power Plot 1.6mm PCB
Output Power vs Frequency (25°C, 3.0V, 5 samples)
2.0
1.5
P o w e r [ d B m ]
1.0
0.5
0.0
Min
Avg
Max
-0.5
-1.0
24 00
24 05
24 10
24 15
24 20
24 25
24 30
24 35
24 40
Freq [MHz]
24 4 5
24 50
24 55
24 60
24 65
24 70
24 75
24 80
Figure 19, Original Output Power Plot.
Spectrum of Board Noise Sources
Putting the channel into continuous transmit and looking at the spectrum of the signal and its
noise spurs is used to control harmonics and noises that are too high for standards or low
sensitivity readings. Placement of decoupling capacitors and the values determine how well the
noise spurs are controlled. Often it is best to use smaller package size capacitors like 0402 to
reach a lower noise floor. Below is a spectrum of the original EVM at 31 mils and the new board
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Application Note AN068
at 62 mils showed identical results. Because the layer spacing was increased, a 47 pf capacitor
was added to the digital lines to lower harmonics in the signal band. Of course a better
measurement would be phase noise density of the power spectrum. This plot was not included
but is often found in the device data sheet.
Marker 1 [T1] RBW 3 kHz RF Att 10 dB
Ref Lvl -14.82 dBm VBW 3 kHz
-20 dBm 2.43296593 GHz
1
SWT 70 s Unit dBm
-20
A
-30
-40
-50
1AP
-60
-70
-80
-90
-100
-110
-120
Center 2.432965932 GHz
Date: 6.JUL.2008 21:12:21
25 MHz/
Span 250 MHz
Figure 20, Spectrum of CC2500
Summary
The data from the 62mil (1.6mm) EVM showed equivalent performance to the original 31mil
(0.8mm) EVM over all corners of operation temperature and voltage. Although a small sample of
parts (10 boards) were used to compare the results, the new board indicates a closer match and
the inclusion of the trace lengths in the balun/matching analysis improves the performance.
Controlling the number of vias used in the digital paths reduce harmonics that might create
current loops in the RF signal path.
The original board S11 matching was just inside a VSWR of 2. Improved matching (shown in the
impedance plots as the 2.45GHz point moving inside a smaller VSWR circle) resulted from
stacking height change and demonstrated improved performance. This was seen in the
sensitivity and power variation measurements.
Controlling trace placement, widths, and ground all influence EMI on the boards, noise currents,
and loop currents. As one might place components close together one should not place device
closer than 20 mils for good isolation or low RF leakage. Gerber files found at the TI web site
CC2500 product’s folder under CC2500_REFDES_062 provide the reference board layout for
copying or further review.
RF Layout Tips
1. Adapt trace widths for same characteristic impedance transmission of previous lines when changing the
stacking height of the FR4 PCB.
2. For a given stacking height the variation of permittivity only changes the impedance slightly
3. Whenever possible include a bottom (copper) side of the board to allow for a solid ground plane under
the RF circuitry
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Application Note AN068
4. Try to avoid using vias in the RF path and is they must be used take into account the added inductance
and capacitance.
5. Check the frequency of oscillation as the traces’ impedances can change the oscillator’s frequency - extra
capacitance can detune the crystal and this means need to be compensated by changing the load capacitors
accordingly.
6. VCO oscillators should be placed orthogonal to the balun inductors
7. Minimize current loops on PCB layouts by placing decoupling capacitors close to the part’s power pin
with minimum return paths to ground
8. Try to avoid capacitive coupling by ensuring that each circuit block or power port has its own decoupling
capacitor of value suggested in the data sheet
9. Avoid components returns through share ground vias.
10. Select discrete components whose s-parameter show adequate linearity in frequency of interest.
11. Keep trace lines short when possible, only use long lines as required for RF.
References
General references
[1] Presentation “PCB Resonance Significance and Avoidance”, Leland Swanson,
TI, July 12, 2005
[2] “Signal Integrity Simplified” by Dr. Eric Bogatin, IBN 0-13-066946-6.
Document History
Revision Date Description/Changes
1.0 Initial release.
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