Preliminary Ttcbi

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LHC Project Document No. LHC-BI-ES-XXXX.XX rev 0.0 Draft Page 16 of 18 register Content Value From Prom Address TTCrx Register name [5] after reset prom: add: Comments: 0Fine Delay 1 0 12 0 Default for test 1Fine Delay 2 0 0 1 not used 2Coarse Delay 0 0 2 not used Enable : CKD1, SerialB, 3Control 10010011 72 3 L1Accept, EventCount 8Single error count 0 9Single error count 0 10Double error count 0 11SEU error count 0 16 ID 0 0 4 Default TTC Address =0 Set master modeTCC add = 17MasterModeA, ID 0 0 5 0 MasterModeB, I2C_ID Set master mode I2C Add = 18 0 1 6 1 19Config 1 10 2 7 Default value 20Config 2 10000100 84 8 Default value 21Config 3 10100111 A7 9 Default value 22Status 11100000 24Bunch Counter Bits 0 25 “ 0 26Event Counter Bits 0 27 “ 0 28 “ 0 9. CONTROL SOFTWARE In order to use the TTCbi board in the LHC BI Front Ends, a dedicated driver, the corresponding library as well as a local and remote test programs will be developed by the SL-BI software section. The resulting interface will allow the user to: – configure its TTCbi (mainly select the bytes redirected to P2 and CPU interrupts). – read asynchronously the generic information available like the beam intensity, energy, the GPS time or the internal error registers… – subscribe to interruptions generated by the TTCbi card. This software will be made available for every operational platforms (CPU and Real Time OS) used by SL-BI. Today, this is limited to PowerPC CPUs running LynxOS3.1. A first version of this software limited to the functionalities available in the SPS BST Master will be available around the 2002 start-up. It will be documented in a dedicated technical specification and available during Q2 2002 in the SL-BI software section EDMS repository for LHC software [http://edmsoraweb.cern.ch:8001/cedar/navigation.tree?cookie=872506&p_top_id=1 598559859&p_top_type=P].
10. REFERENCES [1] LHC Timing Requirements Gary BEETHAM SL/CO et al. http://lhc-proj-timwg.web.cern.ch/lhc-proj-timwg [2] Timing, Trigger and Control (TTC) Systems for LHC Detectors Bruce TAYLOR EP/CMD http://ttc.web.cern.ch/TTC/intro.html [3] LHC Machine Timing Distribution for the Experiments B.G. Taylor EP/CMD http://ttc.web.cern.ch/TTC/intro.html [4] PMC specification IEEE standard P1386.1 http://pcisig.com LHC Project Document No. LHC-BI-ES-XXXX.XX rev 0.0 Draft Page 17 of 18 [5] TTCrx Reference Manual: A Timing,Trigger and Control Receiver ASIC for LHC Detectors J.Christiansen EP/MIC et al. [6] TTC-VMEbus Interface (TTCvi) EP 680-1128-050-C P.Farthout, P.Gallno EP/ATE [7] THE LHC Machine TIMING SYSTEM FUNCTIONAL SPECIFICATION Gary BEETHAM SL/CO et al. [8] PLX PCI 9050-1 Data Book; Version 1.02; December 1999 : http://www.plxtech.com [9] PCF8584 I2C-bus controller; Product specification ; http://www.semiconductors.philips.com [10] JTAG / Boundary scan IEEE 1149.1 standard. [11] Very high speed integrated circuit Hardware Description Language. IEEE 1164 standard. [12] PCI Local Bus Specification Revision 2.2 December 18, 1998. [13] The I2C BUS SPECIFICATION Version 2.0 December 1998
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Preliminary Ttcbi

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