Preliminary Ttcbi

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LHC Project Document No. LHC-BI-ES-XXXX.XX rev 0.0 Draft 5E 5F 00 41 4Ch LSW Enable IRQ1 active low 60 61 00 20 52h MSW EEPROM Control Register:ready delay =32 clks 62 63 0C 00 50h LSW User 0,2,3= Out active low; User 1 =In 64 .. XX XX NOT USED Page 14 of 18 After initialisation, the PCI interface allows access to the non-multiplexed 32-bit local bus. Burst or continuous single cycle in Big Endian (no swapping) is used. The PCI Interrupt A can be requested using Local Interrupt 1 and 2 from XILINX FPGA. Direct slave access of 1 Kbytes in the Local Address Space 0 allows access to all registers and dual-ported RAM of Xilinx FPGA. Item R W Add Size Byte 3 Byte 2 Byte 1 Byte 0 Comments Control W 0 Byte xxxxxxx xxxxxxx xxxxxxx Control See details below Control & Status R 0 Word xxxxxxx xxxxxxx Status Control " Coarse Delay R/W 4 Word xxxxxxx xxxxxxx bit 11 …. 0 25 ns step delay Hardware Bytes Select R/W 8 Word xxxxxxx xxxxxxx Byte 1 Byte 0 0…255 ; 0…255 Hardware Bytes Output R C Word xxxxxxx xxxxxxx Byte 1 Byte 0 read back outputs IRQ Bytes Addr Select R/W 10 Word xxxxxxx xxxxxxx Byte 1 Byte 0 0…255 ; 0…255 IRQ Bytes Addr Mask R/W 14 Word xxxxxxx xxxxxxx Byte 1 Byte 0 00…FF ; 00...FF Single TTC Error count R/W 20 Word xxxxxxx xxxxxxx 16 bit counter Reset on write Double TTC Error count R/W 24 Word xxxxxxx xxxxxxx 16 bit counter Reset on write Ready TTC Error count R/W 28 Word xxxxxxx xxxxxxx 16 bit counter Reset on write Turn Clock Count R/W 30 LWord xxxxxxx 24 bit counter Reset on write Local Message : R/W 80 Word xxxxxxx xxxxxxx Sub Add Data Cmd 0 = 32 Commands R/W 84 Word xxxxxxx xxxxxxx Sub Add Data Cmd 1 R/W 88 Word xxxxxxx xxxxxxx Sub Add Data Cmd 2 .. …. …. xxxxxxx xxxxxxx …. … … R/W FC Word xxxxxxx xxxxxxx Sub Add Data Cmd 31 DP Ram Mess Input R 100 Lword Cmd 3 Cmd 2 Cmd 1 Cmd 0 CmdData @ SubAdd = 256 Commands R 101 Lword Cmd 7 Cmd 6 Cmd 5 Cmd 4 “ R 102 Lword Cmd 11 Cmd 10 Cmd 9 Cmd 8 “ … … … ….. …. …. …. “ R 1FC Lword Cmd255 Cmd254 Cmd253 Cmd252 “ Control Register: bit 0 Internal mode = 1 ; External mode = 0 ( Default); 1 = local 40MHz on bit 1 Sub mode : Single shot = 1; Repetitive = 0 ( Default) bit 2 DP Ram Write Control : Enable = 1; bit 3 Hardware Bytes Output Control : Enable = 1 bit 4 IRQ from Masks control : Enable = 1 bit 5 IRQ from Masks control : Clear Request = 1 bit 6 SPS = 1; LHC = 0 ( For diff. Bunch count ) bit 7 Spare Status Register: bit 0 TTC Input Ready = 1 ; 0 = No Input signal bit 1 1 = Local 40MHz present bit 2 1 = Local Turn Clock present bit 3 1 = TTC Serial B input signal present bit 4 1 = TTC Frame error bit 5 1 = Message record bit 6 1 = IRQ set from Masks bit 7 Spare
LHC Project Document No. LHC-BI-ES-XXXX.XX rev 0.0 Draft Page 15 of 18 Direct slave access in the Local Address Space 1 of 8 bytes allows accessing all the PCF8584 I2C bus controller registers. The PCF8584 [9] has 5 internal registers but occupied only two byte locations. Register selection between the control/status register S1 and the other registers depending on bits loaded in ESO, ES1 and ES2 of register S1. Item R/W ADD h Access Byte 0 Comments Data Reg R/W 00 Byte Data Register Depends on ES2, ES1, ES0 Control Reg S1 W 04 Byte Control See details below Status Reg S1 R 04 Byte Status " Control Register S1 : bit 0 Automatic Acknowledgement = 0 in master mode bit 1 Stop transmission = 1 bit 2 Start transmission = 1 bit 3 Enable Interrupt = 0 ( No irq ) bit 4 ES2 bit 5 ES1 bit 6 ES0 bit 7 Reset all status registers = 1 Status Register S1 : bit 0 BB = 1 : Bus Busy ( in use) bit 1 LAB = 1 : Loss Arbitration bit 2 AAS = 1: Addressed As Slave bit 3 LRB = 1 : Last Received Bit bit 4 BER = 1: Bus error detected bit 5 STS = 1 : stop receive detected bit 6 X = Not used bit 7 PIN = 0 when transmission is completed The default Interface Mode Control (8080 type) is used (separate Write & Read without dtack), along with master transmitter / receiver mode without interrupts. On reset all registers are set by default to the required values: Register S0’ = 0 : PCF8584 Own I2C address = 0; Register S2 = 0 : Serial Clock frequency = 90 KHz ; System clock frequency = 3 MHz. The I2C bus is used to read or write the TTCrx user accessible registers listed below. According to the I2C bus specification [13], the TTCrx device on the bus is addressed by a 7bit wide address. The TTCrx chip occupies two consecutive positions in the I2C address space. The I2C address is derived from the device base address register in the following way: I2C access register : Resulting I2C address : TTCrx Register Address pointer Device Base Address * 2 TTCrx Register Data Device Base Adress *2 + 1 On power on, all registers are initialised to a default value before ten specific registers are loaded with the contents of the optional XC1736 EPROM as defined below.
Page 1 and 2: CERN CH-1211 Geneva 23 Switzerland
Page 3 and 4: Table of Contents LHC Project Docum
Page 5 and 6: Global Trigger LHC Clock General TT
Page 7 and 8: 3.1 BST Message CONTENTS LHC Projec
Page 9 and 10: LHC Project Document No. LHC-BI-ES-
Page 11 and 12: LHC Project Document No. LHC-BI-ES-
Page 13: EEPROM Byte Initial VALUE Destinati
Page 17 and 18: 10. REFERENCES [1] LHC Timing Requi

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