Preliminary Ttcbi

19.07.2012 Views
LHC Project Document No. LHC-BI-ES-XXXX.XX rev 0.0 Draft 16 D3 M_SAddr(0) : LSB of Message subadress writted into dual ported RAM 17 D2 L_DoutStr : Data strobe from local message generator; Active H 18 D1 L_Mess_Data(0): LSB of local message 19 D0 LTC: Turn Clock correspondiing to the signal send to hardware connector 20 GND JTAG header J2: To be used for downloading the FPGA configuration using a JTAG [11] port. Strap settings: Pin1 : GND Pin4 : TCK Pin2 : TDI Pin5 : TDO Pin3 : TMS Pin6 : VCC 7. BOARD CONFIGURATION Page 12 of 18 • ST2 : TTCrx configuration mode. PROM = Configuration downloaded from XC1736 PROM on power-on or TTC reset. NO PROM = Default configuration or downloaded from I2C bus or TTC commands. • ST3 : To perform a direct access to XCV50 JTAG[10] port. Used only for debugging. ON = bypass XC18V01 PROM in JTAG [10] chain.(For test only) OFF = Setting for normal use. • ST4 : PCI 9050 interface access control. ON = Enable PCI bus access ( Normal mode) OFF = Disable PCI bus access ( For test only) • ST5, ST6, ST7: XCV50 configuration mode M1, M0, M2 (see XILINX specifications.) ON OFF OFF = Configuration downloaded from JTAG[10] port J2.(For test only) ON ON ON = Configuration downloaded from XC18V01 flash PROM. (Default) The configuration is first downloaded into the PROM using the JTAG[10] port, then transferred to the XCV50 on next power-on, or by setting the reprogram bit of global control register. • ST8 : 3.3V power supply source according to the PCI specification [12]. P3V3 = from PMC connector (if provided by mother board.) P3V3A = from on-board TPS767D325 regulator. 8. MEMORY MAP All PCI accesses are 16 or 32 bits, using the 33MHz PCI clock with 128 Mbytes/sec block transfer capability. The PCI interface is constructed using a low price PCI 9050 target interface from PLX. [8]. As for all PCI devices, the TTCbi has 256 bytes of configuration space. System software may, on reboot, scan the configuration space to determine the device identification and parameters. One of the most important parameters is the base address, which maps the device into the PCI address space. The TTCbi uses 4 blocks of address space defined in the configuration register as follow: Block 0 : PLX Local Configuration registers mapped into 128 bytes of memory address space. Block 1 : PLX Local Configuration registers mapped into 128 bytes of I/O address space. Block 2 : FPGA internal registers and memories mapped into 1K bytes of memory address space. Block 3 : I2C interface registers mapped into 8 bytes of I/O address space. 8.1 REGISTERS On power ON, the PCI 9050 registers are initialised using a serial EEPROM type National NM93CS46 and can be accessed in block 0 or 1.

EEPROM Byte Initial VALUE Destination Registre Description LHC Project Document No. LHC-BI-ES-XXXX.XX rev 0.0 Draft 00 01 90 50 PCI 02h Device ID. 9050 02 03 10 B5 00h Vendor ID. 10B5 04 05 06 80 0Ah Class Code. 06 07 00 00 08h Class code revision (is not loadable) 08 09 90 50 2Eh Subsystem ID. 9050 0A 0B 10 B5 2Ch Subsystem Vendor ID. 10B5 0C 0D 00 00 3Eh Maximum Latency and Minimum Grant (not loadable) 0E 0F 01 01 3Ch Interrupt Pin (Interrupt Line is not loadable)=01xx 10 11 0F FF LOCAL 02h MSW of Range for PCI to Local Address Space 0 12 13 FC 00 00h LSW = 1k Bytes Mem SPACE FOR FPGA 14 15 0F FF 06h MSW of Range for PCI to Local Address Space 1 16 17 FF F9 04h LSW = 8 Bytes IN I/O SPACE FOR I2C 18 19 00 00 0Ah MSW of Range for PCI to Local Address Space 2 1A 1B 00 00 08h LSW NOT USED 1C 1D 00 00 0Eh MSW Range for PCI to Local Address Space 3 1E 1F 00 00 0Ch LSW NOT USED 20 21 00 00 12h MSWRange for PCI to Local Expansion ROM (64 KB). 22 23 00 00 10h LSW NOT USED 24 25 00 00 16h MSW Local B.A.(Remap) for PCI to Local Add Space 0 26 27 00 01 14h LSW LOCAL Base Addr = 0 ; + 1 = direct slave 28 29 00 00 1Ah MSW Local B.A.(Remap) for PCI to Local Add Space 1 2A 2B 04 01 18h LSW LOCAL Base Addr = 400h ; + 1 = direct slave 2C 2D 00 00 1Eh MSW Local B.A.(Remap) for PCI to Local Add Space 2 2E 2F 00 00 1Ch LSW NOT USED 30 31 00 00 22h MSW Local B.a.(Remap) for PCI to Local Add Space 3 32 33 00 00 20h LSW NOT USED 34 35 00 00 26h MSW of Local B.A.(Remap) for PCI to Local Exp. ROM. 36 37 00 00 24h LSW NOT USED 38 39 54 91 2Ah MSW of Bus Region Descriptors for Local Add Space 0 3A 3B 28 80 28h LSW32 b;No Burst;No wait 3C 3D FC 27 2Eh MSW of Bus Region Descriptors for Local Add Space 1 3E 3F 7B 80 2Ch LSW :08 b;NoBurst;+wait=10,1,3,10,0;+delay=1,1,1 40 41 00 00 32h MSW of Bus Region Descriptors for Local Add Space 2 42 43 00 00 30h LSW NOT USED 44 45 00 00 36h MSW Bus Region Descriptors for Local Add Space 3 46 47 00 00 34h LSW NOT USED 48 49 00 00 3Ah MSW Bus Region Descriptors for Expansion Space 4A 4B 00 00 38h LSW NOT USED 4C 4D 00 00 3Eh MSW of Chip Select (CS 0) Base and Range Register. 4E 4F 02 01 3Ch LSW : Enable 1 KB at addr 0 for XILINX pga. 50 51 00 00 42h MSW of Chip Select (CS1 ) Base and Range Register. 52 53 04 09 40h LSW : Enable 8 By at addr 400h for I2C interface. 54 55 00 00 46h MSW of Chip Select (CS2 ) Base and Range Register. 56 57 00 00 44h LSW NOT USED 58 59 00 00 4Ah MSW of Chip Select (CS3 )Base and Range Register. 5A 5B 00 00 48h LSW NOT USED 5C 5D 00 00 4Eh MSW of Interrupt Control/Status Register. Page 13 of 18

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