Preliminary Ttcbi

LHC Project Document No.
LHC-BI-ES-XXXX.XX rev 0.0 Draft
16 D3 M_SAddr(0) : LSB of Message subadress writted into dual ported RAM
17 D2 L_DoutStr : Data strobe from local message generator; Active H
18 D1 L_Mess_Data(0): LSB of local message
19 D0 LTC: Turn Clock correspondiing to the signal send to hardware connector
20 GND
JTAG header J2: To be used for downloading the FPGA configuration using a JTAG [11] port.
Strap settings:
Pin1 : GND Pin4 : TCK
Pin2 : TDI Pin5 : TDO
Pin3 : TMS Pin6 : VCC
7. BOARD CONFIGURATION
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• ST2 : TTCrx configuration mode.
PROM = Configuration downloaded from XC1736 PROM on power-on or TTC reset.
NO PROM = Default configuration or downloaded from I2C bus or TTC commands.
• ST3 : To perform a direct access to XCV50 JTAG[10] port. Used only for debugging.
ON = bypass XC18V01 PROM in JTAG [10] chain.(For test only)
OFF = Setting for normal use.
• ST4 : PCI 9050 interface access control.
ON = Enable PCI bus access ( Normal mode)
OFF = Disable PCI bus access ( For test only)
• ST5, ST6, ST7: XCV50 configuration mode M1, M0, M2 (see XILINX specifications.)
ON OFF OFF = Configuration downloaded from JTAG[10] port J2.(For test only)
ON ON ON = Configuration downloaded from XC18V01 flash PROM. (Default)
The configuration is first downloaded into the PROM using the JTAG[10] port, then transferred to
the XCV50 on next power-on, or by setting the reprogram bit of global control register.
• ST8 : 3.3V power supply source according to the PCI specification [12].
P3V3 = from PMC connector (if provided by mother board.)
P3V3A = from on-board TPS767D325 regulator.
8. MEMORY MAP
All PCI accesses are 16 or 32 bits, using the 33MHz PCI clock with 128 Mbytes/sec block transfer
capability. The PCI interface is constructed using a low price PCI 9050 target interface from PLX. [8]. As
for all PCI devices, the TTCbi has 256 bytes of configuration space. System software may, on reboot,
scan the configuration space to determine the device identification and parameters. One of the most
important parameters is the base address, which maps the device into the PCI address space.
The TTCbi uses 4 blocks of address space defined in the configuration register as follow:
Block 0 : PLX Local Configuration registers mapped into 128 bytes of memory address space.
Block 1 : PLX Local Configuration registers mapped into 128 bytes of I/O address space.
Block 2 : FPGA internal registers and memories mapped into 1K bytes of memory address space.
Block 3 : I2C interface registers mapped into 8 bytes of I/O address space.
8.1 REGISTERS
On power ON, the PCI 9050 registers are initialised using a serial EEPROM type National
NM93CS46 and can be accessed in block 0 or 1.