Preliminary Ttcbi
Preliminary Ttcbi Preliminary Ttcbi
5.2 OVERALL FEATURES LHC Project Document No. LHC-BI-ES-XXXX.XX rev 0.0 Draft Page 10 of 18 • PMC slave card conforming to the IEEE P1386.1 standard. • Provides Beam Synchronous Timing for both the LHC and SPS accelerators. • Supplies the 40.08 MHz Bunch Clock, which remains synchronous with the bunch structure. • Supplies the Local Turn Clock, corresponding to the orbit frequency. Locked either at 1/924 of the bunch frequency for SPS or 1/3564 of the bunch frequency for LHC. • Local delays provide Local Clocks with the appropriate phase relative to the beam structure, taking into account the difference between particle time-of-flight and signal propagation. • The overall jitter of the received clocks anywhere around the rings is less than 1ns rms. • A BST message consists of 32 BST commands within the 88.9 µs of an LHC period or up to 8 BST commands within the 23.1 µs of an SPS period. • A BST command contains 2 bytes: a sub address or identifier, and its associated data byte. • Two predefined Data Bytes among the 32 sub-addresses can be routed to a hardware connector. • All the received commands are stored in a dual-ported RAM accessible by the local controller. • According to the PCI local bus specification, the TTCbi uses 256 bytes of configuration space. • All control registers and dual-ported RAM are mapped into the PCI memory or I/O spaces. • A PCI interrupt request can be generated on reception of a specific message or on error. • A local clock signal generator and up to 32 byte BST command message generator allows the TTCbi module to run in stand-alone mode for test purposes. • Optical Input, main timing signal outputs and indicator leds are available on the front panel. • All output signals are available on the 64 pin PMC I/O to be routed to the 64 pin I/O of the VME P2. • A PMC Connector supplies the following standard power supply from the VME motherboard:+ 5 V Max 1A ; + 3.3 V Max 1A ; + 12V and - 12v (not used ). 6. EXTERNAL SIGNALS Front Panel: The only required connection is TTC IN, all other signals and LEDs are for test purposes. Item: Description: TTC IN TTC Optical signal input : ST-PC connector on HFBR-2316T Receiver. Optical input power : operating range -22 dBm .... -18 dBm. CH B Serial Channel B, buffered output from TTCrx : Lemo 00 connector ; TTL level / 1 MΩ . LED is ON when CH B =1. LTC Local delayed Turn Clock, buffered output: Lemo 00 connector; 25ns. pulse / 2V / 50Ω From TTCrx L1 trigger in external mode or local generator in internal mode. LED is ON when LTC is present. 40M Local 40 MHz Clock, buffered output: Lemo 00 connector ; square pulse / 2V. / 50 Ω . From TTCrx CKD1 in external mode or local generator in internal mode. LED is ON when 40M is present. ACCESS LED is ON when any registers are accessed from the PCI bus. MESS IN LED is ON when a message is received from TTCrx or local generator. INTERNAL LED is ON when internal mode is set in the global control register. TTC RDY LED is ON when TTCrx ready status = 1. RESET LED is ON when a local reset from PLX is present.
LHC Project Document No. LHC-BI-ES-XXXX.XX rev 0.0 Draft Hardware connector: Signals are connected to the 32 pin PMC J4 to be routed to the VME P2. J4 Pin: P2 Pin: Signal description: 33 C17 Local 40 MHz Clock buffered output : square pulse LVDS + 34 A17 " " LVDS - 35 C18 Local 40 MHz Clock, buffered output : square pulse TTL 36 A18 GND 37 C19 Local delayed Turn Clock, buffered output: 25 ns pulse LVDS + 38 A19 " " LVDS - 39 C20 Local delayed Turn Clock, buffered output: 25 ns pulse TTL 40 A20 GND 41 C21 Spare 42 A21 Spare 43 C22 Spare 44 A22 Spare 45 C23 Hardware Byte 0 bit 0, output TTL . Valide on 40 MHz rising edge. 46 A23 " bit 1, " " 47 C24 " bit 2, " " 48 A24 " bit 3, " " 49 C25 " bit 4, " " 50 A25 " bit 5, " " 51 C26 " bit 6, " " 52 A26 " bit 7, " " 53 C27 Hardware Byte 0 strobe, output TTL . Valide on 40 MHz rising edge. 54 A27 GND 55 C28 Hardware Byte 1 bit 0, output TTL . Valide on 40 MHz rising edge. 56 A28 " bit 1, " " 57 C29 " bit 2, " " 58 A29 " bit 3, " " 59 C30 " bit 4, " " 60 A30 " bit 5, " " 61 C31 " bit 6, " " 62 A31 " bit 7, " " 63 C32 Hardware Byte 1 strobe, output TTL MHz Valide on 40 rising edge. 64 A32 GND Page 11 of 18 Test header J1: To be used for test and debugging purposes. Will fit the HP1600 Logic State Analyser, for which a number of acquisition setups already exist. The 16 signals and the clock are routed from the XILINX chip output port and can be selected from amongst all internal signals according to the user request (see example below). Pin POD Signal Description 3 CLK CK40M : Clock correspondiing to the signal send to hardware connector 4 D15 L_CS0 : Local chip select 0 from PCI9050: Active L 5 D14 Data_OUT(0) : LSB of local data bus output 6 D13 Turn_Count_Reg(0) : LSB of local turn counter register 7 D12 T_BCNT(0) : LSB of Bunch count number from TTCrx 8 D11 T_EVCNTR : Event counter reset from TTCrx ; Active H 9 D10 T_EVCNTL : Event counter strobe LSB from TTCrx ; Active H 10 D9 T_EVCNTH : Event counter strobe MSB from TTCrx ; Active H 11 D8 L_WRITE : Local Write from PCI9050 ; Active L 12 D7 L_READ: Local Read from PCI9050 ; Active L 13 D6 Mess_Out_En : Enable hardware mess out active H 14 D5 M_DStr : Message Data strobe into dual ported RAM; Active H 15 D4 M_Data(0) : LSB of Message data writted into dual ported RAM
- Page 1 and 2: CERN CH-1211 Geneva 23 Switzerland
- Page 3 and 4: Table of Contents LHC Project Docum
- Page 5 and 6: Global Trigger LHC Clock General TT
- Page 7 and 8: 3.1 BST Message CONTENTS LHC Projec
- Page 9: LHC Project Document No. LHC-BI-ES-
- Page 13 and 14: EEPROM Byte Initial VALUE Destinati
- Page 15 and 16: LHC Project Document No. LHC-BI-ES-
- Page 17 and 18: 10. REFERENCES [1] LHC Timing Requi
LHC Project Document No.<br />
LHC-BI-ES-XXXX.XX rev 0.0 Draft<br />
Hardware connector: Signals are connected to the 32 pin PMC J4 to be routed to the VME P2.<br />
J4 Pin: P2 Pin: Signal description:<br />
33 C17 Local 40 MHz Clock buffered output : square pulse LVDS +<br />
34 A17 " " LVDS -<br />
35 C18 Local 40 MHz Clock, buffered output : square pulse TTL<br />
36 A18 GND<br />
37 C19 Local delayed Turn Clock, buffered output: 25 ns pulse LVDS +<br />
38 A19 " " LVDS -<br />
39 C20 Local delayed Turn Clock, buffered output: 25 ns pulse TTL<br />
40 A20 GND<br />
41 C21 Spare<br />
42 A21 Spare<br />
43 C22 Spare<br />
44 A22 Spare<br />
45 C23 Hardware Byte 0 bit 0, output TTL . Valide on 40 MHz rising edge.<br />
46 A23 " bit 1, " "<br />
47 C24 " bit 2, " "<br />
48 A24 " bit 3, " "<br />
49 C25 " bit 4, " "<br />
50 A25 " bit 5, " "<br />
51 C26 " bit 6, " "<br />
52 A26 " bit 7, " "<br />
53 C27 Hardware Byte 0 strobe, output TTL . Valide on 40 MHz rising edge.<br />
54 A27 GND<br />
55 C28 Hardware Byte 1 bit 0, output TTL . Valide on 40 MHz rising edge.<br />
56 A28 " bit 1, " "<br />
57 C29 " bit 2, " "<br />
58 A29 " bit 3, " "<br />
59 C30 " bit 4, " "<br />
60 A30 " bit 5, " "<br />
61 C31 " bit 6, " "<br />
62 A31 " bit 7, " "<br />
63 C32 Hardware Byte 1 strobe, output TTL MHz Valide on 40 rising edge.<br />
64 A32 GND<br />
Page 11 of 18<br />
Test header J1: To be used for test and debugging purposes. Will fit the HP1600 Logic State<br />
Analyser, for which a number of acquisition setups already exist. The 16 signals and the clock are<br />
routed from the XILINX chip output port and can be selected from amongst all internal signals<br />
according to the user request (see example below).<br />
Pin POD Signal Description<br />
3 CLK CK40M : Clock correspondiing to the signal send to hardware connector<br />
4 D15 L_CS0 : Local chip select 0 from PCI9050: Active L<br />
5 D14 Data_OUT(0) : LSB of local data bus output<br />
6 D13 Turn_Count_Reg(0) : LSB of local turn counter register<br />
7 D12 T_BCNT(0) : LSB of Bunch count number from TTCrx<br />
8 D11 T_EVCNTR : Event counter reset from TTCrx ; Active H<br />
9 D10 T_EVCNTL : Event counter strobe LSB from TTCrx ; Active H<br />
10 D9 T_EVCNTH : Event counter strobe MSB from TTCrx ; Active H<br />
11 D8 L_WRITE : Local Write from PCI9050 ; Active L<br />
12 D7 L_READ: Local Read from PCI9050 ; Active L<br />
13 D6 Mess_Out_En : Enable hardware mess out active H<br />
14 D5 M_DStr : Message Data strobe into dual ported RAM; Active H<br />
15 D4 M_Data(0) : LSB of Message data writted into dual ported RAM
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