Preliminary Ttcbi

CERN 

CH-1211 Geneva 23 

Switzerland 

the 

Large 

Hadron 

Collider 

project 

LHC Project Document No. 

LHC-BI-ES-XXXX.XX rev 0.0 Draft 

CERN Div./Group or Supplier/Contractor Document No. 

SL/BI 

EDMS Document No. 

- 

Preliminary 

ENGINEERING SPECIFICATIONS 

TTCbi 

Date: 2001-11-08 

A TIMING, TRIGGER AND CONTROL INTERFACE 

FOR THE BEAM SYNCHRONOUS TIMING SYSTEM. 

Abstract 

Beam Synchronous Timing (BST) is required for beam instrumentation in the LHC accelerator chain. 

The Timing, Trigger and Control (TTC) system, designed for LHC detectors, provides a way of distributing the 

40MHz bunch clock and Orbit turn clock from the Prevessin Control Room (PCR) to the LHC experiment areas 

and to beam instrumentation around the ring and in the transfer lines. In addition we can profit from the TTC's 

ability to transmit data by inserting a BST message which can be broadcasted to all instrumentation crates 

throughout the TTC distribution network. The TTC interface for beam instrumentation (TTCbi) acts as an 

interface between the TTC distribution network and its receiving end users. The TTCbi is designed to recover 

the 2 distributed clocks, decode and store all BST messages and make them available to the front-end 

electronics controllers. The TTCbi is a PCI Mezzanine Card (PMC). This document is intended to provide a 

functional and physical description of the TTCbi for the end user. 

Prepared by : 

Jean-Jaques SAVIOZ 

[SL/CERN] 

Jean.Jaques.Savioz@cern.ch 

Checked by : 

Rhodri Jones [SL/CERN] 

Jean-Jacques Gras [SL/CERN]

History of Changes 



Rev. No. Date Pages Description of Changes 

0.0 10/12/2001 17 Creation 

Page 2 of 18

Table of Contents 



Page 3 of 18 

1. INTRODUCTION.............................................................................. 4 

2. TTC SYSTEM OVERVIEW .................................................................. 4 

2.1 TTC FRAME FORMAT..................................................................... 4 

3. BST SYSTEM OVERVIEW .................................................................. 6 

3.1 BST MESSAGE CONTENTS ............................................................ 7 

4. TTCBI OVERVIEW ........................................................................... 7 

5. FUNCTIONAL DESCRIPTION ............................................................. 8 

5.1 ARCHITECHTURE ......................................................................... 8 

5.2 OVERALL FEATURES....................................................................10 

6. EXTERNAL SIGNALS .......................................................................10 

7. BOARD CONFIGURATION ................................................................12 

8. MEMORY MAP ................................................................................12 

8.1 REGISTERS................................................................................12 

9. CONTROL SOFTWARE.....................................................................16 

10. REFERENCES.................................................................................17 

11. PICTURES .....................................................................................18

1. INTRODUCTION 



Page 4 of 18 

Beam Synchronous Timing (BST) is required for beam instrumentation in the LHC [1]. The Timing, 

Trigger and Control (TTC) system [2], designed for LHC detectors, provides a way of distributing the 40MHz 

bunch clock and Orbit turn clock from the Prevessin Control Room (PCR) to the LHC experiment areas and 

to beam instrumentation around the ring and in the transfer lines [3]. In addition we can profit from the TTC's 

ability to transmit data by inserting a BST message which can be broadcasted to all instrumentation crates 

throughout the TTC distribution network. The TTC interface for beam instrumentation (TTCbi) acts as an 

interface between the TTC distribution network and its receiving end users. The TTCbi is designed to recover 

the 2 distributed clocks, decode and store all BST messages and make them available to the front-end 

electronics controllers. The TTCbi is a PCI Mezzanine Card (PMC) [4] to be plugged onto a motherboard. 

This document document is intended to provide a functional description of the TTCbi for the end user. 

2. TTC SYSTEM OVERVIEW 

The Timing, Trigger and Control (TTC) system for LHC detectors has been specified and a complete 

description of the system and its functionality can be found in reference [2]. However, a brief overview of the 

TTC system features that are relevant for the understanding and utilisation of the TTCbi is given here. 

The TTC system provides the distribution of all signals necessary to synchronise the detectors: clock, trigger, 

and arbitrary control data, which are all distributed on a single optical fibre. The distribution is synchronous to 

the LHC bunch structure. Figure 2 illustrates the basic architecture of the TTC system. At the top of the TTC 

tree structure, two communication channels are Time Division Multiplexed (TDM), BiPhase Mark (BPM) 

encoded and transmitted over a passive optical fibre distribution network using a single laser source. One of 

the TDM channels (channel A) is exclusively dedicated to broadcast a global trigger. In our case, this feature 

is used to send the orbit turn clock by setting this bit high every time the beam completes a revolution of the 

machine. Channel B is used to broadcast data to all or specific system destinations. Data in channel B can 

be of two types: broadcast commands or individually addressed commands/data. Broadcast commands will 

be used to distribute the BST messages to all TTC destinations in the system. The TTC system is also used 

to distribute the LHC 40.08 MHz bunch-crossing reference clock signal. This signal is not explicitly 

transmitted over the network and has to be recovered from the incoming frame at each TTC system 

destination. 

The CERN Microelectronics Group has developed a TTC receiver ASIC (TTCrx) [5] which delivers the TTC 

signals to the front-end controllers. The TTCrx can deliver the full range of decoded and deskewed signals, 

including all received synchronous commands. The commands/data are implemented in the system to 

transmit user-defined data and commands over the network. These commands have two distinct modes of 

operation. In the first mode, they are aimed at the TTCrx themselves and their user-defined content can be 

used to control the receiver chip’s operation. In the second mode, the data is intended for the external 

electronics. In this case, both the data and sub-address contents of the received commands are externally 

available. 

2.1 TTC frame format 

Both the broadcast and the individually addressed commands are transmitted over the TTC network 

using a frame format that has been specified in reference [2] and which is schematically represented in 

Figure 3. The frame structure contains several fields to control the transmission, and includes a field in which 

several redundant bits are inserted for error detection and correction. The coding scheme used is a standard 

Hamming code with the capability of double error detection and single bit error correction. The error 

correction coding covers the 8-bit data word in the case of a short frame and the 32-bit data in the case of a 

long frame. A broadcast of a long frame can be performed by setting the TTCrx address equal to zero. The 

address space selection bit (E) instructs the addressed TTC receiver either to execute an internal operation 

or to make the received command/data externally available. Using this scheme it is possible to address up to 

256 internal and external sub-addresses. 

Each frame is identified by a header bit (FMT) that indicates its type. Start (logical “0”) and stop (logical “1”) 

bits are always included at the beginning and end of the frame transmission to facilitate correct 

synchronisation.

Global Trigger 

LHC Clock 

General TTC frame: 

1 

0 

ENCODER 

MULTIPLEXER 

MODULATOR/LASER 

1:32 TREE COUPLER 

REPEATER 

TTCrx 

Figure 2 : TTC distribution network 



Global single-mode fibres links 

Local multi-mode fibres links 

Broadcast Commands 

Addressed Commands 

- 40.08MHz clock 

- Global trigger 

- Bunch counter reset 

- Bunch crossing number 

- Event counter reset 

- Event number 

- Broadcast commands 

- Subaddress 

- Addressed commands 

IDLE START FMT COMMANDS/DATA CHCK STOP 

Short format Broadcast Commands/Data: 

0 0 8b CMD/DATA 5b CHCK 1 

Long format Broadcast or Individually-Addressed Commands/Data: 

0 1 14b TTCrx ADDR E 8b SUBADDR 8b DATA 7b CHCK 1 

Figure 3 : TTC Data Transmission frame 

Page 5 of 18

ORBIT 

TURN CLOCK 

CPU 

IRQ 

RESPONSE 

MESSAGE 

ASSEMBLER 

PROCESS 

WRITE 

TO FIFO 

FIFO OUT 

TRIGGER 

FIFO 

3. BST SYSTEM OVERVIEW 



Page 6 of 18 

The beam synchronous timing system for LHC beam instrumentation serves to synchronise 

acquisitions in areas that are very distant geographically, and is also used to convey signals, 

parameters and commands simultaneously to all instruments around the machine. All necessary 

real-time information is regrouped and transmitted in a so-called BST message. 

The complete BST system consists of: a BST Master, used to broadcast the synchronisation 

signals and the BST messages; the TTC system, used to encode and transmit the signals; a 

receiver interface, the TTCbi, installed in each beam instrumentation controller and which is the 

subject of this specification. 

A real-time process called the BST message assembler collects all the data and commands to be 

transmitted via the TTC system on a given turn. These data and commands are then assembled 

into a message of a predefined number of bytes. At each orbit turn clock period, the BST Master 

transmits the message for the current turn over channel B of the TTC system. 

The BST Master is based on a standard VME crate, including a fast processor, several network 

interfaces and a specific TTC module known as the TTCvi [6]. This module acts as the interface 

between the BST message assembler and the TTC system, and delivers the necessary A and B 

channel signals to the TTC encoder and transmitter. The BST message is alternately stored in one 

of the two FIFOs present on the TTCvi, and sent out with a possible phase adjustment on each 

Orbit Turn Clock. Figure 4 illustrates the basic architecture and transmission sequence of the BST 

Master 

In total, three operational BST systems are required, one for each of the LHC rings and another for 

the SPS ring and its transfer lines. Separate systems are needed since the revolution frequencies 

(and hence the bunch clock and turn clock) of all three are or can be different. 

Universal time 

Orbit Turn Clock 

Machine 

Events 

Beam 

Parameters 

Real-time 

commands 

Hardware 

triggers 

Phase adjustment 

BST 

MESSAGE 

ASSEMBLER 

TTCVI 

FIFOs 

FIFO 1 FIFO 2 

CH A 

CH B 

Period = 88.9 µs (LHC) ; 23.1 µs (SPS) 

Figure 4 : Basic architecture and transmission sequence of BST Master. 

TO 

TTC Encoder 

FIFO 2 FIFO 1 FIFO 2 

FIFO 1

3.1 BST Message CONTENTS 



Page 7 of 18 

The size of the BST message is limited by several physical parameters such as the serial 

output bandwidth and the duration of message assembly process. A message of 32 Long format 

Commands/Data can cover all beam instrumentation needs. The 8-bit sub-address allows 256 

identified bytes of data to be sent. Table 1 defines the contents of each byte and its update 

frequency. This table is subject to change according to LHC operation or end users requirements. 

Bytes Description Data format Updated every 

0 Machine Mode Enumerated type: No beam, filling, ramping, physic,… On change 

1 Beam Type Enumerated type: Ion, Proton,… On change 

2 Beam Energy 

3 Beam Energy 

2 bytes in GEV On change 

4 Mean Current per Bunch 

5 Mean Current per Bunch 

2 Bytes * 10E11 ppp 

6 Number of injected Bunches 

7 Number of injected Bunches 

2 Bytes integer On change 

8 Next Batch to Inject 0 for no beam or 1 .. 12 On change 

9 GPS Absolute Time 








64 bits UTC format On change 

17 Last Machine Timing Event 

18 Last Machine Timing Event 

2 Bytes : Machine Timing Event number On reception 

19 BI Predefined received Events 

20 BI Predefined received Events 

2 bytes : corresponding to 16 predefined events table On reception 

21 Main Trigger Byte 8 X 1 bit dedicated Trigger: warning injection, start post-mortem, … 1 Turn 

22 BI devices dedicated Bytes 10 Bytes device dedicated commands or triggers : 1 Turn 

23 BI devices dedicated Bytes 









Closed orbit capture, Single Turn trajectory measurement,…. 

Bytes 0 to 20 (the data in blue) come from the new slow timing interface (TGR module) [7] where a 

time granularity of 1ms is adequate. Bytes 21 to 31(the data in green), where a time granularity of 1 

turn is required, come either from an external trigger (e.g. an injection warning) or a demand from 

an operator application process (e.g. a closed orbit acquisition). There is also a possibility of 

inserting a time stamp to allow the clear identification of measurements. 

4. TTCbi OVERVIEW 

The TTCbi is another key component of the BST system, and is the subject of this 

specification. It has the task of interfacing the TTC system with the beam instrumentation, and is 

found at the end of the TTC distribution network. A PMC format has been chosen for the TTCbi, 

allowing it to be plugged into different types of motherboard. Most beam instrumentation 

applications will be based on a standard VME bus, and the TTCbi will therefore reside on a 

dedicated PMC connector on the CPU itself, giving a direct connection of hardware signals to and 

from the VME P2 user I/O connector. The TTCbi is built around the TTC receiver ASIC (TTCrx) [5] 

and the basic features of the card depend on this chip. In addition to delivering the timing signals,

PROM 

Optical 

Input 



Page 8 of 18 

the TTCrx is used to handle the delivery of BST messages to the local CPU. The received 

messages are stored in a dual ported memory which is accessible, together with all control 

registers, from the CPU via a commercial PCI interface. All the control logic is put in an FPGA with 

the possibility of being reprogrammed. As it is not foreseen to install beam instrumentation 

controllers in irradiated areas, the TTCbi is not made with radiation-hard materials. 

5. FUNCTIONAL DESCRIPTION 

5.1 ARCHITECHTURE 

Figure 5 shows the architecture of the TTCbi. The core function of the board is enclosed in the 

TTCrx circuit. A complete description of the chip and its functionality can be found in reference [5]. 

TTCrx 

Deskewed 

CLOCK 

L1A trigger 

OUT 

EVENT 

COUNT 

Differential 

input 

SUB ADDR 

DATA 

I2C 

STATUS 

JTAG 

Coarse Delay 

Local 

Message 

Generator 

IRQ MASK 

Dual 

Ported 

Memory 

I2C Bus 

Interface 

PROM 

FPGA 

Figure 5 : TTCvi Bloc Diagram 

Outputs 

selection 

CONTROL 

LOGIC 

PCI 

Bus 

Interface 

OUTPUT: 

Bunch Clock 

Turn Clock 

Hardware 

Bytes 

Front Panel 

Leds 

& 

Diagnostic 

PCI 

BUS 

The incoming optical frame is converted into a differential signal by a photodiode with integrated 

pre-amplifier. The TTCrx recovers the 40MHz LHC reference clock with minimum jitter, and can 

deskew it in steps of 104ps. The recovery circuit extracts the data stream and demultiplexes the 

two channels. Channel A is identified as a Level 1 Trigger and an Event Counter is incremented 

each time it occurs. The data in channel B is fed into a serial to parallel converter, which decodes 

and sends out the two supported data formats (broadcast or individually addressed message). A 

hamming error detection/correction circuit can detect double bit errors, and correct single bit errors. 

An I2C interface is used to allow read/write accesses to all internal registers, the status of which 

can be read directly from the PCI bus interface. An optional PROM can be use to load pre-defined 

register values after a reset.



Page 9 of 18 

A key card component is the PCI 9050 high performance bus interface described in reference [8]. 

The 9050 is configured as a direct data transfer to a 32 bit non-multiplexed local bus, and can 

generate a PCI interrupt from a user interrupt request. The local bus is used to access two chips: 

1) The PCF8584 I2C bus controller, which serves as an interface between the parallel local bus 

and the serial I2C bus for bi-directional connection with the internal registers of the TTCrx. The 

control of the I2C bus specific sequences, protocol and timing can be found in reference [9]. 

2) The XILINX FPGA, where all logic functions are implemented. On reboot, the FPGA 

configuration is downloaded from a Flash PROM, which is itself in-situ programmable using a 

Boundary-Scan (JTAG port) [10]. All signals from the TTCRx, local bus, output connections, front 

panel LEDs and diagnostics are routed to the FPGA I/O ports. The FPGA's configuration is 

designed using VHDL code [11], giving the maximum of flexibility for satisfying future requirements. 

The TTCbi is currently designed with the following FPGA functionality: 

• All received data bytes from the TTCrx are written in the corresponding sub-address of 

a dual-ported RAM. The 24-bit turn clock event counter delivered by the TTCrx is 

recorded at the beginning of each turn clock period in order to be read by the local 

controller together with the RAM contents. 

• The TTCrx chip has only a 0 to 375ns coarse delay range. This is insufficient to 

compensate for the time of flight of particles to different locations around the 

accelerators. Hence a local turn clock delay has been added to allow a 25 ns step 

delay of up to 88.9µs for the LHC and up to 23.1µs for the SPS, corresponding to one 

revolution period respectively in each machine. 

• Four programmable Two Data Bytes, called "hardware", selected among the received 

message can be sent directly to the hardware connector together with the two main 

clocks (bunch and turn clocks), synchronous with the rising edge of the Local Delayed 

Turn Clock. Two 8-bit registers are used to define the two sub-addresses of the data 

bytes to be sent. 

• 8-bit mask registers are used to control interrupt generation to the local controller. Two 

of these masks are used to identify the two possible sub-addresses at which the data 

which will generate the interrupt is to be found. Each of these sub-addresses then has 

its own specific data mask to generate the interrupt. An interrupt will be generated if at 

least one of the bits of the mask is present in the data byte of a received command 

corresponding to the appropriate sub-address. When an interrupt is generated, the 

overwriting of dual port memory is stopped after storing the current message, and is 

only restarted after the message has been read. 

• Three 16-bit counters are used to record single-bit, double-bit and transmission errors 

detected by the TTCrx. In case of double-bit or transmission detection, the 

corresponding command is rejected. 

• In the absence of the optical signal, an internal Message Generator can locally 

simulate a sequence of up to 32 preloaded commands with the associated timing 

signals. The sequence can be generated either once (Single-shot mode) or on every 

simulated local turn clock (Repetitive mode). 

• A global control / status register, detailed in section 5.5, allows the remote control of 

the board. 

• The front panel, detailed in section 5.6, regroups three main signals and 8 indicator 

LEDs, to give an overview of the board status. 

• For test and debugging purposes, the 40 MHz clock and 16 control signals detailed in 

section 5.3 are routed to a test connector where a logic state analyser such as the 

HP16500 series can be attached.

5.2 OVERALL FEATURES 



Page 10 of 18 

• PMC slave card conforming to the IEEE P1386.1 standard. 

• Provides Beam Synchronous Timing for both the LHC and SPS accelerators. 

• Supplies the 40.08 MHz Bunch Clock, which remains synchronous with the bunch structure. 

• Supplies the Local Turn Clock, corresponding to the orbit frequency. Locked either at 1/924 of 

the bunch frequency for SPS or 1/3564 of the bunch frequency for LHC. 

• Local delays provide Local Clocks with the appropriate phase relative to the beam structure, 

taking into account the difference between particle time-of-flight and signal propagation. 

• The overall jitter of the received clocks anywhere around the rings is less than 1ns rms. 

• A BST message consists of 32 BST commands within the 88.9 µs of an LHC period or up to 8 

BST commands within the 23.1 µs of an SPS period. 

• A BST command contains 2 bytes: a sub address or identifier, and its associated data byte. 

• Two predefined Data Bytes among the 32 sub-addresses can be routed to a hardware 

connector. 

• All the received commands are stored in a dual-ported RAM accessible by the local controller. 

• According to the PCI local bus specification, the TTCbi uses 256 bytes of configuration space. 

• All control registers and dual-ported RAM are mapped into the PCI memory or I/O spaces. 

• A PCI interrupt request can be generated on reception of a specific message or on error. 

• A local clock signal generator and up to 32 byte BST command message generator allows the 

TTCbi module to run in stand-alone mode for test purposes. 

• Optical Input, main timing signal outputs and indicator leds are available on the front panel. 

• All output signals are available on the 64 pin PMC I/O to be routed to the 64 pin I/O of the VME 

P2. 

• A PMC Connector supplies the following standard power supply from the VME motherboard:+ 

5 V Max 1A ; + 3.3 V Max 1A ; + 12V and - 12v (not used ). 

6. EXTERNAL SIGNALS 

Front Panel: The only required connection is TTC IN, all other signals and LEDs are for test purposes. 

Item: Description: 

TTC IN TTC Optical signal input : ST-PC connector on HFBR-2316T Receiver. 

Optical input power : operating range -22 dBm .... -18 dBm. 

CH B Serial Channel B, buffered output from TTCrx : Lemo 00 connector ; TTL level / 1 MΩ . 

LED is ON when CH B =1. 

LTC Local delayed Turn Clock, buffered output: Lemo 00 connector; 25ns. pulse / 2V / 50Ω 

From TTCrx L1 trigger in external mode or local generator in internal mode. 

LED is ON when LTC is present. 

40M Local 40 MHz Clock, buffered output: Lemo 00 connector ; square pulse / 2V. / 50 Ω . 

From TTCrx CKD1 in external mode or local generator in internal mode. 

LED is ON when 40M is present. 

ACCESS LED is ON when any registers are accessed from the PCI bus. 

MESS IN LED is ON when a message is received from TTCrx or local generator. 

INTERNAL LED is ON when internal mode is set in the global control register. 

TTC RDY LED is ON when TTCrx ready status = 1. 

RESET LED is ON when a local reset from PLX is present.



Hardware connector: Signals are connected to the 32 pin PMC J4 to be routed to the VME P2. 

J4 Pin: P2 Pin: Signal description: 

33 C17 Local 40 MHz Clock buffered output : square pulse LVDS + 

34 A17 " " LVDS - 

35 C18 Local 40 MHz Clock, buffered output : square pulse TTL 

36 A18 GND 

37 C19 Local delayed Turn Clock, buffered output: 25 ns pulse LVDS + 

38 A19 " " LVDS - 

39 C20 Local delayed Turn Clock, buffered output: 25 ns pulse TTL 

40 A20 GND 

41 C21 Spare 

42 A21 Spare 

43 C22 Spare 

44 A22 Spare 

45 C23 Hardware Byte 0 bit 0, output TTL . Valide on 40 MHz rising edge. 

46 A23 " bit 1, " " 

47 C24 " bit 2, " " 

48 A24 " bit 3, " " 

49 C25 " bit 4, " " 

50 A25 " bit 5, " " 

51 C26 " bit 6, " " 

52 A26 " bit 7, " " 

53 C27 Hardware Byte 0 strobe, output TTL . Valide on 40 MHz rising edge. 

54 A27 GND 

55 C28 Hardware Byte 1 bit 0, output TTL . Valide on 40 MHz rising edge. 

56 A28 " bit 1, " " 

57 C29 " bit 2, " " 

58 A29 " bit 3, " " 

59 C30 " bit 4, " " 

60 A30 " bit 5, " " 

61 C31 " bit 6, " " 

62 A31 " bit 7, " " 

63 C32 Hardware Byte 1 strobe, output TTL MHz Valide on 40 rising edge. 

64 A32 GND 

Page 11 of 18 

Test header J1: To be used for test and debugging purposes. Will fit the HP1600 Logic State 

Analyser, for which a number of acquisition setups already exist. The 16 signals and the clock are 

routed from the XILINX chip output port and can be selected from amongst all internal signals 

according to the user request (see example below). 

Pin POD Signal Description 

3 CLK CK40M : Clock correspondiing to the signal send to hardware connector 

4 D15 L_CS0 : Local chip select 0 from PCI9050: Active L 

5 D14 Data_OUT(0) : LSB of local data bus output 

6 D13 Turn_Count_Reg(0) : LSB of local turn counter register 

7 D12 T_BCNT(0) : LSB of Bunch count number from TTCrx 

8 D11 T_EVCNTR : Event counter reset from TTCrx ; Active H 

9 D10 T_EVCNTL : Event counter strobe LSB from TTCrx ; Active H 

10 D9 T_EVCNTH : Event counter strobe MSB from TTCrx ; Active H 

11 D8 L_WRITE : Local Write from PCI9050 ; Active L 

12 D7 L_READ: Local Read from PCI9050 ; Active L 

13 D6 Mess_Out_En : Enable hardware mess out active H 

14 D5 M_DStr : Message Data strobe into dual ported RAM; Active H 

15 D4 M_Data(0) : LSB of Message data writted into dual ported RAM



16 D3 M_SAddr(0) : LSB of Message subadress writted into dual ported RAM 

17 D2 L_DoutStr : Data strobe from local message generator; Active H 

18 D1 L_Mess_Data(0): LSB of local message 

19 D0 LTC: Turn Clock correspondiing to the signal send to hardware connector 

20 GND 

JTAG header J2: To be used for downloading the FPGA configuration using a JTAG [11] port. 

Strap settings: 

Pin1 : GND Pin4 : TCK 

Pin2 : TDI Pin5 : TDO 

Pin3 : TMS Pin6 : VCC 

7. BOARD CONFIGURATION 

Page 12 of 18 

• ST2 : TTCrx configuration mode. 

PROM = Configuration downloaded from XC1736 PROM on power-on or TTC reset. 

NO PROM = Default configuration or downloaded from I2C bus or TTC commands. 

• ST3 : To perform a direct access to XCV50 JTAG[10] port. Used only for debugging. 

ON = bypass XC18V01 PROM in JTAG [10] chain.(For test only) 

OFF = Setting for normal use. 

• ST4 : PCI 9050 interface access control. 

ON = Enable PCI bus access ( Normal mode) 

OFF = Disable PCI bus access ( For test only) 

• ST5, ST6, ST7: XCV50 configuration mode M1, M0, M2 (see XILINX specifications.) 

ON OFF OFF = Configuration downloaded from JTAG[10] port J2.(For test only) 

ON ON ON = Configuration downloaded from XC18V01 flash PROM. (Default) 

The configuration is first downloaded into the PROM using the JTAG[10] port, then transferred to 

the XCV50 on next power-on, or by setting the reprogram bit of global control register. 

• ST8 : 3.3V power supply source according to the PCI specification [12]. 

P3V3 = from PMC connector (if provided by mother board.) 

P3V3A = from on-board TPS767D325 regulator. 

8. MEMORY MAP 

All PCI accesses are 16 or 32 bits, using the 33MHz PCI clock with 128 Mbytes/sec block transfer 

capability. The PCI interface is constructed using a low price PCI 9050 target interface from PLX. [8]. As 

for all PCI devices, the TTCbi has 256 bytes of configuration space. System software may, on reboot, 

scan the configuration space to determine the device identification and parameters. One of the most 

important parameters is the base address, which maps the device into the PCI address space. 

The TTCbi uses 4 blocks of address space defined in the configuration register as follow: 

Block 0 : PLX Local Configuration registers mapped into 128 bytes of memory address space. 

Block 1 : PLX Local Configuration registers mapped into 128 bytes of I/O address space. 

Block 2 : FPGA internal registers and memories mapped into 1K bytes of memory address space. 

Block 3 : I2C interface registers mapped into 8 bytes of I/O address space. 

8.1 REGISTERS 

On power ON, the PCI 9050 registers are initialised using a serial EEPROM type National 

NM93CS46 and can be accessed in block 0 or 1.

EEPROM 

Byte 

Initial 

VALUE 

Destination 

Registre Description 



00 01 90 50 PCI 02h Device ID. 9050 

02 03 10 B5 00h Vendor ID. 10B5 

04 05 06 80 0Ah Class Code. 

06 07 00 00 08h Class code revision (is not loadable) 

08 09 90 50 2Eh Subsystem ID. 9050 

0A 0B 10 B5 2Ch Subsystem Vendor ID. 10B5 

0C 0D 00 00 3Eh Maximum Latency and Minimum Grant (not loadable) 

0E 0F 01 01 3Ch Interrupt Pin (Interrupt Line is not loadable)=01xx 

10 11 0F FF LOCAL 02h MSW of Range for PCI to Local Address Space 0 

12 13 FC 00 00h LSW = 1k Bytes Mem SPACE FOR FPGA 

14 15 0F FF 06h MSW of Range for PCI to Local Address Space 1 

16 17 FF F9 04h LSW = 8 Bytes IN I/O SPACE FOR I2C 

18 19 00 00 0Ah MSW of Range for PCI to Local Address Space 2 

1A 1B 00 00 08h LSW NOT USED 

1C 1D 00 00 0Eh MSW Range for PCI to Local Address Space 3 

1E 1F 00 00 0Ch LSW NOT USED 

20 21 00 00 12h MSWRange for PCI to Local Expansion ROM (64 KB). 

22 23 00 00 10h LSW NOT USED 

24 25 00 00 16h MSW Local B.A.(Remap) for PCI to Local Add Space 0 

26 27 00 01 14h LSW LOCAL Base Addr = 0 ; + 1 = direct slave 

28 29 00 00 1Ah MSW Local B.A.(Remap) for PCI to Local Add Space 1 

2A 2B 04 01 18h LSW LOCAL Base Addr = 400h ; + 1 = direct slave 

2C 2D 00 00 1Eh MSW Local B.A.(Remap) for PCI to Local Add Space 2 

2E 2F 00 00 1Ch LSW NOT USED 

30 31 00 00 22h MSW Local B.a.(Remap) for PCI to Local Add Space 3 

32 33 00 00 20h LSW NOT USED 

34 35 00 00 26h MSW of Local B.A.(Remap) for PCI to Local Exp. ROM. 

36 37 00 00 24h LSW NOT USED 

38 39 54 91 2Ah MSW of Bus Region Descriptors for Local Add Space 0 

3A 3B 28 80 28h LSW32 b;No Burst;No wait 

3C 3D FC 27 2Eh MSW of Bus Region Descriptors for Local Add Space 1 

3E 3F 7B 80 2Ch LSW :08 b;NoBurst;+wait=10,1,3,10,0;+delay=1,1,1 

40 41 00 00 32h MSW of Bus Region Descriptors for Local Add Space 2 

42 43 00 00 30h LSW NOT USED 

44 45 00 00 36h MSW Bus Region Descriptors for Local Add Space 3 

46 47 00 00 34h LSW NOT USED 

48 49 00 00 3Ah MSW Bus Region Descriptors for Expansion Space 


4C 4D 00 00 3Eh MSW of Chip Select (CS 0) Base and Range Register. 

4E 4F 02 01 3Ch LSW : Enable 1 KB at addr 0 for XILINX pga. 

50 51 00 00 42h MSW of Chip Select (CS1 ) Base and Range Register. 

52 53 04 09 40h LSW : Enable 8 By at addr 400h for I2C interface. 

54 55 00 00 46h MSW of Chip Select (CS2 ) Base and Range Register. 

56 57 00 00 44h LSW NOT USED 

58 59 00 00 4Ah MSW of Chip Select (CS3 )Base and Range Register. 


5C 5D 00 00 4Eh MSW of Interrupt Control/Status Register. 

Page 13 of 18



5E 5F 00 41 4Ch LSW Enable IRQ1 active low 

60 61 00 20 52h MSW EEPROM Control Register:ready delay =32 clks 

62 63 0C 00 50h LSW User 0,2,3= Out active low; User 1 =In 

64 .. XX XX NOT USED 

Page 14 of 18 

After initialisation, the PCI interface allows access to the non-multiplexed 32-bit local bus. Burst or 

continuous single cycle in Big Endian (no swapping) is used. 

The PCI Interrupt A can be requested using Local Interrupt 1 and 2 from XILINX FPGA. 

Direct slave access of 1 Kbytes in the Local Address Space 0 allows access to all registers and 

dual-ported RAM of Xilinx FPGA. 

Item R W Add Size Byte 3 Byte 2 Byte 1 Byte 0 Comments 

Control W 0 Byte xxxxxxx xxxxxxx xxxxxxx Control See details below 

Control & Status R 0 Word xxxxxxx xxxxxxx Status Control " 

Coarse Delay R/W 4 Word xxxxxxx xxxxxxx bit 11 …. 0 25 ns step delay 

Hardware Bytes Select R/W 8 Word xxxxxxx xxxxxxx Byte 1 Byte 0 0…255 ; 0…255 

Hardware Bytes Output R C Word xxxxxxx xxxxxxx Byte 1 Byte 0 read back outputs 

IRQ Bytes Addr Select R/W 10 Word xxxxxxx xxxxxxx Byte 1 Byte 0 0…255 ; 0…255 

IRQ Bytes Addr Mask R/W 14 Word xxxxxxx xxxxxxx Byte 1 Byte 0 00…FF ; 00...FF 

Single TTC Error count R/W 20 Word xxxxxxx xxxxxxx 16 bit counter Reset on write 

Double TTC Error count R/W 24 Word xxxxxxx xxxxxxx 16 bit counter Reset on write 

Ready TTC Error count R/W 28 Word xxxxxxx xxxxxxx 16 bit counter Reset on write 

Turn Clock Count R/W 30 LWord xxxxxxx 24 bit counter Reset on write 

Local Message : R/W 80 Word xxxxxxx xxxxxxx Sub Add Data Cmd 0 

= 32 Commands R/W 84 Word xxxxxxx xxxxxxx Sub Add Data Cmd 1 

R/W 88 Word xxxxxxx xxxxxxx Sub Add Data Cmd 2 

.. …. …. xxxxxxx xxxxxxx …. … … 

R/W FC Word xxxxxxx xxxxxxx Sub Add Data Cmd 31 

DP Ram Mess Input R 100 Lword Cmd 3 Cmd 2 Cmd 1 Cmd 0 CmdData @ SubAdd 

= 256 Commands R 101 Lword Cmd 7 Cmd 6 Cmd 5 Cmd 4 “ 

R 102 Lword Cmd 11 Cmd 10 Cmd 9 Cmd 8 “ 

… … … ….. …. …. …. “ 

R 1FC Lword Cmd255 Cmd254 Cmd253 Cmd252 “ 

Control Register: bit 0 Internal mode = 1 ; External mode = 0 ( Default); 1 = local 40MHz on 

bit 1 Sub mode : Single shot = 1; Repetitive = 0 ( Default) 

bit 2 DP Ram Write Control : Enable = 1; 

bit 3 Hardware Bytes Output Control : Enable = 1 

bit 4 IRQ from Masks control : Enable = 1 

bit 5 IRQ from Masks control : Clear Request = 1 

bit 6 SPS = 1; LHC = 0 ( For diff. Bunch count ) 

bit 7 Spare 

Status Register: bit 0 TTC Input Ready = 1 ; 0 = No Input signal 

bit 1 1 = Local 40MHz present 

bit 2 1 = Local Turn Clock present 

bit 3 1 = TTC Serial B input signal present 

bit 4 1 = TTC Frame error 

bit 5 1 = Message record 

bit 6 1 = IRQ set from Masks 

bit 7 Spare



Page 15 of 18 

Direct slave access in the Local Address Space 1 of 8 bytes allows accessing all the PCF8584 I2C 

bus controller registers. The PCF8584 [9] has 5 internal registers but occupied only two byte locations. 

Register selection between the control/status register S1 and the other registers depending on bits loaded in 

ESO, ES1 and ES2 of register S1. 

Item R/W ADD h Access Byte 0 Comments 

Data Reg R/W 00 Byte Data Register Depends on ES2, ES1, ES0 

Control Reg S1 W 04 Byte Control See details below 

Status Reg S1 R 04 Byte Status " 

Control Register S1 : bit 0 Automatic Acknowledgement = 0 in master mode 

bit 1 Stop transmission = 1 

bit 2 Start transmission = 1 

bit 3 Enable Interrupt = 0 ( No irq ) 

bit 4 ES2 

bit 5 ES1 

bit 6 ES0 

bit 7 Reset all status registers = 1 

Status Register S1 : bit 0 BB = 1 : Bus Busy ( in use) 

bit 1 LAB = 1 : Loss Arbitration 

bit 2 AAS = 1: Addressed As Slave 

bit 3 LRB = 1 : Last Received Bit 

bit 4 BER = 1: Bus error detected 

bit 5 STS = 1 : stop receive detected 

bit 6 X = Not used 

bit 7 PIN = 0 when transmission is completed 

The default Interface Mode Control (8080 type) is used (separate Write & Read without dtack), 

along with master transmitter / receiver mode without interrupts. 

On reset all registers are set by default to the required values: 

Register S0’ = 0 : PCF8584 Own I2C address = 0; 

Register S2 = 0 : Serial Clock frequency = 90 KHz ; System clock frequency = 3 MHz. 

The I2C bus is used to read or write the TTCrx user accessible registers listed below. According to 

the I2C bus specification [13], the TTCrx device on the bus is addressed by a 7bit wide address. 

The TTCrx chip occupies two consecutive positions in the I2C address space. The I2C address is 

derived from the device base address register in the following way: 

I2C access register : Resulting I2C address : 

TTCrx Register Address pointer Device Base Address * 2 

TTCrx Register Data Device Base Adress *2 + 1 

On power on, all registers are initialised to a default value before ten specific registers are loaded 

with the contents of the optional XC1736 EPROM as defined below.



Page 16 of 18 

register 

Content 

Value 

From Prom 

Address TTCrx Register name [5] after reset prom: add: Comments: 

0Fine Delay 1 0 12 0 Default for test 

1Fine Delay 2 0 0 1 not used 

2Coarse Delay 0 0 2 not used 

Enable : CKD1, SerialB, 

3Control 10010011 72 3 L1Accept, EventCount 

8Single error count 0 

9Single error count 0 

10Double error count 0 

11SEU error count 0 

16 ID 0 0 4 Default TTC Address =0 

Set master modeTCC add = 

17MasterModeA, ID 0 0 5 0 

MasterModeB, I2C_ID 

Set master mode I2C Add = 

18 

0 1 6 1 

19Config 1 10 2 7 Default value 

20Config 2 10000100 84 8 Default value 

21Config 3 10100111 A7 9 Default value 

22Status 11100000 

24Bunch Counter Bits 0 

25 “ 0 

26Event Counter Bits 0 

27 “ 0 

28 “ 0 

9. CONTROL SOFTWARE 

In order to use the TTCbi board in the LHC BI Front Ends, a dedicated driver, the 

corresponding library as well as a local and remote test programs will be developed by 

the SL-BI software section. 

The resulting interface will allow the user to: 

– configure its TTCbi (mainly select the bytes redirected to P2 and CPU 

interrupts). 

– read asynchronously the generic information available like the beam intensity, 

energy, the GPS time or the internal error registers… 

– subscribe to interruptions generated by the TTCbi card. 

This software will be made available for every operational platforms (CPU and Real 

Time OS) used by SL-BI. Today, this is limited to PowerPC CPUs running LynxOS3.1. 

A first version of this software limited to the functionalities available in the SPS BST 

Master will be available around the 2002 start-up. It will be documented in a dedicated 

technical specification and available during Q2 2002 in the SL-BI software section 

EDMS repository for LHC software 

[http://edmsoraweb.cern.ch:8001/cedar/navigation.tree?cookie=872506&p_top_id=1 

598559859&p_top_type=P].

10. REFERENCES 

[1] LHC Timing Requirements 

Gary BEETHAM SL/CO et al. 

http://lhc-proj-timwg.web.cern.ch/lhc-proj-timwg 

[2] Timing, Trigger and Control (TTC) Systems for LHC Detectors 

Bruce TAYLOR EP/CMD 

http://ttc.web.cern.ch/TTC/intro.html 

[3] LHC Machine Timing Distribution for the Experiments 

B.G. Taylor EP/CMD 

http://ttc.web.cern.ch/TTC/intro.html 

[4] PMC specification IEEE standard P1386.1 

http://pcisig.com 



Page 17 of 18 

[5] TTCrx Reference Manual: A Timing,Trigger and Control Receiver ASIC for LHC Detectors 

J.Christiansen EP/MIC et al. 

[6] TTC-VMEbus Interface (TTCvi) EP 680-1128-050-C 

P.Farthout, P.Gallno EP/ATE 

[7] THE LHC Machine TIMING SYSTEM FUNCTIONAL SPECIFICATION 

Gary BEETHAM SL/CO et al. 

[8] PLX PCI 9050-1 Data Book; Version 1.02; December 1999 : 

http://www.plxtech.com 

[9] PCF8584 I2C-bus controller; Product specification ; 

http://www.semiconductors.philips.com 

[10] JTAG / Boundary scan IEEE 1149.1 standard. 

[11] Very high speed integrated circuit Hardware Description Language. IEEE 1164 standard. 

[12] PCI Local Bus Specification Revision 2.2 December 18, 1998. 

[13] The I2C BUS SPECIFICATION Version 2.0 December 1998

11. PICTURES 

Component side: 

Wiring side: 



Page 18 of 18

Preliminary Ttcbi

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