Fabric Manager Users Guide, Version 6.1, Revision A - QLogic

2–Advanced Fabric Manager Capabilities
Fabric Unicast Routing
The Shortest Path algorithm has one option: SpineFirstRouting. When
enabled, this will avoid credit loops in complex full bisectional bandwidth
(FBB)—like fabrics which use QLogic 12000 and 9000 Series modular switches.
Given equal cost routes, SpineFirstRouting routes through chassis spine first. This
avoids credit loops caused by routing using edge/leaf switches instead of spines.
SpineFirstRouting is enabled by default and has no ill side effects. Unlike simpler
algorithms in other SMs, the QLogic SM's shortest path algorithm has
sophisticated traffic balancing and routing algorithms which allow it to provide high
performance for a wide variety of topologies
Fat Tree
The Fat Tree algorithm can provide better balancing of ISL traffic than the
shortestpath algorithm. It accomplishes the balancing of ISL traffic through
identification of the topology and figuring out what tier in the fabric each switch is
at. To accomplish figure out the switch tier it needs to understand how many tiers
of switch chips there are in the fabric and whether all Host Cannel Adapters and
Target Channel Adapters are at the same tier or on varied tiers of the fabric. Large
switches typically have multiple internal tiers of switch chips. For example, all the
QLogic 12800 series models have two tiers of switch chips.
Dimension Ordered Routing — Up/Down (dor-updown)
This routing algorithm is only for mesh and torus topologies. It provides shortest
path routing while avoiding credit loops. Dimension Ordered Routing (DOR) refers
to a specific method of routing a mesh or torus fabric that avoids credit loops while
preserving shortest paths. Refer to Figure 2-1
Figure 2-1. Dimension Ordered Routing
In the context of DOR, mesh refers to an N-dimensional grid of switches, where
each node is linked along each dimension to a neighbor in both the forward and
reverse direction. One can easily imagine 2D planes where each switch is linked
to 4 neighbor switches, and 3D cubes where each switch is linked to 6 neighbor
switches. End nodes are evenly distributed over the switches. Refer to Figure 2-2
2-4 IB0054608-01 B