Evaluating Virtex-II Pro Development System, it's features and ...

Vasko Mitanov
Faculty of Electrical Engineering and Information Technologies,
University Ss. Cyril and Methodius, Macedonia
Email: vasko.mitanov@gmail.com

Provides an advanced hardware platform that
consists of a high performance Virtex-II Pro
Platform FPGA
Surrounded by a comprehensive collection of
peripheral components that can be used to
create a complex system and to
demonstrate the capability of the Virtex-II
Pro Platform FPGA.

The core of development board is Xilinx Virtex-II
Pro XC2VP30
Virtex®-II Pro FPGA with PowerPC® 405 cores
Up to 2 GB of Double Data Rate (DDR) SDRAM
System ACE controller and Type II
CompactFlash connector for FPGA configuration
and data storage
Embedded Platform Cable USB configuration port
High-speed SelectMAP FPGA configuration from
Platform Flash In-System
Programmable Configuration PROM
Support for “Golden” and “User” FPGA
configuration bitstreams

On-board 10/100 Ethernet PHY device
Silicon Serial Number for unique board identification
RS-232 DB9 serial port
Two PS-2 serial ports
Four LEDs connected to Virtex-II Pro I/O pins
Four switches connected to Virtex-II Pro I/O pins
Five push buttons connected to Virtex-II Pro I/O pins
Six expansion connectors joined to 80 Virtex-II Pro
I/O pins with over-voltage protection
High-speed expansion connector joined to 40 Virtex-
II Pro I/O pins that can be used differentially or single
ended

AC-97 audio CODEC with audio amplifier and
speaker/headphone output and line level output
Microphone and line level audio input
On-board XSGA output, up to 1200 x 1600 at 70 Hz
refresh
Three Serial ATA ports, two Host ports and one
Target port
Off-board expansion MGT link, with user-supplied
clock
100 MHz system clock, 75 MHz SATA clock
Provision for user-supplied clock
On-board power supplies
Power-on reset circuitry
PowerPC 405 reset circuitry

5V Regulated Power Supply Interface. The board includes
power supply subsystem for generating additional 3.3V,
2.5V and 1.5V for various block of the FPGA (core,
peripheral, I/O)
The board includes 8 Multi-Gigabit Transceivers. Three
pairs of MGT are terminated by SATA connectors located
on the board and one pair is terminated by optional SMA
connector. There is independent 75MHz clock for SATA
communication via MGT transceivers. Two SATA ports are
configured as Host ports, one port is configured as Target
port.
Another very important feature of the board is
incorporated JEDEC 184 pin DDR (Double Data Rate)
SDRAM port which supports up to 2 GB memory modules.

Fast Ethernet 10/100 IEEE compliant interface is implemented on
the board. Only the PHY is implemented and the MAC layer is left
to the developer to implement this layer and upper layers in
FPGA. The Ethernet interface is implemented as standard RJ-45
connector on the board.
One Serial RS232 Port and two PS/2 ports are provided on the
board. The RS-232 port is implemented as DB-9 connector on
the board. The board provides electronic circuits to provide
necessary voltage levels for RS-232 standard.
The board provides XSGA interface via DAC with 180 MHz clock.
This DAC can provide VESA compatible output of 1280x1024
pixels at refresh rate of 75 Hz or maximal 1600x1200 pixels at
70 Hz refresh rate. Also 15 pin D-SUB connector is supplied on
the board for connecting to monitor.

AC97 Audio codec with full-duplex stereo ADC and DAC
are implemented on the board. This CODEC provides
analog mixing and combining capabilities of microphone
input, line-in input and PCM data. Output is stereo power
amplified. There are standard audio input/output
connectors located on the board.
For various display and information purposes, the board
includes four LED diodes which can be controlled by FPGA,
four DIP Switches and five push buttons. All of these LEDs,
switches and push buttons are controlled/monitored by
FPGA directly. Specific pins on which this buttons and LEDs
are connected can be found in UCFs (User Constraint
Files), provided with additional CDs in the package along
with this board.

The board is programmed via USB 2.0 interface. This
interface configures and programs FPGA via
Boundary-Scan.
The board includes System Advanced Configuration
Environment controller. This controller provides FPGA
with configuration from various sources. This
controller support: Compact Flash Port, JTAG Port,
Microprocessor port and Test JTAG Port.
Each board includes unique silicon serial number
(SSN) which can be read by FPGA and can be used in
designs where unique identification of the board is
required.

Virtex-II Pro Development System does not
come with any development or design tools
for HDL, synthesis, design implementation or
configuration of FPGA XC2VP30.

EDA tools from Xilinx that support this
development system:
- ISE Design Suite
- Embedded Developers Kit (EDK) and
- ChipScope Pro.

ISE Design Suite from Xilinx is complete design environment for
developing FPGA in all phases:
Design entry. Process of describing design of the system in one
of the following ways: by HDL, VHDL, Verilog, System-C or
schematic.
Synthesis. Process of generating netlist files from designs of
previous phase.
Implementation. Converting logical design into device dependant
format.
Verification. Process of verifying functionality of design.
Verification can be made by simulator or with ChipScope Pro by
in-circuit verification process after device programming.
Device Configuration. The process of download configuration
files to development board.

Important notes regarding ISE:
Last supported version of ISE supported by
Virtex-II Pro Development System is ISE v10.1
Newer versions of ISE(11.x+) are not
supported.
Older versions of ISE (7.0 - 9.2) don’t fully
support Virtex-II Pro board.
ISE WebPACK edition (the only free edition
of ISE) is not supported by Virtex-II Pro
Development System.

EDK is integrated development environment for
designing embedded processing systems.
Supported embedded processor cores:
- PowerPC® 405 hard processor cores
- MicroBlaze soft processor cores

ChipScope Pro is tool for analyzing internal
FPGA signals including embedded processor
busses.
Signals are captured at or near operating
speed.
Extensive support for embedded hard
processor cores PowerPC 405® and
MicroBlaze.

Tools and configuration files needed for setting up complete development
environment:
Xilinx ISE 10.1 (At least Foundation/Logic Edition). Can be bought from
Xilinx website: http://www.xilinx.com/tools/designtools.htm
Xilinx EDK. Can be bought separately or in bundle with Xilinx ISE 10.1
Embedded or with System Edition.
IP Cores for peripherals on Virtex-II Pro Development System. This IP
Cores can be found on CD that comes with board (the files are located in
directory \V2P_CD\lib on the CD). Note that these files cannot be found
on the Internet.
User Constraint Files (UCF) for this board. These files are describing pinout
and I/O drive characteristics for peripherals on Virtex-II Pro
Development Board (AC97/Ethernet/XSGA/DDR/Serial/PS2 etc…). Latest
version of these files can be downloaded from:
http://www.xilinx.com/univ/XUPV2P/UCF_Files/UCF_FILES.zip

Install ISE and EDK.
After installation of ISE and EDK, the installer automatically
installs Windows drivers that support communication
with Virtex-II Pro Development Board via USB.
After installation of USB Windows drivers, development
board can be connected to PC by supplied USB cable and
then can be powered ON.
After Windows detects development board and configures
appropriate drivers, the board needs to be configured with
utility iMPACT located in:
XILINX_INSTALL_DIR\10.1\ISE\bin\nt\impact.exe
Unpack and copy IP Cores for peripherals (directory
xup_v2pro_dev_brd) for example on c:\
xup_v2pro_dev_brd. DO NOT USE directories with names
containing spaces.
Unpack and copy User Constraint Files into same location

Optionally, if we want to use sample reference
designs supplied with CD that comes with Virtex-
II Pro board, we need to download and install:
◦ PLB IP Core for DDR memory version 1.11a
(plb_ddr_v1_11_a
plb_ddr_v1_11_a) from Xilinx support forums because
PLB IP Core for DDR supplied with ISE v10.1 is version
2.00.1b and is not backward compatible with version
1.11a.
For new designs IP core mpmc (Multi-Port Memory
Controller) should be used. Plb_ddr_v2_00 has obsolete
PLB v3.4 support. Xilinx migrated newest IP Cores to PLB
v4.6. (mpmc supports PLB v4.6)

Updated version of xup_v2pro_dev_brd that
supports Xilinx ISE 10.1 and EDK can be
found on Univeristy of Kansas website:
https://wiki.ittc.ku.edu/ittc/images/6/64/Xu
p_xbd.zip
This version additionally adds support for Multi
Port Memory Controller (mpmc IP).

◦ Problem with supplied reference designs using soft
IP Core xilnet v1.00a (xilnet_v1_00_a) for TCP/IP
stack because this IP Core is no longer supported
and distributed by Xilinx. Recommended
replacement for xilnet v1.00a by Xilinx is lwip IP
Core v1.00/v2.00/v3.00. Because lwip IP Core is
larger than xilnet (it requires OS supporting
functions), lwip can be used in RAW mode which
doesn’t require OS support. Lwip IP core is not API
compatible with Xilnet.

Purpose of this sample project:
To demonstrate some of the capabilities of
Virtex-II Pro Development System and to get
acquainted with development environment.

Following features were chosen to be evaluated:
Creation, Synthesis, Verification and Deployment of sample project in Xilinx EDK;
Embedded hardware processor cores Power PC® 405 located in XC2VP30 FPGA;
IP core wrapper for embedded hardware processor core (PPC405);
IP core for Serial Communication (RS-232);
IP core that controls/drives Dual Rank 512MB DDR memory;
Connecting DDR IP core with Embedded Processor IP Core via PLB bus;
Mounting external 512MB DDR Memory module on JEDEC 184 pin port to evaluate
board conformity (mechanical and electrical) to JEDEC DDR-SDR standard
specifications;
Developing example application in application programming language C that runs
on one of the Power PC 405 processor cores and uses all of above mentioned
features (IP cores, Embedded Processor, RS232 and DDR Interfaces) by testing
DDR 512MB memory and sends results to PC via RS-232 interface.

Results:
Software application running on one PowerPC core successfully
used all of the supplied 512MB external RAM memory and
results were successfully sent to host PC.
When the DDR memory module was removed* from the 184 pin
port, the software application running on PC successfully
detected absence of memory module.
Note that EDK project should be saved in directory that doesn’t
contain spaces (full path to the file). Because gcc compiler and ld
linker will fail.
*Memory Module was removed from the board while power was switched
off

Xilinx-II Pro development system has a lot of
peripherals integrated on the board which
can be used by supplied IP Cores
By proper installation and setup of software
and hardware environment, Xilinx-II Pro
development system becomes very powerful
FPGA research platform for commercial
purposes as well for engineering curricula

Thank You!