CMPUT 329 Memory Technologies Memory classes

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SRAM with Bi-directional Data Bus microprocessor WE_L CS_L OE_L WR_L IOE_L IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DIO3 DIO2 DIO1 DIO0 15 Internal Address Decoding The SRAM shown in the previous slides had 3 address lines and stored 8 words, requiring a 3-to-8 internal decoder. Such a decoder requires eight AND gates, with three inputs each, and three invertors. Consider the HM628512 SRAM that has 19 address lines and stores 512K words. What size internal decoder this chip requires? A 19-to-512K decoder with 524288 AND gates, each with 19 inputs? 16 8
HM628512 17 Internal Address Decoding To avoid such a complexity in the decoding logic, all memories (EPROMs, SRAMs, and DRAMs) use two-dimensional decoding which reduces the decoder size to approximately the square root of the number of addresses. The memory cells are organized in a two-dimensional array. Some address lines are used to select a row and the others are used to select a column. The cell selected by the whole address is at the intersection of the row and the column. 18 9
Page 1 and 2: CMPUT 329 Memory Technologies José
Page 3 and 4: Writing 1 in a Dynamic Memories bit
Page 5 and 6: Forgetful Memories bit line word li
Page 7: 0 A2 1 A1 1 A0 3-to-8 decoder 1 2 1
Page 11 and 12: Internal Structure of a 64K × 1 DR
Page 13 and 14: 25 26 13
Page 15 and 16: Fast Page Mode DRAMs In a DRAM with
Page 17 and 18: An Enhanced Data Output Read Cycle

CMPUT 329 Memory Technologies Memory classes

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