CMPUT 329 Memory Technologies Memory classes

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Static RAM Cell 3 Dynamic <strong>Memory</strong> Cell An SRAM cell has a bi-stable latch that requires from four to six transistors to be built. To deliver the higher memory density required for computer systems, a single transistor memory cell was developed. bit line word line 1-bit DRAM cell 4 2
Writing 1 in a Dynamic Memories bit line word line 1-bit DRAM cell To store a 1 in this cell, a HIGH voltage is placed on the bit line, causing the capacitor to charge through the on transistor. 5 Writing 0 in a Dynamic Memories bit line word line 1-bit DRAM cell To store a 0 in this cell, a LOW voltage is placed on the bit line, causing the capacitor to discharge through the on transistor. 6 3
Page 1: CMPUT 329 Memory Technologies José
Page 5 and 6: Forgetful Memories bit line word li
Page 7 and 8: 0 A2 1 A1 1 A0 3-to-8 decoder 1 2 1
Page 9 and 10: HM628512 17 Internal Address Decodi
Page 11 and 12: Internal Structure of a 64K × 1 DR
Page 13 and 14: 25 26 13
Page 15 and 16: Fast Page Mode DRAMs In a DRAM with
Page 17 and 18: An Enhanced Data Output Read Cycle

CMPUT 329 Memory Technologies Memory classes

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