CMPUT 329 Memory Technologies Memory classes

External Address Decoding
microprocessor
A0
A0
A1
A1
•
A19
A19
A0
27256
A0
A1
A1
•
A14
A14
CS
OE
O0
O1
O7
D0
D1
•
D7
A0
A0
A1
A1
•
A14
A14
CS
OE
27256 27256 27256
A0
A0
A0
A0
A1
A1
A1
A1
O0
O1
O7
D0
D1
•
D7
•
A14
A14
CS
OE
O0
O1
O7
D0
D1
•
D7
•
A14
A14
CS
OE
O0
O1
O7
D0
D1
•
D7
D0
D1
D0
D1
•
D7
D7
READ
WRITE
A19
A18
A17
A15
A16
74x139
HIMEN_L
SE0000_L
1G 1Y0
SE8000_L
1Y1
SF0000_L
1A 1Y2
SF8000_L
1B 1Y3
27
Improved DRAMs
Central Idea: Each read to a DRAM actually
reads a complete row of bits or word line from
the DRAM core into an array of sense amps.
A traditional asynchronous DRAM interface
then selects a small number of these bits to be
delivered to the cache/microprocessor.
All the other bits already extracted from the DRAM
cells into the sense amps are wasted.
28
14