CMPUT 329 Memory Technologies Memory classes

More documents

Recommendations

Info

Address Decoding: 16x1 DRAM 19 20 10
Internal Structure of a 64K × 1 DRAM Row decoder 256 × 256 array A0-A7 RAS_L CAS_L WE_L row address control column address Column latches, multiplexers, and demultiplexers latch, mux, and dmux control DOUT DIN 21 Two Dimensional Decoding Row and column address lines are shared by the “temporal multiplexing” technique. RAS (row address strobe) and CAS (column address strobe) signals determine what address lines specify. Access time is further reduced when memory is read sequentially. The 2D decoding method also minimizes the length of the longest wire in the decoder. 22 11
Page 1 and 2: CMPUT 329 Memory Technologies José
Page 3 and 4: Writing 1 in a Dynamic Memories bit
Page 5 and 6: Forgetful Memories bit line word li
Page 7 and 8: 0 A2 1 A1 1 A0 3-to-8 decoder 1 2 1
Page 9: HM628512 17 Internal Address Decodi
Page 13 and 14: 25 26 13
Page 15 and 16: Fast Page Mode DRAMs In a DRAM with
Page 17 and 18: An Enhanced Data Output Read Cycle

CMPUT 329 Memory Technologies Memory classes

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?