CMPUT 329 Memory Technologies Memory classes

CMPUT 329
Memory Technologies
José Nelson Amaral
1
Memory classes
Read only memory (ROM) - non-volatile
PROM
EPROM
EEPROM (flash)
Random access memory (RAM) - volatile
Static RAM (SRAM)
Dynamic RAM (DRAM)
Synchronized DRAM (SDRAM)
Double data rate (DDR) SDRAM
2
1

Static RAM Cell
3
Dynamic Memory Cell
An SRAM cell has a bi-stable latch that requires from
four to six transistors to be built.
To deliver the higher memory density required for
computer systems, a single transistor memory cell
was developed.
bit line
word line
1-bit DRAM cell
4
2

Writing 1 in a Dynamic
Memories
bit line
word line
1-bit DRAM cell
To store a 1 in this cell, a HIGH voltage is placed on
the bit line, causing the capacitor to charge through
the on transistor.
5
Writing 0 in a Dynamic
Memories
bit line
word line
1-bit DRAM cell
To store a 0 in this cell, a LOW voltage is placed on
the bit line, causing the capacitor to discharge through
the on transistor.
6
3

Destructive Reads
bit line
word line
1-bit DRAM cell
To read the DRAM cell, the bit line is precharged to
a voltage halfway between HIGH and LOW, and
then the word line is set HIGH.
Depending on the charge in the capacitor, the precharged
bit line is pulled slightly higher or lower.
A sense amplifier detects this small change and
recovers a 1 or a 0.
7
Recovering from
Destructive Reads
bit line
word line
1-bit DRAM cell
The read operation discharges the capacitor.
Therefore a read operation in a dynamic memory must
be immediately followed by a write operation of the same
value read to restore the capacitor charges.
8
4

Forgetful Memories
bit line
word line
1-bit DRAM cell
The problem with this cell is that it is not bi-stable:
only the state 0 can be kept indefinitely, when the
cell is in state 1, the charge stored in the capacitor
slowly dissipates and the data is lost.
9
Accesses to SRAM
Read An address is placed on the address inputs while
CS and OE are asserted. The latch outputs for the
selected memory locations are delivered to DOUT.
Write An address is placed on the address inputs and
a data word is placed on DIN; then CS and WE are
asserted. The latches in the selected memory
location open, and the input word is stored.
10
5

0 A2
1 A1
1 A0
3-to-8
decoder
1
2
1
0
WE_L
CS_L
OE_L
0
2
3
4
5
6
7
WR_L
IOE_L
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIN2
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIN1
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIN0
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DOUT3 DOUT2 DOUT1 DOUT0
0 A2
1 A1
1 A0
3-to-8
decoder
1
2
1
0
WE_L
CS_L
OE_L
0
2
3
4
5
6
7
WR_L
IOE_L
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DOUT3 DOUT3 DOUT3 DOUT3
6

0 A2
1 A1
1 A0
3-to-8
decoder
1
2
1
0
WE_L
CS_L
OE_L
0
2
3
4
5
6
7
WR_L
IOE_L
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DOUT3 DOUT3 DOUT3 DOUT3
0 A2
1 A1
1 A0
3-to-8
decoder
1
2
1
0
WE_L
CS_L
OE_L
0
2
3
4
5
6
7
WR_L
IOE_L
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DOUT3 DOUT3 DOUT3 DOUT3
7

SRAM with Bi-directional
Data Bus
microprocessor
WE_L
CS_L
OE_L
WR_L
IOE_L
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
DIO3 DIO2 DIO1 DIO0
15
Internal Address Decoding
The SRAM shown in the previous slides had 3 address
lines and stored 8 words, requiring a 3-to-8 internal
decoder.
Such a decoder requires eight AND gates, with
three inputs each, and three invertors.
Consider the HM628512 SRAM that has 19 address
lines and stores 512K words. What size internal
decoder this chip requires?
A 19-to-512K decoder with 524288 AND gates, each
with 19 inputs?
16
8

HM628512
17
Internal Address Decoding
To avoid such a complexity in the decoding logic,
all memories (EPROMs, SRAMs, and DRAMs) use
two-dimensional decoding which reduces the
decoder size to approximately the square root
of the number of addresses.
The memory cells are organized in a two-dimensional
array. Some address lines are used to select a row
and the others are used to select a column. The
cell selected by the whole address is at the intersection
of the row and the column.
18
9

Address Decoding: 16x1 DRAM
19
20
10

Internal Structure of a
64K × 1 DRAM
Row
decoder
256 × 256
array
A0-A7
RAS_L
CAS_L
WE_L
row
address
control
column
address
Column latches,
multiplexers,
and demultiplexers
latch, mux, and
dmux control
DOUT
DIN
21
Two Dimensional Decoding
Row and column address lines are shared by
the “temporal multiplexing” technique.
RAS (row address strobe) and CAS (column
address strobe) signals determine what address
lines specify.
Access time is further reduced when memory is
read sequentially.
The 2D decoding method also minimizes the
length of the longest wire in the decoder.
22
11

Micron MT48lC128MA2
512 Mbits
Can work as:
128 M x 4
64 M x 8
32 M x 16
Pin Assignment
Address lines: A0-A12
Data lines: DQ0 - DQ15
23
24
12

25
26
13

External Address Decoding
microprocessor
A0
A0
A1
A1
•
A19
A19
A0
27256
A0
A1
A1
•
A14
A14
CS
OE
O0
O1
O7
D0
D1
•
D7
A0
A0
A1
A1
•
A14
A14
CS
OE
27256 27256 27256
A0
A0
A0
A0
A1
A1
A1
A1
O0
O1
O7
D0
D1
•
D7
•
A14
A14
CS
OE
O0
O1
O7
D0
D1
•
D7
•
A14
A14
CS
OE
O0
O1
O7
D0
D1
•
D7
D0
D1
D0
D1
•
D7
D7
READ
WRITE
A19
A18
A17
A15
A16
74x139
HIMEN_L
SE0000_L
1G 1Y0
SE8000_L
1Y1
SF0000_L
1A 1Y2
SF8000_L
1B 1Y3
27
Improved DRAMs
Central Idea: Each read to a DRAM actually
reads a complete row of bits or word line from
the DRAM core into an array of sense amps.
A traditional asynchronous DRAM interface
then selects a small number of these bits to be
delivered to the cache/microprocessor.
All the other bits already extracted from the DRAM
cells into the sense amps are wasted.
28
14

Fast Page Mode DRAMs
In a DRAM with Fast Page Mode, a page is defined as
all memory addresses that have the same row address.
To read in fast page mode, all the steps for row access
in a standard read cycle are performed.
Then OE and CAS are switched high, but RAS remains
low.
Then the last steps for providing a new column address,
asserting CAS and OE, are performed for each new
memory location to be read.
29
Write Cycle on an Asynchronous DRAM
15

A Fast Page Mode Read Cycle on an Asynchronous DRAM
Enhanced Data Output
RAMs (EDO-RAM)
The process to read multiple locations in an EDO-RAM
is very similar to the Fast Page Mode.
The difference is that the output drivers are not disabled
when CAS goes high.
This distinction allows the data from the current read cycle
to be present at the outputs while the next cycle
begins.
As a result, faster read cycle times are allowed.
32
16

An Enhanced Data Output Read Cycle on an Asynchronous DRAM
Synchronous DRAMs
(SDRAM)
A Synchronous DRAM (SDRAM) has a clock input. It operates
in a similar fashion as the fast page mode and EDO DRAM.
However the consecutive data is output synchronously on the
falling/rising edge of the clock, instead of on command by
CAS.
How many data elements will be output (the length of
the burst) is programmable up to the maximum size of
the row.
SDRAM also uses multiple “banks” of memory to interleave
RAS/CAS activation and data transfer.
34
17

DDR SDRAM
A Double Data Rate (DDR) SDRAM is an SDRAM
that allows data transfers both on the rising and
falling edge of the clock.
Thus the effective data transfer rate of a DDR
SDRAM is two times the data transfer rate of
a standard SDRAM with the same clock frequency.
35
References
Randy H. Katz & Gaetano Borriello,
“Contemporary Logic Design”, 2/E,
Pearson / Prentice Hall, 2005. (ISBN 0-201-30857-6)
section 10.4
John F. Wakerly, "Digital Design, Principles
and Practices", 3/E, Pearson / Prentice Hall, 2001.
(ISBN 0-13-089896-1) sections 10.1-10.4
36
18