TMS320C6474 EVM Board - Spectrum Digital Support

TMS320C6474 

Mezzanine EVM Board 

Technical 

Reference 

2008 DSP Development Systems


Mezzanine EVM Board 

Technical Reference 

511225-0001 Rev. A 

November 2008 

SPECTRUM DIGITAL, INC. 

12502 Exchange Drive, Suite 440 Stafford, TX. 77477 

Tel: 281.494.4505 Fax: 281.494.5310 

sales@spectrumdigital.com www.spectrumdigital.com

IMPORTANT NOTICE 

Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any 

product or service without notice. Customers are advised to obtain the latest version of relevant 

information to verify that the data being relied on is current before placing orders. 

Spectrum Digital, Inc. warrants performance of its products and related software to current 

specifications in accordance with Spectrum Digital’s standard warranty. Testing and other quality 

control techniques are utilized to the extent deemed necessary to support this warranty. 

Please be aware that the products described herein are not intended for use in life-support 

appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for 

the product described herein to be used in other than a development environment. 

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, 

software performance, or infringement of patents or services described herein. Nor does Spectrum 

Digital warrant or represent any license, either express or implied, is granted under any patent right, 

copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any 

combination, machine, or process in which such Digital Signal Processing development products or 

services might be or are used. 

WARNING 

This equipment is intended for use in a laboratory test environment only. It generates, uses, and can 

radiate radio frequency energy and has not been tested for compliance with the limits of computing 

devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable 

protection against radio frequency interference. Operation of this equipment in other environments 

may cause interference with radio communications, in which case the user at his own expense will be 

required to take whatever measures necessary to correct this interference. 

Copyright © 2008 Spectrum Digital, Inc.

Contents 

1 Overview of the TMS320C6474 Mezzanine EVM Board . . . . . . . . . . . . . . . . . . . . . . . . 1-1 

Provides you with an overview of the TMS320C6474 Mezzanine EVM Board, key features, and 

block diagram. 

1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 

1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 

1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 

1.4 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 

1.5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 

2 Introduction to the TMS320C6474 EVM Mezzanine Board . . . . . . . . . . . . . . . . . . . . . 2-1 

Provides you with a description of the TMS320C6474 EVM Mezzanine Board, key features, and 

block diagram. 

2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 

2.2 EVM Configuration and Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . 2-3 

2.3 JTAG Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 

2.4 EVM Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 

2.5 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 

2.6 I 2 C Configuration EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 

2.6.1 EEPPROM Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 

2.6.2 C6474 Boot and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 

2.6.3 CDCL6010 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 

2.6.4 CDCE906 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 

2.7 I 2 C Device Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 

2.8 CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 

2.8.1 Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 

2.8.2 Optimal Configuration Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 

2.8.3 NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 

2.8.4 Power Main Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 

2.8.5 Power Domain Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 

2.8.6 Thermal and BOOT Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 

2.8.7 Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 

2.9 Ethernet Phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 

2.10 Serial Rapid I/O (SRIO) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 

2.11 Antenna Interface (AIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 

2.12 Micrtor Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

3 TMS320C6474 Mezzanine EVM Board Physical Specifications . . . . . . . . . . . . . . . 3-1 

Describes the physical layout of the TMS320C6474 EVM Mezzanine Board and its connectors. 

3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 

3.2 Connector Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 

3.2.1 J1, AMCC Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 

3.2.2 J2, J4, CPU2 AIFX SMA Interface Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 

3.2.3 J3, J5, CPU1 AIFX SMA Interface Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 

3.2.4 J6, J7, Optional Clock Inputs SMA’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 

3.2.5 J8, J9, Optional External FSYNC Burst SMA Inputs . . . . . . . . . . . . . . . . . . . . . . . . 3-8 

3.2.6 J10, 14 Pin TI JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 

3.2.7 J11, CPLD Programming Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 

3.2.8 J13, 60 Pin Emulation Interface for CPU1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 

3.2.9 J14, 60 Pin Emulation Interface for CPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 

3.2.10 J15 Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 

3.2.11 J17, PWR2 Converter Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 



3.2.14 J20, TPS54010PWP Converter Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 

3.2.15 J501, Embedded Emulation USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 

3.2.16 J506, +12 Volt Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 

3.2.17 LA1, Logic Analyzer 1 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 

3.2.18 LA2, Logic Analyzer 2 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 

3.2.19 P1, Optional Fanpower Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 

3.2.20 P2, Optional Fanpower Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 

3.3 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 

3.3.1 SW1, Reset Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 

3.3.2 SW2, PORz Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 

3.3.3 SW3, XWMRSTz Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 

3.3.4 SW4, CPLD Option Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 

3.3.5 SW5, Boot Mode and Configuration Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 

3.4 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 

3.4.1 JP1, CLKS0 Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 

3.4.2 JP2, CLKS1 Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 

3.4.3 JP3, User FSBYC Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 

3.4.4 JP4, CPU1 I 2 C Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 

3.4.5 JP5, CPU2 I 2 C Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 

3.4.6 JP6, Voltage Control Override CPU1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 

3.4.7 JP7, Voltage Control Override CPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 

3.4.8 JP8, SYNC Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 

3.5 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 

3.6 System LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 

A Mezzanine EVM Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 

Contains the schematics for the TMS320C6474 EVM Mezzanine Board 

B Mezzanine EVM Board Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 

Contains the mechanical information about the TMS320C6474 Mezzanine EVM Board

About This Manual 

Notational Conventions 

This document describes the board level operations of the TMS320C6474 DSP 

Mezzanine EVM Board. The board is based on the Texas Instruments 

TMS320C6474 Digital Signal Processor. 

The TMS320C6474 Mezzanine EVM Board is a table top card to allow engineers and 

software developers to evaluate certain characteristics of the TMS320C6474 DSP to 

determine if the processor meets the designers application requirements. Evaluators 

can create software to execute onboard or expand the system in a variety of ways. 

This document uses the following conventions. 

The TMS320C6474 Mezzanine Board will sometimes be referred to as the EVM, 

C6474 EVM, or TMS320C6474 EVM. 

Program listings, program examples, and interactive displays are shown in a special 

italic typeface. Here is a sample program listing. 

equations 

!rd = !strobe&rw; 

Information About Cautions 

This book may contain cautions. 

This is an example of a caution statement. 

A caution statement describes a situation that could potentially damage your software, 

or hardware, or other equipment. The information in a caution is provided for your 

protection. Please read each caution carefully. 

Related Documents 

Texas Instruments TMS320C64xx DSP CPU Reference Guide 

Texas Instruments TMS320C64xx DSP Peripherals Reference Guide

Table 1: Manual History 

Revision 

A 

Initial Release 

History

Chapter 1 

Overview of the 

TMS320C6474 Evaluation Module 

Chapter One provides an overview description of the TMS320C6474 

Evaluation Module along with the key features and a block diagram of the 

evaluation platform. 

Topic 

Page 

1.1 Key Features 1-2 

1.2 Functional Overview 1-3 

1.3 Basic Operation 1-3 

1.5 Configuration Switch Settings 1-4 

1.7 Power Supply 1-4 

1-1

Spectrum Digital, Inc 

1.1 Key Features 

The C6474 Evaluation Module (EVM) is a high performance standalone development 

platform that enables users to evaluate and develop applications for the TI C64xx DSP 

family. The EVM also serves as a hardware reference design for the TMS320C6474 

DSP. The EVM is an AMCC type double width Mezzanine board. 

The dual DSPs on the C6474 Mezzanine Board interface to on-board peripherals 

dedicated I/O pins or SRIO interface connector. The DDR2 memory is on its own 

dedicated EMIF. 

The EVM has a 100/1000 mbit Phy which is connected to the DSP’s on board EMAC. 

The board is powered by +12 volts delivered via the AMCC connector. On-board 

switching voltage regulators provide the DSP core voltage, 1.1V for I/O, 1.5V for 

RGMII, 1.8V for DDR, and 3.3V I/O supplies. The board is held in reset until these 

supplies are within operating specifications. 

Code Composer communicates with the Mezzanine Board via the mini-USB connector 

to the embedded JTAG emulator on the EVM. The Mezzanine board can also be used 

with an external emulator through the external 14 or 60 pin JTAG connectors. 

Schematics, logic equations and application notes are available to ease hardware 

development and reduce time to market. 

The key features of the of the C6474 EVM include: 

• Two (2) Texas Instruments TMS320C6474 DSPs operating at 1 Ghz. (6 cores, 

3 per device) 

• 128 Mbytes of DDR2 memory for each processor 

• 10/100/1000 MBPs multi-channel ethernet interface 

• I 2 C Serial ROM for boot loading each processor 

• 4 user accessible LEDs per processor 

• Software board configuration through registers implemented in CPLD and I 2 C ROM 

• Auto-Configured boot options and clock input selection 

• Standard AMCC expansion connectors for use as a daughter card 

• On-board JTAG emulator with USB host interface 

• Single voltage power supply (+12V) 

1-2 TMS320C6474 Mezzanine EVM Board Technical Reference


1.2 Functional Overview of the TMS320C6474 EVM 

The EVM Platform is a double wide AMCC expansion board. The board has two Texas 

Instruments C6474 DSPs running at 1 Ghz. The figure below is a block diagram of 

the TMS320C6474 EVM. 

ENET 

14 Pin 

JTAG 

DDR2 32 DSP 

VCTRL F1 

Power Supply 

DDR2 C6474 

JTAG 

F1 

SGMII 

Marvell 

PHY Altera 

CPLD Boot CFG SysCtrl 

I²C 

USB 

Embedded 

ROM 

JTAG 

AIF 

Resets 

I²C Bus 

VCTRL F2 

DDR2 C6474 

DSP 

DDR2 32 F2 

Power Supply 

60 Pin JTAG 

60 Pin JTAG 

ClkGen 

SRIO 

AIF 

Crow's Feet 

PWR 

Mezzanine 

Figure 1-1, Block Diagram, TMS320C6474 EVM 

1.3 Basic Operation 

The EVM Platform is designed to work with TI’s Code Composer Studio development 

environment and ships with a version specifically tailored to work with the board. 

Code Composer communicates with the board through the on-board JTAG emulator. 

To start, follow the instructions in the Quick Start Guide to install Code Composer. 

This process will install all of the necessary development tools, documentation and 

drivers. 

After the install is complete, follow these steps to run Code Composer. The EVM board 

must be fully connected to launch the EVM version of Code Composer. 

1) Connect the included power supply to the EVM board. 

2) Connect the EVM to your PC with a standard USB cable (also included). 

3) Launch Code Composer from its icon on your desktop. 

Detailed information about the EVM including examples and reference 

material is available on the EVM’s included compact disc. 

1-3


1.4 Configuration Switch Settings 

1.5 Power Supply 

Figure 1-2, TMS320C6474 EVM 

The configuration switch settings for the EVM platform are discussed in chapter 2. The 

EVM has one set of 8 and one set of 4 configuration switches that allow users to 

control the operational state of the DSP when it is released from reset. The 

configuration switch blocks are labeled SW4 and SW5 on the EVM board. These 

switches are located next to the reset switch. 

The EVM operates from a single +12V external power supply connected to the main 

power input (J5). Internally, the +12V input is converted into +5V, +3.3V, +2.5V, +1.8V, 

+1.1V and 2 core voltages for the DSPs using multiple voltage regulators. The core 

voltage supply incorporates smart reflex technology and is used for the DSP core 

while the +3.3V supply is used for the support circuitry and other chips on the board. 

The +2.5 volts is used to operate the Maxell ethernet Phy. The +1.1 volt supply 

operates DSP peripherals. The +1.8 volt supply is used to support DDR2 memories. 

The power connector is a 2.5mm barrel-type plug. 


Chapter 2 

Introduction to the 

TMS320C6474 EVM Mezzanine Board 

Chapter five provides a description of the TMS320C6474 Mezzanine 

EVM Board along with the key features and a block diagram of the 

circuit board. 

Topic 

Page 

2.1 Memory Map 2-2 

2.2 EVM Configuration and Configuration Switch Settings 2-3 

2.3 JTAG Overview 2-5 

2.4 EVM Power Domains 2-5 

2.5 Clock Domains 2-6 

2.6 I 2 C Configuration EEPROM 2-7 

2.6.1 EEPROM Version 2-7 

2.6.2 C6474 Boot and Configuration 2-8 

2.6.3 CDCL6010 Configuration 2-9 

2.6.4 CDCE906 Configuration 2-10 

2.7 I 2 C Device Address Mapping 2-11 

2.8 CPLD 2-12 

2.8.1 Version Register 2-12 

2.8.2 Optional Configuration Switches 2-13 

2.8.3 NMI 2-13 

2.8.4 Power Main Control 2-14 

2.8.5 Power Domain Status 2-14 

2.8.6 Thermal and BOOT Status 2-15 

2.8.7 Register 6 2-15 

2.9 Ethernet Phy 2-16 

2.10 Serial Rapid I/O (SRIO) Interfaces 2-17 

2.11 Antenna Interface (AIF) 2-18 

2.12 Mictor Expansion Connectors 2-19 

2-1


2.1 Memory Map 

The C64xx family of DSPs has a large byte addressable address space. Program 

code and data can be placed anywhere in the unified address space. Addresses are 

always 32-bits wide. 

The memory map shows the address space of a C6474 EVM. By default, the internal 

memory sits at the lower section of the address space. Portions of memory can be 

remapped in software as L2 cache rather than fixed RAM. 

Note that each device has 3 cores and can access the on chip peripherals. 

Address 

0x00000000 

0x00800000 

0x00900000 

0x80000000 

0xA0000000 

0xB0000000 

L2 SRAM 

Reserved Space 

or 

Peripheral Regs 

or 

L2 SRAM 

DDR2 RAM 

AIF Data 

Reserved 

0xF0000000 

Figure 2-1, Memory Map, C6474 Mezzanine EVM Board 



2.2 EVM Configuration and Configuration Switch Settings 

Note 

Both C6474 devices operate in the same 

boot mode configuration on the EVM. 

The C6474 EVM has two I 2 C configuration EEPROMs and two configuration switches, 

SW4, and SW5. 

The two I 2 C configuration EEPROMs known as factory I 2 C configuration EEPROM 

and user I 2 C configuration EEPROM. 

The factory I 2 C configuration EEPROM is write protected and can not be changed, the 

user I 2 C configuration EEPROM is mapped to C6474 CPU1 and can be over written. 

At RESET the embedded control processor samples the configuration switches SW4, 

and SW5 and determines if the factory I 2 C configuration EEPROM in conjunction with 

configuration switches are used to configure the on board C6474 devices, or if the 

user I 2 C configuration EEPROM in conjunction with configuration switches configures 

the EVM. 

Switch SW5 controls general boot parameters, whereas SW4 determines general 

control parameters such as if the board is used in stand alone mode or which I 2 C 

configuration EEPROM is used. 

If SW4 ROMSEL is ON the user configuration EEPROM is selected. If the SW4 

ROMSEL is OFF the factory configuration switch is selected. 

The user I 2 C configuration EEPROM as shipped, contains the exact same defaults as 

the factory I 2 C configuration EEPROM. The factory shipped configuration uses the 

factory configuration EEPROM with the defaults over written via SW5, 

(OVERRIDE=OFF). The exact same configuration could be duplicated by enabling the 

user I 2 C configuration on SW4, ROM_SEL switch. 

Anytime a parameter on SW5 is selected the override position MUST be selected to the 

OFF position for the parameters to be active at boot. Furthermore when the 

OVERRIDE position is active all the configuration switches on SW5 must be set 

appropriately as they are all over written at boot. 

For more detailed information on the available configurations for SW4 and SW5 are 

defined in chapter 3, sections 3.3.4 and 3.3.5. 

2-3


The following tables describe switches SW4 and SW5. 

Table 1: SW4 Configuration Switch 

SW4 Switch 

Position 

Description 

Function 

1 AMCC/Standalone 

Select 

2 ROM_SEL 

Select 

3 DDRSLRATE 

Select 

4 Use Mode 

select 

* Default position as shipped 

Off = Operating in AMCC mode 

On =Operating in stand alone mode * 

Off =Select factory I 2 C configuration default EEPROM * 

On =Select the user I 2 C configuration EEPROM 

Off =DSP DDRSLRATE is 1 (full memory speed) * 

On =DSP DDRSLRATE is 0 (reduce slew rate by 33%) 

Off = Factory test mode 

On =Standard Mode * 

Note: For SW4 ON position is a logic low or “0”, OFF position is a logic high or “1” 

When in AMCC mode the AMCC_ENABLEn signal from the AMCC connector acts as 

an additional power on reset. When the AMCC_ENABLEn signal is high both the PORz 

and XWMRSTz resets to the DSP are asserted along with boot configuration. If the 

AMCC_ENABLEn signal is low and the boot configuration process is complete then 

PORz and XWMRSTz are released. 

Table 2: SW5 Configuration Switch 

SW5 Switch 

Position 

Description Function Default * 

1 BOOTM0 DSP Boot Mode 0 OFF 

2 BOOTM1 DSP Boot Mode 1 ON 



5 LENDIAN DSP LENDIAN OFF 

6 L2CONFIG DSP L2CONFIG OFF 

7 CORECLK DSP CORECLK OFF 

8 OVERRIDE Off = use boot mode setting from switches ON 

On = use boot mode setting from EEPROM 





2.3 JTAG Overview 

The EVM incorporates Spectrum Digital’s embedded JTAG emulation, a 14 pin JTAG 

interface and 2 - 60 pin TI JTAG/Trace headers. A CPLD is used for routing the various 

JTAG paths so that no user switches or hardware configuration is required. 

The board supports both C6474 devices in the JTAG scan chain when used with the 

on-board emulation or 14 pin JTAG header J10. When the 60 pin JTAG header is used 

only one C6474 device is connected to that header. There is a 60 pin JTAG header 

for each cpu. If only one 60 pin JTAG header is used, the other C6474 device is 

accessible via its 14 pin or 60 pin JTAG emulation connector. 

2.4 EVM Power Domains 

The EVM incorporates a power domain controller via the on board CPLD and on board 

emulation/configuration processor. The board is powered by 12 volt input supplied by 

connector J506 or the AMC interface connector. This 12 volts is down converted to +5 

volts to operate the on-board 3.3 volt, 2,5 volt, 1.8 volt, 1.1 volt and 2 DSP core 

regulators. 

At power up, the 3.3 volt domain EVM_3V3, the 2.5 volt domain EMU_2V5 and 1.8 volt 

domain EVM_1V8 are enabled. The configuration processor then enables the 

EVM_2V5 domain, the F_DVDD_18 domain, the F_VDDD_11 domain, and the 

F1_CVDD domain and the F2_CVDD domain. All these domains are monitored by 

separate power monitors. As the domains are enabled the power feedback LEDS from 

the CPLD are illuminated. When the power domains are present the configuration 

processor then enables the clock domains, sets the boot mode parameters and then 

releases the reset and power on reset signals to the C6474 devices. If the 

configuration is successful the RED configuration LED is turned off. 

This configuration is all handled automatically via the CPLD and configuration 

processor. 

2-5


2.5 Clock Domains 

The EVM incorporates a wide variety of clocks to the C6474 devices. These clocks 

are configured automatically during the power up configuration sequence. The figure 

below illustrates the clocking for the CPU #1 on the EVM module. CPU #2 uses a 

similar technique. 

50 Mhz 

U18 

U3 

66 Mhz 

U4 

SN65LVDS31 

30.72 Mhz 

U1 

CDCE906 

U2 

CDCL6010 

F1_ALTCORE_CLKP 

F1_ALTCORE_CLKN 

F1_DDRCLKP 

F1_DDRCLKN 

F1_SYSCLKP 

F1_SYSCLKN 

F1_SYNC_CLKP 

F1_SYNC_CLKN 

} 

} 

} 

} 

C6474 

CPU1 

CPU 

50 Mhz 

Clock 

DDR 

Clock 

System 

Clock 

66 Mhz 

61.44 Mhz 

SYNC_CLOCKS 

30.72 Mhz 

U6 

125 Mhz 

U5 

125 Mhz 

SN65LVDS104 

Figure 2-2, C6474 EVM Clock Domains 

} 

SRIO 

125 Mhz 

Clocks 



2.6 I 2 C Boot Configuration EEPROM 

The C6474 EVM supports 2 boot configuration EEPROMS, one is programmed with 

factory defaults which the user cannot modify. The other is the user configuration 

EEPROM that can be used to override factory defaults. The user configuration 

EEPROM is programmed with factory defaults for production test purposes. The 

EEPROMS are broken into 5 configuration sections and occupy either 1 or 2 32-byte 

blocks of EEPROM. The following tables describe the contents of the EEPROMs. 

Table 3: I 2 C Boot Configuration EEPROM 

EEPROM 

Address 

Name 

Function 

0x00 - 0x1F EEPROM Version EEPROM Version string 

0x20 - 0x3F 

C6474 Boot and 

Configuration 

DSP Boot mode 

configuration settings 

0x60 - 0x7F CDCL6010 Configuration CDCL6010 Settings 

0x80 - 0xBF CDCE906 Configuration CDCE906 Settings 

0xC0 - 0xFF 

Unused 

During the boot process the EEPROM is read section by section and used to configure 

the C6474 EVM. The firmware makes the following simple checks before configuring 

the C6474 EVM: 

- Verifies factory EEPROM exists. If not then configuration aborts. 

- Verifies that factory EEPROM version and firmware version match. 

If not then configuration aborts. 

- Verifies that user EEPROM exists. If user EEPROM is selected as the 

configuration source and does not exist then configuration aborts. 

- Verifies that CDCE906 exists and has a valid EEPROM section header, if 

true then configure the CDCE906. 

- Verifies that CDCE906 exists and has a valid EEPROM section header, if 

true then configure the CDCE906. 

2.6.1 EEPROM Version 

The EEPROM version string occupies 1 32-byte block of EEPROM. The version string 

as defined as "C6474 V00.00.01" for Major.Minor.Build format. During the boot 

sequence the factory programmed EEPROM version string is read and compared to 

that of the embedded firmware. If they do not match then the boot sequence is 

aborted. 

2-7


2.6.2 C6474 Boot and Configuration 

The C6474 Boot and Configuration section occupies 3 bytes with the following 

definitions: 

Table 4: Byte 0: Default 0xF0 

Bit # Name Function 

0 BOOTM0 DSP BOOTM0 




4 LENDIAN DSP LENDIAN 

5 L2CONFIG DSP L2CONFIG 

6 CORECLK DSP CORECLK 

7 DDRSLRATE DSP DDRSLRATE 

Table 5: Byte 1: Default 0x21 


3 - 0 DEVNUM - F1 DSP F1 Device Number 

7 - 4 DEVNUM - F2 DSP F2 Device Number 

Table 6: Byte 2: Default 0x00 


0 FRAME_SYNC_SELECT 0 - Select GPIO9 (default) 

1 - Select EXT_CPLD_FSYNC_BURST 

1 FRAME_SYNC_DISABLE 0 - Enable frame clocks (default) 

1 - disable frame clocks 

2 - 7 Not used 



2.6.3 CDCL6010 Configuration 

The CDCL6010 is an 11 output clock multiplier, distributor, jitter cleaner and buffer. This 

programmable device generates 10 clock signals. These clock signals are defined in 

the table below. 

Table 7: CDCL6010 Generated Clocks 

Pin # Pin Name Clock Signal Generated 

6 YP0 F1.SYSCLK.P 

7 YPN F1.SYSCLK.N 

9 YP1 F2.SYSCLK.P 

10 YN1 F2.SYSCLK.N 

27 YP5 F1.FSYNC_CLKP 

28 YN5 F1.FSYNC_CLKN 

30 YP6 F2.FSYNC_CLKP 

31 YN6 F2.FSYNC_CLKN 

33 YP7 CPLD_FSYNC_CLKP 

34 YN7 CPLD_FSYNC_CLKN 

The CDCL6010 Configuration section occupies 32 bytes. The section ID is 3. During 

boot process if the CDCL6010 section ID is read as 3 and the number of address/data 

pairs is greater then 0 then the CDCL6010 will be configured. 

Table 8: CDCL6010 - Base Address - 0x60 

Byte # Value Function 

0 0x03 Section ID 

1 N Number of Address: Data pairs 

2 Address 1 CDCL6010 - Register address 

3 Data 1 CDCL6010 - Register data 

4 - 31 Reserved 

2-9


2.6.4 CDCE906 Configuration 

The CDCE906 is a programmable 3-PLL 6 output clock synthesizer. This device 

generates 6 clock signals on the EVM. Two of the six clocks are fed into 2 sets of inputs 

to U3, SN65LVD31 which generates 4 differential clock domains. The clock signals 

generated by the CDCE906 are defined in the table below. 

Table 9: CDCE906 Generated Clocks 


11 Y0 CLK 30.72MHZ 

12 Y1 CPLD_CLK 

15 Y2 Input to 1A U3, SN65LVDS31 




Of the 2 sets of 2 inputs (4 total) to U3, each of them have an option to use the 

CDCE906 output or fixed oscillators as inputs. currently the EVM uses fixed oscillators. 

The clock signals generated by the SN65LVD31 are defined in the table below. 

Table 10: SN65LVD31 Generated Clocks 


2 1Y F1_ALTCORE_CLKP 

3 1Z F1_ALTCORE_CLKN 

5 2Z F1_DDRCLK_N 

6 2Y F1_DDRCLK_P 

10 3Y F2_ALTCORE_CLKP 

11 3Z F2_ALTCORE_CLKN 

13 4Z F2_DDRCLK_N 

14 4Y F2_DDRCLK_P 

2-10 TMS320C6474 Mezzanine EVM Board Technical


The CDCE906 Configuration section occupies 64 bytes. The section ID is 4. During 

boot process if the CDE906 section ID is read as 4 and the number of address/data 

pairs is greater then 0 then the CDE906 will be configured. 

Table 11: CDCE906 - Base Address - 0x80 

Byte # Value Function 

0 0x04 Section ID 

1 N Number of Address: Data pairs 

2 Address 1 CDC906 - Register address 

3 Data 1 CDC906 - Register data 

4 - 31 Reserved 

2.7 I 2 C Device Address Mapping 

The following table specifies the I 2 C device mappings for the C6474 EVM: 

Table 12: I 2 C Device Address Mapping 

Device Device Address Reference 

CPU1 BOOT EEPROM 0b1010000_rw 0xA0 U23 

CPU1 FACTORY CONFIG EEPROM 0b1010001_rw 0xA2 U13 

CPU1 USER CONFIG EEPROM 0b1010010_rw 0xA4 U12 

CPU1 CDCL6010 0b1101000_rw 0xD0 U2 

F1 CDCE906 0b1101001_rw 0xD1 U1 

CPU2 BOOT EEPROM 0b1010000_rw 0xA0 U36 

2-11


2.8 CPLD 

NOTE 

This is to be used at the factory only. 

The CPLD registers on the C6474 EVM are accessed from the embedded emulation 

processor. On EVM power up both C6474 devices are powered down. Once the 

embedded emulation processor has booted it will then configure the C6474 boot 

modes and configuration pins, sequence the power supplies and then release the 

C6474 resets. There are three boot mode options on the C6474: 

- Factory Default Mode: Boot mode options are configured from factory 

default I 2 C configuration EEPROM. 

- User Boot Mode: Boot mode options are configured from user I 2 C 

configuration EEPROM. 

- Switch Mode: Boot mode and selected configuration options driven from 

boot/configuration switches. 

The following tables describe the contends of the CPLD registers. 

2.8.1 Version Register (read/write) 

The default CPLD version is 0x21. 

Table 13: Version Register 

Bit # 

Name 

0 VER - Minor:0 




4 VER - Major:0 






2.8.2 Optional Configuration Switches (read/write) 

Bits 0-3 map to SW4. The DSP_CFG0_ADDR and DSP_CFG1_ADDR are used 

during the boot configuration process to address the boot configuration shadow 

registers. The boot modes, boot configuration and device numbers are read from one 

of the I 2 C EEPROMS and written into 3 shadow configuration registers. The shadow 

registers are mapped to the same address as the VERSION register. 

Table 14: Optional configuration Switches 


0 SW_STANDALONE 0 : Operating in stand alone mode 

1 : Operating in AMCC mode 

1 SW_ROM_SEL 0 : Use settings from factory default EEPROM 

1 : Use settings from user config EEPROM 

2 DDRSLRATE Switch DDRSLRATE Select 

3 SW_FACTORY_TEST Internal use for Emulation development 

4 DSP_CFG0_ADDR DSP Config shadow register address 0 

5 DSP_CFG1_ADDR DSP Config shadow register address 1 

6 Reserved 

7 Reserved 

2.8.3 NMI (read/write) 

Table 15: NMI 


0 F1 - NMI0 F1 NMI0 Pin 






6 ENET_RESETn Drives ENET_RESETn Pin 

7 Not used 

2-13


2.8.4 Power Main Control (read/write) 

Default power configuration is for all supplies except for the 2.5v to be off on startup 

and the DSP resets forced to reset. The 2.5V supply must be active as it is shared by 

the embedded emulation block. 

Table 16: Power Main Control 


0 EN_DUT_2V5 Enable 2.5 volt supply 

1 EN_DUT_1V2 Enable 1.1/1.2 volt supply 



4 EN_F1_CORE Enable F1 core supply 

5 EN_F2_CORE Enable F2 core supply 

6 DSP_RELEASE 1 : Release DSP reset 

0 : Force DSP reset 

7 I 2 C_WP 

2.8.5 Power Domain Status (read only) 

This read only register provides the status of the various power levels. 

Table 17: Power Domain Status 


0 STAT_2V5 2.5 volt power good 




4 STAT_F1_CORE F1 power good 

5 STAT_F2_CORE F2 power good 

6 F1_RSTAT F1 Reset status 

7 F2_RSTAT F2 Reset status 



2.8.6 Thermal and BOOT Status (read only) 

Table 18: Thermal and BOOT Status 


0 F1_ALERT1Z F1 TMP411 ALERT1Z 

1 F1_CRIT1Z F1 TMP411 CRIT1Z 

2 F1_BOOT_PIN_RELEASE 0 : Boot mode pins are active to F1 

1 : Boot mode pins are high-Z to F1 

3 F2_ALERT1Z F2 TMP411 ALERT1Z 

4 F2_CRIT1Z F2 TMP411 CRIT1Z 

5 F2_BOOT_PIN_RELEASE 0 : Boot mode pins are active to F2 

1 : Boot mode pins are high-Z to F2 

6 Reserved 

7 AMCC_ENABLE 0 : AMCC enabled 

1 : AMCC disabled 

2.8.7 Register 6 

This register is reserved for future use. 

Table 19: Register 6 


0 Not used Reserved 








2-15


2.8.8 BOOT Mode Switches (read only) 

Bits 0 - 7 of this register are mapped to switch SW5. 

Table 20: Boot Mode Switches 


0 SW_MODE0 Switch Boot Mode 0 




4 SW_LENDIAN Switch LENDIAN Select 

5 SW_L2CONFIG Switch L2CONFIG Select 

6 SW_CORECLK Switch CORECLK Select 

7 SW_OVERRIDE 1 = use boot mode setting from switches 

0 = user boot mode setting from EEPROM 

2.9 Ethernet Phy 

The C6474 EVM incorporates a multi-port Marvell 88E6122 ethernet switch. The 

C6474 (U17) is the master device which configures this switch via the MDIO interface. 

Both C6474 devices have access to this switch as shown in the figure below. 

AMC CONNECTOR 

U17 

C6474 

Device #1 

SGMII 

MDIO 

Port6 

MDIO 

Port4 

Port1 

RJ-45 

CONN 

MARVELL 

88E6122 

Optional 

U18 

C6474 

Device #2 

SGMII 

Port5 

SPI 

ROM 

Figure 2-3, C6474 Ethernet Logic 



2.10 Serial Rapid I/O (SRIO) Interfaces 

The C6474 EVM uses Serial Rapid I/O to communicate between the 2 CPU devices 

and the AMC connector. This versatile high speed interface allows the user to 

effectively communicate between on board and off board systems. The figure below 

illustrates the as shipped configuration of the SRIO. 

AMC CONNECTOR 

PORT 4 

PORT 8 

PORT 9 PORT 5 

RX0_P 

RX0_P 

PORT 0 

TO AMC 

CONN 

RX0_N 

TX0_P 

0 

0 

RX0_N 

TX0_P 

PORT 0 

TO AMC 

CONN 

U17 

C6474 

DEV NUM = 1 

TX0_N 

RX1_P 

0 

0 

TX0_N 

RX1_P 

U30 

C6474 

DEV NUM = 2 

PORT 1 

TO C6474 

U30 

RX1_N 

TX1_P 

0 

0 

RX1_N 

TX1_P 

PORT 1 

TO C6474 

U17 

TX1_N 

0 

0 

TX1_N 

OPTIONAL PATH VIA CROWS FOOT 

PATH AS SHIPPED 

0 

CROWS FOOT 

3 WAY FOOTPRINT 

Figure 2-4, C6474 EVM SRIO Port Routing 

2-17


2.11 Antenna Interface (AIF) 

The antenna interface uses high speed serial interface to communicate between the 

two on board C6474 devices and external interfaces. Port 0 on the EVM supports one 

incoming stream and one outgoing stream via DSP interconnection. Port 1 supports 

direct full DSP to DSP interconnection. Ports 2-5 default configuration supports 1 full 

link to the AMC connector (port 5) and 3 full DSP to DSP links (ports 2-4). The figure 

below illustrates the antenna configuration on the C6474 EVM. 

PORT 0 

TX0_P 

TX0_N 

RX0_P 

RX0_N 

U17 

C6474 

DEV NUM = 1 

RX0_P 

RX0_N 

TX0_P 

TX0_N 

PORT 0 

U30 

C6474 

DEV NUM = 2 

TX1_P 

RX1_P 

PORT 1 

TX1_N 

RX1_P 

RX1_N 

TX1_P 

PORT 1 

RX1_N 

TX1_N 

AMC CONNECTOR 

TX_P 

RX_P 

PORTs 

2,3,4,5 

TX_N 

RX_N 

PORTs 

2,3,4,5 

RX_P 

TX_P 

U17 

C6474 

DEV NUM = 1 

RX_N 

TX_N 

U30 

C6474 

DEV NUM = 2 

Figure 2-5, C6474 EVM Antenna Interface 



2.12 Mictor Connectors 

The C6474 EVM provides 2 Mictor connectors (LA0 and LA1) for expansion interfaces 

for Timer 0/1 and GPIO[15:10] pins for each processor. Furthermore McASP1 on both 

processors are available on these Mictors. McASP0 provides a direct DSP to DSP 

connection. All the signals present on the Mictor connectors are described in sections 

3.2.17 and 3.2.18 of chapter 3. The figure below illustrates a brief description of the 

Mictor connector interface on the C6474 EVM. 

GPIO15:10 

C6474 U17 

TIMER0/1 

McBSP1 

McBSP0 

McBSP0 

LA0 

LA1 

C6474 U30 

McBSP1 

TIMER0/1 

GPIO15:10 

Figure 2-6, C6474 Mictor Connectors 

2-19



Chapter 3 

Physical Description 

This chapter describes the physical layout of the TMS320C6474 

Mezzanine Board and its connectors. 

Topic 

Page 

3.1 Board Layout 3-3 

3.2 Connector Index 3-5 

3.2.1 J1, AMCC Interface Connector 3-5 

3.2.2 J2, J4, CPU2 AIFX SMA Interface Connectors 3-8 

3.2.3 J3, J5, CPU1 AIFX SMA Interface Connectors 3-8 

3.2.4 J6, J7, Optional Clock Inputs SMA’s 3-8 

3.2.5 J8, J9, Optional External FSYNC Burst SMA Inputs 3-8 

3.2.6 J10, 14 Pin TI JTAG Interface 3-9 

3.2.7 J11, CPLD Programming Header 3-10 

3.2.8 J13, 60 Pin Emulation Interface for CPU1 3-10 

3.2.9 J14, 60 Pin Emulation Interface for CPU2 3-11 

3.2.10 J15, Ethernet Connector 3-12 

3.2.11 J17, PWR2 Converter Interface 3-12 



3.2.14 J20, TPS54010PWP Converter Interface 3-14 

3.2.15 J501, Embedded Emulation USB Connector 3-14 

3.2.16 J506, +12 Volt Input 3-14 

3.2.17 LA1, Logic Analyzer 1 Connector 3-15 

3.2.18 LA2, Logic Analyzer 2 Connector 3-16 

3.2.19 P1, Optional Fanpower Connector 3-16 

3.2.20 P2, Optional Fanpower Connector 3-16 

3-1


Topic 

Page 

3.3 Switches 3-17 

3.3.1 SW1, Reset Pushbutton 3-17 

3.3.2 SW2, PORz Pushbutton 3-17 

3.3.3 SW3, XWMRSTz Pushbutton 3-18 

3.3.4 SW4, CPLD Option Switch 3-18 

3.3.5 SW5, Boot Mode and Configuration Switch 3-19 

3.4 Jumpers 3-21 

3.4.1 JP1, CLKS0 Header 3-21 

3.4.2 JP2, CLKS1 Header 3-22 

3.4.3 JP3, User FSYNC Inputs 3-23 

3.4.4 JP4, CPU1 I 2 C Header 3-24 

3.4.5 JP5, CPU2 I 2 C Header 3-24 

3.4.6 JP6, Voltage Control Override CPU1 3-15 

3.4.7 JP7, Voltage Control Override CPU2 3-27 

3.4.8 JP8, SYNC Burst 3-28 

3.5 Test Points 3-29 

3.6 System LEDs 3-31 



3.1 Board Layout 

The C6474 Mezzanine Board is a 7.107 x 5.848 inch (180.52 x 148.54 mm.) 

multi-layer board which is powered through connector J506. Figure 3-1 shows the 

layout of the C6474 Mezzanine Board. 

P1 

JP4 

J13 

J4 

J2 

JP1 

JP2 

JP6 

DS10-13 

DS2 

J1 

J8 

J9 

J15 

DS501 

J501 

J10 

J7 

J6 

J11 

JP3 

J506 

SW4 

SW5 

SW1 

SW2 

SW3 

P2 

LA2 J5 JP5 J14 J3 

LA1 

JP7 

DS20-23 

DS3 

DS4-9 

JP8 

Figure 3-1, TMS320C6474 Mezzanine Board, Top Side 

3-3


J18 

J19 

J17 

J20 

Figure 3-2, TMS320C6474 Mezzanine Board, Bottom Side 



3.2 Connector Index 

The TMS320C6474 Mezzanine Board has several connectors which provide the user 

access to the various signals on the board. 

* Must disable on board logic to use this feature 

3.2.1 J1, AMCC Interface Connector 

Table 1: TMS320C6474 Mezzanine Board Connectors 

Connector # Pins Function 

J1 

AMC Interface 

J2 SMA CPU 1 AIFTXN0 Output 

J4 SMA CPU 1 AIFTXP0 Output 

J3 SMA CPU 2 AIFTXN0 Input 

J5 SMA CPU 2 AIFTXP0 Input 

J6 SMA * Alternate Input CLK To CDCL60IO Positive 

J7 SMA * Alternate Input CLK To CDCL60IO Negative 

J8 SMA External FYSNC Burst Input Positive 

J9 SMA External FYSNC Burst Input Negative 

J10 14 TI JTAG (+3.3 Volt Compatible) 

J11 10 CPLD Programming header 

J13 60 CPU 1 Trace Interface 

J14 60 CPU 2 Trace Interface 

J15 

Ethernet Interface 

J17 6 Socket for PW2 Supply 



J20 6 Socket For Spare Supply 

J501 

USB Connection to Embedded JTAG controller 

J506 

+12 Volt Input 

LA1 

CPU 1, CPU2 McBSP Expansion 

LA2 

CPU 1, CPU2 Timer, GPIO Expansion 

P1 Fan Connector for CPU 1 

P2 Fan Connector for CPU 2 

The J1 card edge connector plugs into the J1 connector on the DSK circuit board. 

This connector provides a high speed Serial Rapid I/O to the DSK board. This 

connector has 170 pins. Pin 1 is across from pin 170, and pin 85 is across from pin 

86.The signals on this connector are shown in the tables below. 

3-5


Table 2: J1, AMCC Connector, Pins 1-42, 170-129 

Pin Signal Description Pin Signal Description 

1 GND Ground 170 GND Ground 

2 +12V 12 Volt Power 169 NC Reserved 

3 PS1 AMC_PS1 168 NC Reserved 

4 ALT +3.3V Not Used 167 NC Reserved 

5 GND Ground 166 NC Reserved 

6 165 NC Reserved 


8 163 NC Reserved 

9 +12V 12 Volt Power 162 NC Reserved 


11 160 NC 

12 159 NC 


14 157 SRIO Channel 19 TXMT+ 

15 156 SRIO Channel 19 TXMT- 


17 154 SRIO Channel 19 RCV+ 

18 +12V 12 Volt Power 153 SRIO Channel 19 RCV- 



21 150 SRIO Channel 198TXMT- 



24 147 SRIO Channel 18 RCV- 



27 +12V 12 Volt Power 144 SRIO Channel 17 TXMT- 






33 138 SRIO Channel 16 TXMT- 






39 132 SRIO Channel 165TXMT- 


41 ENABLE AMC ENABLE 130 SRIO Channel 15 RCV+ 




Table 3: J1, AMCC Connector, Pins 43-128-86 

Pin Signal Description Pin Signal Description 


44 DSPB.RIOTXP0 SRIO Channel 0 TXMT+ 127 SRIO Channel 14 TXMT+ 

45 DSPB.RIOTXN0 SRIO Channel 0 TXMT- 126 SRIO Channel 14 TXMT- 


47 DSPB.RIORXP0 SRIO Channel 0 RCV+ 124 SRIO Channel 14 RCV+ 

48 DSPB.RIORXP0 SRIO Channel 0 RCV- 123 SRIO Channel 14 RCV- 


50 DSPB.RIOTXP1 SRIO Channel 1 TXMT+ 121 SRIO Channel 13 TXMT+ 

51 DSPB.RIOTXN1 SRIO Channel 1 TXMT- 120 SRIO Channel 13 TXMT- 


53 DSPB.RIORXP1 SRIO Channel 1 RCV+ 118 SRIO Channel 13 RCV+ 

54 DSPB.RIORXN1 SRIO Channel 1 RCV- 117 SRIO Channel 13 RCV- 


56 NC I 2 C Clock 115 SRIO Channel 12 TXMT+ 

57 +12V 12 Volt Power 114 SRIO Channel 12 TXMT- 


59 NC SRIO Channel 2 TXMT+ 112 SRIO Channel 12 RCV+ 

60 NC SRIO Channel 2 TXMT+ 111 SRIO Channel 12 RCV- 


62 NC SRIO Channel 2 RCV+ 109 NC 

63 NC SRIO Channel 2 RCV- 108 NC 


65 NC SRIO Channel 3 TXMT+ 106 NC 

66 NC SRIO Channel 3 TXMT- 105 NC 


68 NC SRIO Channel 3 RCV+ 103 NC 

69 NC SRIO Channel 3 RCV- 102 NC 


71 NC I 2 C Data 100 NC 

72 +12V 12 Volt Power 99 NC 


74 NC 97 SRIO Channel 9 TXMT+ 

75 NC 96 SRIO Channel 9 TXMT- 


77 NC 94 SRIO Channel 9 RCV+ 

78 NC 93 SRIO Channel 9 RCV- 


80 NC 91 SRIO Channel 8 TXMT+ 

81 NC 90 SRIO Channel 8 TXMT- 


83 PST PS0 AMC Present0 88 SRIO Channel 8 RCV+ 



3-7


3.2.2 J2, J4 CPU2 AIFTX SMA Interface Connectors 

Connectors J2 and J4 provide an optional SMA connection to CPU2. These SMA’s 

connect to the CPU2 AIFTXN0 and AIFTXP0 outputs respectively. 

3.2.3 J3, J5, CPU1 AIFRX SMA Interface Connectors 

Connectors J3 and J5 provide an optional SMA connection to CPU1. These SMA’s 

connect to the CPU1 AIFRXN0 and AIFRXP0 inputs respectively. 

3.2.4 J6,J7, Optional Clock Input SMA’s 

Connectors J6 and J7 provide an optional SMA connection to the CDCL6010 clock 

generator. The onboard generator must be disabled to use these inputs. This generator 

is used to provide the sysclk and fsync clocks to CPU1 and CPU2. J6 is the positive 

differential input for this alternate clock source and J7 is the negative differential input 

for this alternate clock source. 

3.2.5 J8, J9, Optional External FSYNC Burst SMA Inputs 

Connectors J8 and J9 provide an optional SMA connection to generate fsync bursts to 

CPU1 and CPU2. J8 is the positive differential input, J9 is the negative differential 

input. These inputs generate a pulse to the onboard CPLD which generates burst 

pulses to the corresponding CPU inputs. 



3.2.6 J10, 14 Pin TI JTAG Interface 

J10 is a standard TI 14 pin JTAG connector. The onboard CPLD multiplexes this 

interface with the onboard emulation logic and the 60 pin interface connectors for each 

CPU. When an emulator is plugged into J10 both CPU1 and CPU2 are in the scan 

chain unless one of the 60 pin interface connectors is also plugged in. The CPLD 

provides 3.3 Volt to 1.8 Volt conversion on this interface so any 3.3Volt compatible 

emulator can be used to interface to the C6474 devices. Note, that when an emulator is 

plugged into this connector the onboard emulation is disabled. The pinout for the 

connector is shown in the figure below. 

TMS 

TDI 

PD (+3.3V) 

TDO 

TCK-RET 

TCK 

EMU0 

1 2 

3 4 

5 6 

7 8 

9 10 

11 12 

13 14 

TRST- 

GND 

no pin (key) 

GND 

GND 

GND 

EMU1 

Header Dimensions 

Pin-to-Pin spacing, 0.100 in. (X,Y) 

Pin width, 0.025-in. square post 

Pin length, 0.235-in. nominal 

Figure 3-2, J10, 14 Pin JTAG Interface 

The signal names for each pin are shown in the table below. 

Table 4: J10, 14 Pin JTAG Interface 

Pin # 

Signal Name 

1 TMS 

2 TRST- 

3 TDI 

4 GND 

5 PD 

6 no pin 

7 TDO 

8 GND 

9 TCK-RET 

10 GND 

11 TCK 

12 GND 

13 EMU0 

14 EMU1 

3-9


3.2.7 J11, CPLD Programming Header 

J11 is used in the factory to program the onboard CPLD. It is not intended to be used 

under normal operation. 

3.2.8 J13, 60 Pin Emulation Interface for CPU1 

The 60 pin emulation connector for CPU1 is for advanced emulation capability. The 

signals on this connector are 4 columns by 15 rows as shown in the table below 

Row # 

Table 5: J13, 60 Pin Emulation Connector 

Column A 

Signal Name 

Column B 

Signal Name 

Column C 

Signal Name 

Column D 

Signal Name 

1 Ground IDO ID2 Ground 

2 Ground TMS EMU18 Ground 

3 Ground EMU17 TRSTn Ground 

4 Ground TDI EMU16 Ground 

5 Ground EMU14 EMU15 Ground 


7 Ground TDO EMU11 Ground 

8 TYPE0 TVD TCLKRTN TYPE1 




12 Ground TCLK EMU4 Ground 



15 Ground ID1 ID3 Ground 



3.2.9 J14, 60 Pin Emulation Interface for CPU2 

The 60 pin emulation connector for CPU2 is for advanced emulation capability. The 

signals on this connector are 4 columns by 15 rows as shown in the table below 

Row # 

Table 6: J13, 60 Pin Emulation Connector 

Column A 

Signal Name 

Column B 

Signal Name 

Column C 

Signal Name 

Column D 

Signal Name 

1 Ground IDO ID2 Ground 

2 Ground TMS EMU18 Ground 

3 Ground EMU17 TRSTn Ground 

4 Ground TDI EMU16 Ground 



7 Ground TDO EMU11 Ground 

8 TYPE0 TVD TCLKRTN TYPE1 




12 Ground TCLK EMU4 Ground 



15 Ground ID1 ID3 Ground 

3-11


3.2.10 J15, Ethernet Connector 

J15 is an integrated 1 gigabit Ethernet interface connector. It is driven from the 

88E6122Marvell Phy P1 port. The output connections are shown in the table below. 

Table 7: J15, Ethernet Connector Pin Out 

Pin # Signal Name 

1 TX1+ 

2 TX1- 

3 TX2+ 

4 TX3+ 

5 TX3- 

6 TX2- 

7 TX4+ 

8 TX4- 

3.2.11 J17, PWR2 Converter Interface 

Connector J17 provides the interface for output of the PWR2 DC-DC converter that 

generates +1.8 volts. The signals on this connector are shown in the table below. 

Table 8: J17, PWR2 Converter Interface 


1 F_DVDD_18 

2 F_DVDD_18 

3 GND 

4 GND 

5 GND 

6 F_DVDD_18_MON 





generates +1.1 volts. The signals on this connector are shown in the table below. 



1 F_DVDD_11 

2 F_DVDD_11 

3 GND 

4 GND 

5 GND 




generates the F1_CVDD voltage. The signals on this connector are shown in the table 

below. 



1 F1_CVDD 

2 F1_CVDD 

3 GND 

4 GND 

5 GND 

6 F1_CVDD_MON 

3-13


3.2.14 J20, TPS54010PWP Converter Interface 

Connector J20 provides the interface for output of the TPS54010PWP DC-DC 

converter that generates the F2_CVDD voltage. The signals on this connector are 

shown in the table below. 

Table 11: J17, TPS54010WP Converter Interface 


1 F2_CVDD 

2 F2_CVDD 

3 GND 

4 GND 

5 GND 

6 F2_CVDD_MON 

3.2.15 J501, Embedded Emulation USB Connector 

J501 is a Mini USB connector which is the primary interface to the embedded USB 

emulation controller. The pin outs for this connector are shown in the table below. 

Table 12: J501, Embedded Emulation USB Connector 


1 Power Input 

2 Data Minus 

3 Data Plus 

4 ID, not used 

5 Ground 

3.2.16 J506, +12 Volt Input 

Connector J506 is used to provide +12 volts to the board. Do not use the connector if 

powering the board from the AMCC connector. 



3.2.17 LA1, Logic Analyzer 1 Connector 

LA1 is a standard 38 pin mictor connector used to interface to the McBSP ports on the 

C6474 CPU1 and CPU2 devices. This connector is used for expansion and visibility 

interfaces. The signal on the pins are shown in the table below. 

Table 13: LA1, Logic Analyzer 1 Connector 

Pin Signal Pin Signal 

1 Not Used 38 Not Used 



4 CPU1-TIMI0 35 CPU2-TIMI0 

5 CPU1-TIMI1 34 CPU2-TIMI1 

6 CPU1-TIMO0 33 CPU2-TIMO0 

7 CPU1-TIMO1 32 CPU2-TIMO1 





12 CPU1-GPIO10 27 CPU2-GPIO10 








3-15


3.2.18 LA2, Logic Analyzer 2 Connector 

LA2 is a standard 38 pin mictor connector used to interface to the Timer and GPIO pins 

on the C6474 CPU1 and CPU2 devices. This connector is used for expansion and 

visibility interfaces. The signal on the pins are shown in the table below. 

Table 14: LA2, Logic Analyzer 2 Connector 

Pin Signal Pin Signal 




4 CPU1 CLKS0 35 CPU2 CLKS0 


6 CPU1-CLKR0 CPU2-CLKX0 33 Not Used 

7 CPU1-FSR0 CPU2-FSX0 32 Not Used 

8 CPU1-DR0 CPU2-DX0 31 Not Used 

9 CPU1-CLX0 CPU2-CLRK0 30 Not Used 

10 CPU1-FSX0 CPU2-FSR0 29 Not Used 

11 CPU1-DX0 CPU2-DR0 28 Not Used 

12 CPU1-CLKS1 27 CPU2-CLKS1 


14 CPU1-CLRK1 25 CPU2-CLKX1 

15 CPU1-FSR1 24 CPU2-FSX1 

16 CPU1-DR1 23 CPU2-DX1 

17 CPU1-CLKX1 22 CPU2-CLRK1 

18 CPU1-FSX1 21 CPU2-FSR1 

19 CPU1-DX1 20 CPU2-DR1 

3.2.19 P1, Optional Fanpower Connector 

P1 provides +5 volts for an optional Fan connection for CPU1. 

3.2.20 P2, Optional Fanpower Connector 

P2 provides +5 volts for an optional Fan connection for CPU2. 



3.3 Switches 

The TMS320C6474 Mezzanine Board has three push button switches, SW1-SW3. 

Their positions on the board are indicated in Figure 3-1. The functions of each switch 

are listed in the table below. 

Table 15: Mezzanine Board Switches 

Switch 

SW1 

SW2 

SW3 

Function 

Reset 

Power On Reset 

XWRSTz 

3.3.1 SW1, Reset Pushbutton 

When pushed SW1 drives a full board reset. This is equivalent to a power cycle and will 

have the following effects: 

- Turns off power to both DSPs. 

- Resets the CPLD. 

- Resets the embedded emulation block including USB port. 

- Turns on power to DSPs but holds them in reset with both PORz and 

XWMRSTz asserted low. 

- Reloads board configuration from EEPROMs and/or switches. 

- Releases reset to Ethernet controller then releases DSPs. 

If you are running Code Composer Studio (CCS) via the embedded emulation block 

then you will loose your CCS connection when SW1 is pressed as it does a full reset of 

the embedded emulation block. In this case you will have to exit and reenter CCS to 

reload the emulation application. 

If you are running CCS via an external emulator then you will still loose your CCS 

connection but can recover with a CCS disconnect/connect sequence. 

3.3.2 SW2, PORz Pushbutton 

Switch SW2 drives the DSP PORz pin low when pressed. If the DSP asserts RSTAT 

low then boot mode configuration pins will be re-asserted. If RSTAT is not asserted 

then boot mode configuration pins are high-z. 

This switch is digitally debounced and will drive PORz low for a minimum of 10 ms. 

3-17


3.3.3 SW3, XWMRSTz Pushbutton 

SW3 drives the DSP XWMRSTz pin low when pressed. The DSP boot configuration 

pins are NOT asserted for XWMRSTz. 

This switch is digitally debounced and will drive XWMRSTz low for minimum of 10ms. 

3.3.4 SW4, CPLD Option Switch 

SW4 is a 4 position DIP switch that is used to pull down the CPLD lines 

CPLD.OPTSW0-3 to ground. A diagram of the SW4 switch is shown below. 

Logic “1” 

Switch “OFF” 

Elevated 

Actuator 

1 2 3 4 

ON 

STANDALONE Logic “0” 

Switch ON 

ROM SEL 

DDRSLEWRATE 

FACTORY TEST 

SW4 

Figure 3-3, SW4, CPLD Option Switch 

Standalone Operation, Factory Test Selected 

The following table describes the positions on switch SW4. 

SW4 Switch 

Description 

Position 

1 AMCC/Standalone 

Select 

2 ROM_SEL 

Select 

3 DDRSLRATE 

Select 

4 Use Mode 

select 


Table 16: SW4, CPLD Option Switch 

Function 

Off = Operating in AMCC mode 

On =Operating in stand alone mode * 

Off =Select factory I 2 C configuration default EEPROM * 

On =Select the user I 2 C configuration EEPROM 

Off =DSP DDRSLRATE is 1 (full memory speed) * 

On =DSP DDRSLRATE is 0 (reduce slew rate by 33%) 

Off = Factory test mode 

On =Standard Mode * 




3.3.5 SW5, Boot Mode and Configuration Switch 

SW5 is a 8 position DIP switch that is used to configure boot options when the override 

switch, (SW5, position 8), is in the “OFF” position. A diagram of switch SW5 is shown 

below. See section 2.2 for configuration information. 

SW5 

Logic “1” 

Switch “OFF” 

Elevated 

Actuator 

1 2 3 4 5 6 7 8 

ON 

BOOTM0 

BOOTM1 

BOOTM2 

BOOTM3 

LENDIAN 

L2 CONFIG 

CORE CLK SEL 

OVERRIDE 

Logic “0” 

Switch ON 

Figure 3-4, SW5, Boot Mode and Configuration Switch 

I 2 C Boot Mode Selected 

Position 

The following table describes the positions on switch SW5. 

Table 17: SW5, Boot Mode and Configuration Switch Settings 

* default 

Function 

1 BOOTM0 

2 BOOTM1 

3 BOOTM2 

4 BOOTM3 

Boot Mode Options 

See next table 

5 LENDIAN Off = Little endian * 

On = Big endian 

6 L2 CONFIG On = Asymmetric L2 Configuration * 

Off = Symmetric L2 Configuration 

7 CORE CLK SEL On = Use SYSCLKIN for CPU Core Clock 

Off = Use ALTCORECLK for CPU Core Clock * 

8 OVERRIDE On = Ignore all options on SW5 

Off = Overrides I 2 C Config EEPROM 7 above parameters * 

3-19


The table below shows the signals on each switch position. 

Table 18: SW5, Boot Mode Options 

M3 M2 M1 M0 Boot Mode 

On On On On No Boot 

On On On Off I 2 C Master Boot A * 

On On Off On I 2 C master Boot B 

On On Off Off I 2 C Slave Boot 

On Off On On EMAC Master Boot 

On Off On Off EMAC Slave Boot 

On Off Off On EMAC Forced-Mode Boot 

On Off Off Off Reserved 

Off On On On Serial RapidIO Boot (Config 0) 

Off On On Off Serial RapidIO Boot (Config 1) 

Off On Off On Serial RapidIO Boot (Config 2) 

Off On Off Off Serial RapidIO Boot (Config 3) 

* default 

For more information on the boot modes refer to TI document SPRS552. 



3.4 Jumpers 

The TMS320C6474 Mezzanine Board has eight jumper blocks, JP1-JP8. Their 

positions on the board are indicated in Figure 3-1. The functions of each switch 

are listed in the table below. 

Table 19: C6474 Mezzanine Board Switches 

Switch 

JP1 

JP2 

JP3 

JP4 

JP5 

JP6 

JP7 

JP8 

Function 

CLKS0 Header 

CLKS1 Header 

User FSYNC Inputs 

C6474 CPU1 Alternate I 2 C Access Header 

C6474 CPU2 Alternate I 2 C Access Header 

C6474 CPU11 Power Reflex Overrides 

C6474 CPU2 Power Reflex Overrides 

C6474 CPU1 to CPU2 Sync Burst Connection 

3.4.1 Jumper JP1, CLKS0 Header 

Jumper JP1 is a 4 position jumper used to access the CLKS0 signals on the C6474 

CPU1 and CPU2. The layout of the header is shown in the figure below. 

2 

4 

1 

3 

Figure 3-5, Jumper JP1 

The signals on each pin are shown in the table. 

Table 20: Jumper JP1, CLKS0 Header 

Position Signal Position Signal 

1 GND 2 CPU1 CLKS0 


3-21


3.4.2 Jumper JP2, CLKS1 Header 

Jumper JP2 is a 4 position jumper to access the CLKS1 signals on the C6474 CPU1 

and CPU2. The layout of the header is shown in the figure below. 

2 

4 

1 

3 



Table 21: Jumper JP2, CLKS1 Header 






3.4.3 Jumper JP3, User FSYNC Inputs 

Jumper JP3 is a 14 position jumper used to drive optional burst signals to the C6474 

devices. The signals are buffered by U10. The buffer needs to be enabled when these 

optional inputs are used. The layout of the jumper is shown below. 

2 

1 

FSYNC INs 


The function of each jumper setting is shown in the table below. 

Table 22: Jumper JP3, User FSYNC Inputs 


1 GND 2 CPU1, CPU2 FSYNC_CLK 

3 GND 4 CPU1, CPU2 SYNC_BURST 

5 GND 6 CPU1, CPU2 TRTCLK 

7 GND 8 CPU1, CPU2 TRT 

9 GND 10 CPU1 SMFRAME CLK 

11 GND 12 CPU2 SMFRAME CLK 

13 GND 14 BUFFER ENABLE 

3-23


3.4.4 Jumper JP4, CPU1 I 2 C Header 

Jumper JP4 is an access point to the CPU1’s I 2 C signals. The mapping of the header is 

shown in the figure below. 

2 

4 

1 

3 



Table 23: Jumper JP4, CPU1 I 2 C Header 


1 GND 3 SCL (+3.3 Volts) 

2 GND 4 SDA (+3.3 Volts) 

3.4.5 Jumper JP5, CPU2 I 2 C Header 

Jumper JP4 is an access point to the CPU2’s I 2 C signals. The mapping of the header is 

shown in the figure below. 

2 

4 

1 

3 



Table 24: Jumper JP4, CPU2 I 2 C Header 


1 GND 3 SCL (+3.3 Volts) 

2 GND 4 SDA (+3.3 Volts) 



3.4.6 Jumper JP6, Voltage Control Override CPU1 

The C6474 device incorporates smart reflex power supply circuitry to adjust the core 

voltage on the device. JP6 is an override jumper that allows the user to force the pins 

off. Shorting positions 1-2, 3-4, 5-6, 7-8 forces that control position off. The jumper can 

be used in any combination of the above sequence to vary the core voltage. This is not 

recommended in general practice. In general practice the C6474 device itself will set 

these voltage control pins. The layout of the jumper is shown below. 

JP6 

1 

2 

VCTRL 

3 

2 

1 

0 



Table 25: Jumper JP6, Voltage Control Override CPU1 


2 GND 1 CPU1 VCNTL0 




3-25


Table 26: Jumper JP6, Voltage Selection 

VCNTL # VCNTL[3:0] CV DD 

0 0000 0.900 

1 0001 0.920 

2 0010 0.940 

3 0011 0.960 

4 0100 0.980 

5 0101 1.00 

6 0110 1.02 

7 0111 1.04 

8 1000 1.06 

9 1001 1.08 

10 1010 1.10 

11 1011 1.12 

12 1100 1.14 

13 1101 1.16 

14 1110 1.18 

15 1111 1.20 



3.4.7 Jumper JP7, Voltage Control Override CPU2 

The C6474 device incorporates smart reflex power supply circuitry to adjust the core 

voltage on the device. JP7 is an override jumper that allows the user to force the pins 

off. Shorting positions 1-2, 3-4, 5-6, 7-8 forces that control position off. The jumper can 

be used in any combination of the above sequence to vary the core voltage. This is not 

recommended in general practice. In general practice the C6474 device itself will set 

these voltage control pins. The layout of the jumper is shown below. 

F2 VCTRL 

3 

2 

1 

0 

2 

1 

JP7 



Table 27: Jumper JP7, Voltage Control Override CPU2 






3-27


Table 28: Jumper JP7, Voltage Selection 

VCNTL # VCNTL[3:0] CV DD 

0 0000 0.900 

1 0001 0.920 

2 0010 0.940 

3 0011 0.960 

4 0100 0.980 

5 0101 1.00 

6 0110 1.02 

7 0111 1.04 

8 1000 1.06 

9 1001 1.08 

10 1010 1.10 

11 1011 1.12 

12 1100 1.14 

13 1101 1.16 

14 1110 1.18 

15 1111 1.20 

3.4.8 Jumper JP8, SYNC Burst 

Jumper JP8 is a 2 position jumper which allows the Sync burst pin of the C6474 

CPU1 to be connected to the Sync Burst pin of CPU2. The normal configuration is to 

short this jumper. The jumper is shown in the figure below. 

JP8 

JP8 

Installed 

Un-installed 




3.5 Test Points 

The TMS320C6474 Mezzanine Board has 28 test points. The position of each test 

point is shown in the figure below. 

TP7 

TP4 TP9-11 TP1 TP2-3 TP19-22 TP6 

DS2 

DS501 

TP15-18 

TP5 

DS10-DS13 

DS3 

TP12-14 

DS4-DS9 

DS20-DS23 

Figure 3-13, TMS320C6474 Mezzanine Board Test Point Locations 

3-29


Table 29: TMS320C6474 Mezzanine Board Test Points 

Test Point Signal Test Point Signal 

TP1 CDCL6010, Status, U2, Pin 13 TP13 F2_PORz, U11A, N3 

TP2 CDCL6010, YP10, U2, Pin 46 TP14 F2_XWRSTz, U11A, P2 

TP3 CDCL6010, YN10, U2, Pin 45 TP15 SRIO_CLK_EN, U11B, D6 

TP4 F1_SYSCLKOUT, U17C, AD6 TP16 BURST_CLK_EN, U11B, C5 

TP5 F2_SYSCLKOUT, U30C, AD6 TP17 CPU_CLKS_EN, U11B, D5 

TP6 3.3V_ALT, J1, B4 TP18 U11B, A2 

TP7 DVDD18MON, U17I, AG7 TP19 U11D, M12, B4.IO_49 

TP9 F1_RESETSTAT, U11C, E13 TP20 U11D, R13, B4.IO_50 

TP10 F1_PORz, U11C, E14 TP21 U11D, N12, B4.IO_51 

TP11 F1_XWRSTz, U11C, D13 TP22 U11D, R14, B4.IO_52 

TP12 F2_RESETSTAT, U11A, M4 



3.6 System LEDs 

The TMS320C6474 Mezzanine Board has seventeen LEDs. Their positions on the 

board are indicated in Figure 3-1. The meaning of each switch are listed in the table 

below. 

Table 30: Mezzanine Board LEDs 

Switch Color Meaning 

DS2 Green 12 Volt Power 

DS3 Red Board Config Status 

DS4 Green +3.3 Volts Okay 




DS8 Green CPU 1 Core Voltage Okay 

DS9 Green CPU 2 Core Voltage Okay 

DS10 Green CPU 1 User LED 0, controlled by GPO0 








DS501 Green Embedded JTAG USB Link Status 

3-31



Appendix A 

Schematics 

This appendix contains the schematics for the TMS320C6474 

Mezzanine Board. 

A-1

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


REV DESCRIPTION 

DATE APPROVED 

A Initial schematic ready for layout. 

08/15/08 RRP 

01 EVM TITLE SHEET 

02 AMC INTERFACE 

03 SRIO ROUTING 

04 AIF ROUTING 

05 MASTER CLOCK DOMAIN 

06 SRIO CLOCK DOMAIN 

D D 

07 McBSP MICTOR/ FSYNC EXP CONN 

08 HIERARCHIAL EMULATION BLOCK 

09 CPLD1 - JTAG/ENABLES 

10 CPLD2 - C6474 CPU-1 INTERFACE PINS 

11 CPLD 3 - SWITCHES 

12 CPLD 4 - C6474 CPU-2 INTERFACE PINS 

13 CPLD 5 - POWER PINS 

14 EMU0/1 ROUTING 

15 C6474-CPU1 DDR2 MEMORY 

16 C6474-CPU1 McBSP/GPIO/BOOT STRAPPING 

17 C6474-CPU1 DDR2 INTERFACE CONTROLLER 

18 C6474-CPU1 AIF/FSYNC INTERFACE 

19 C6474-CPU1 EMU INTERFACE 

20 C6474-CPU1 I2C/VCTL/MISC 

21 C6474-CPU1 PLL 

22 C6474-CPU1 SRIO/SGMII 

23 C6474-CPU1 PWR PINS 

24 C6474-CPU1 PWR PINS II 

C 25 C6474-CPU1 PWR CAPS CORE 

C 

26 C6474-CPU2 DDR2 MEMORY 

27 C6474-CPU2 McBSP/GPIO/BOOT STRAPPING 

28 C6474-CPU2 DDR2 INTERFACE CONTROLLER 

29 C6474-CPU2 AIF/FSYNC INTERFACE 

30 C6474-CPU2 EMU INTERFACE 

31 C6474-CPU2 I2C/VCTL/MISC 

32 C6474-CPU2 PLL 

33 C6474-CPU2 SRIO/SGMII 

34 C6474-CPU2 PWR PINS 

35 C6474-CPU2 PWR PINS II 

36 C6474-CPU2 PWR CAPS CORE 

37 88E6122 INTERFACE 

38 88E6122 POWER 

39 ETHERNET CONNECTOR 

40 POWER 

41 POWER MONITORS 

42 C6474-CPU1 CORE POWER 

B 43 C6474-CPU2 CORE POWER 

B 

44 POWER IN 12V TO 5 V CONVERTER 

45 EMU TOPOLOGY DIAGRAM 

REVISION STATUS OF SHEETS 

REV 

SHEET 

REV 

A A A A A 

SHEET 

41 42 43 44 45 

REV A A A A A A A A A A 

DWN 

DATE 

SHEET 31 32 33 34 35 36 37 38 39 40 

R.R.P. 08/15/2008 

A CHK 

DATE 

SPECTRUM DIGITAL INCORPORATED 

A 

REV A A A A A A A A A A 

T.W.K. 08/15/2008 

ENGR 

DATE 

SHEET 21 22 23 24 25 26 27 28 29 30 

R.R.P. 08/15/2008 

Title: DUAL TMS320C6474 AMC MEZZANINE BOARD 

ENGR-MGR 

DATE 

REV 

A A A A A 

R.R.P. 08/15/2008 

Page Contents: 

Title Page 

QA 

DATE 

SHEET 11 12 13 14 15 16 17 18 19 20 

C.M.D. 08/15/2008 

Revision: 

MFG 

DATE 

Size: B 

DWG NO 511222-0001 

A 

REV A A A A B A A A A A NEXT ASSY 

USED ON 

R.R.P. 08/15/2008 

RLSE 

DATE 

Date: Wednesday, October 15, 2008 Sheet 1 o f 45 

SHEET 

3 5 

10 APPLICATION 

R.R.P. 08/15/2008 

A 

1 

A 

2 

A 

A 

4 

A 

6 

7 

8 

9 

A-2 TMS320C6474 Mezzanine EVM Board Technical Reference

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


J1 

3.3V_ALT 

B1 

B170 

TP6 

B2 

B169 

AMC_PS1 

B3 

B168 

B4 

B167 

B5 

B166 

B6 

B165 

B7 

B164 

B8 

B163 

D R1 

D 

B9 

B162 

360 

B10 

B161 

B11 

B160 

B12 

B159 

B13 

B158 

B14 

B157 

AMCC_P19_TXP 

AMCC_P19_TXP 4 

B15 

B156 

AMCC_P19_TXN 

AMCC_P19_TXN 4 

37 AMCC_P0_TXP 

AMCC_P0_TXP 

B16 

B155 

37 AMCC_P0_TXN 

AMCC_P0_TXN 

B17 

B154 

AMCC_P19_RXP 

AMCC_P19_RXP 4 

B18 

B153 

AMCC_P19_RXN 

AMCC_P19_RXN 4 

37 AMCC_P0_RXP 

AMCC_P0_RXP 

B19 

B152 

AMCC_P0_RXN 

AMCC_P18_TXP 

37 AMCC_P0_RXN 

B20 

B151 


B21 

B150 

AMCC_P18_TXN 


B22 

B149 

B23 

B148 

AMCC_P18_RXP 


B24 

B147 

AMCC_P18_RXN 


B25 

B146 

B26 

B145 

AMCC_P17_TXP 


B27 

B144 

AMCC_P17_TXN 


B28 

B143 

EVM_3V3 

B29 

B142 

AMCC_P17_RXP 


B30 

B141 

AMCC_P17_RXN 


B31 

B140 

R2 

AMCC_P16_TXP 

C B32 

B139 


C 

10K 

B33 

B138 

AMCC_P16_TXN 


B34 

B137 

B35 

B136 

AMCC_P16_RXP 


B36 

B135 

AMCC_P16_RXN 


B37 

B134 

B38 

B133 

AMCC_P15_TXP 


B39 

B132 

AMCC_P15_TXN 


B40 

B131 

AMC.ENABLEn 

AMCC_P15_RXP 

AMC.ENABLEn 

B41 

B130 


B42 

B129 

AMCC_P15_RXN 


B43 

B128 

AMCC_P4_TXP 

AMCC_P4_TXP 

DSPA_RIORXP0 

B44 

B127 

AMCC_P14_TXP 


AMCC_P4_TXN 

AMCC_P4_TXN 

DSPA_RIORXN0 

B45 

B126 

AMCC_P14_TXN 


B46 

B125 

AMCC_P4_RXP 

AMCC_P4_RXP 

DSPA_RIOTXP0 

B47 

B124 

AMCC_P14_RXP 


AMCC_P4_RXN 

DSPA_RIOTXN0 

AMCC_P14_RXN 

AMCC_P4_RXN 

B48 

B123 


B49 

B122 

AMCC_P5_TXP 

AMCC_P5_TXP 

DSPA_RIORXP1 

B50 

B121 

AMCC_P13_TXP 


AMCC_P5_TXN 

AMCC_P5_TXN 

DSPA_RIORXN1 

B51 

B120 

AMCC_P13_TXN 


B52 

B119 

AMCC_P5_RXP 

AMCC_P5_RXP 

DSPA_RIOTXP1 

B53 

B118 

AMCC_P13_RXP 


AMCC_P5_RXN 

AMCC_P5_RXN 

DSPA_RIOTXN1 

B54 

B117 

AMCC_P13_RXN 


B55 

B116 

B DSPA_I2C_SCL 

B56 

B115 

AMCC_P12_TXP 


B 

B57 

B114 

AMCC_P12_TXN 


B58 

B113 

DSPA_RIORXP2 

B59 

B112 

AMCC_P12_RXP 


DSPA_RIORXN2 

B60 

B111 

AMCC_P12_RXN 


B61 

B110 

DSPA_RIOTXP2 

B62 

B109 

DSPA_RIOTXN2 

B63 

B108 

B64 

B107 

DSPA_RIORXP3 

B65 

B106 

DSPA_RIORXN3 

B66 

B105 

B67 

B104 

DSPA_RIOTXP3 

B68 

B103 

DSPA_RIOTXN3 

B69 

B102 

B70 

B101 

DSPA_I2C_SDA 

B71 

B100 

B72 

B99 

AMC_12V 

B73 

B98 

B74 

B97 

AMCC_P9_TXP 

AMCC_P9_TXP 3 

B75 

B96 

AMCC_P9_TXN 

AMCC_P9_TXN 3 

B76 

B95 

AMC_PS1 

B77 

B94 

AMCC_P9_RXP 

AMCC_P9_RXP 3 

R3 

B78 

B93 

AMCC_P9_RXN 

AMCC_P9_RXN 3 

220 

D1 

B79 

B92 

A BAS16-7-F 

B80 

B91 

AMCC_P8_TXP 

A 

AMCC_P8_TXP 3 


B81 

B90 

AMCC_P8_TXN 

AMCC_P8_TXN 3 

B82 

B89 

DS2 

AMC_PS0 

B83 

B88 

AMCC_P8_RXP 

AMCC_P8_RXP 3 


B84 

B87 

AMCC_P8_RXN 

AMCC_P8_RXN 3 

GREEN 

B85 

B86 


AMC INTERFACE 

Revision: 

EDGE CONNECTOR 

Size: B 

DWG NO 511222-0001 

A 

Date: 

Sheet o f Wednesday, October 15, 2008 2 45 

9 

3 

3 

3 

3 

3 

3 

3 

3 

A-3

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


CF1 CFOOT2 

CF2 CFOOT2 

D AMCC_P4_RXP 

AMCC_P5_TXP 

D 

2 

AMCC_P4_RXP 2 

AMCC_P5_TXP 

2 

22 F1_RIORXP0 

F1_RIORXP0 1 .1uF 

1 F2_RIOTXP0 

F2_RIOTXP0 33 

3 

3 

22 F1_RIORXN0 

CF3 CFOOT2 

CF4 CFOOT2 

2 

AMCC_P4_RXN 

AMCC_P4_RXN 2 

AMCC_P5_TXN 

AMCC_P5_TXN 

2 

F1_RIORXN0 1 .1uF 

1 F2_RIOTXN0 

3 

3 

F2_RIOTXN0 33 

CF5 CFOOT2 

2 

AMCC_P4_TXP 

AMCC_P4_TXP 2 

22 F1_RIOTXP0 

F1_RIOTXP0 1 

3 

CF6 CFOOT2 

AMCC_P5_RXP 

AMCC_P5_RXP 

2 

.1uF 1 F2_RIORXP0 

F2_RIORXP0 33 

3 

CF7 CFOOT2 

CF8 CFOOT2 

2 

AMCC_P4_TXN 

AMCC_P4_TXN 2 

AMCC_P5_RXN 

AMCC_P5_RXN 

2 

22 F1_RIOTXN0 

F1_RIOTXN0 1 

.1uF 1 F2_RIORXN0 

F2_RIORXN0 33 

C 3 

3 

C 

CF9 CFOOT2 

CF10 CFOOT2 

2 

AMCC_P8_RXP 

AMCC_P8_RXP 2 

AMCC_P9_TXP 

AMCC_P9_TXP 

2 

22 F1_RIORXP1 

F1_RIORXP1 1 

F2_RIOTXP1 

.1uF 

1 

F2_RIOTXP1 33 

3 

3 

CF11 CFOOT2 

2 

AMCC_P8_RXN 

AMCC_P8_RXN 2 

22 F1_RIORXN1 

F1_RIORXN1 1 

.1uF 

3 

CF12 CFOOT2 

AMCC_P9_TXN 

AMCC_P9_TXN 

2 

1 F2_RIOTXN1 

F2_RIOTXN1 33 

3 

B CF13 CFOOT2 

CF14 CFOOT2 

B 

2 

AMCC_P8_TXP 

AMCC_P8_TXP 2 

AMCC_P9_RXP 

AMCC_P9_RXP 

2 

22 F1_RIOTXP1 

F1_RIOTXP1 1 

F2_RIORXP1 

.1uF 

1 

F2_RIORXP1 33 

3 

3 

CF15 CFOOT2 

2 

AMCC_P8_TXN 

AMCC_P8_TXN 2 

22 F1_RIOTXN1 

F1_RIOTXN1 1 

3 

CF16 CFOOT2 

AMCC_P9_RXN 

AMCC_P9_RXN 

2 

F2_RIORXN1 

.1uF 

1 

F2_RIORXN1 33 

3 

A SPECTRUM DIGITAL INCORPORATED 

A 

Title: 

DUAL TMS320C6474 AMC MEZZANINE BOARD 


SRIO ROUTING 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


0 

0 

0 

0 

2 

2 

2 

2 

2 

2 

2 

2 

0 

0 

0 

0 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


CF17 CFOOT1 

CF18 CFOOT2 

2 AMCC_P14_TXP 2 

18 F1_AIFTXP1 

F1_AIFTXP1 

1 2 

F2_AIFRXP1 

F2_AIFRXP1 29 

18 F1_AIFTXP4 

F1_AIFTXP4 1 

.1uF 

3 

CF19 CFOOT2 


F2_AIFRXP4 

.1uF 

1 

F2_AIFRXP4 29 

3 

CF20 CFOOT1 

CF21 CFOOT2 

CF22 CFOOT2 

2 

D AMCC_P14_TXN 2 AMCC_P15_RXN 2 

F1_AIFTXN1 

F2_AIFRXN1 

F1_AIFTXN4 

F2_AIFRXN4 

D 

18 F1_AIFTXN1 

1 2 

F2_AIFRXN1 29 

18 F1_AIFTXN4 

1 

.1uF 

1 

F2_AIFRXN4 29 

.1uF 

3 

3 

CF23 CFOOT1 

CF24 CFOOT2 

2 AMCC_P14_RXP 2 

18 F1_AIFRXP1 

F1_AIFRXP1 

1 2 

F2_AIFTXP1 

F2_AIFTXP1 29 

18 F1_AIFRXP4 

F1_AIFRXP4 1 

.1uF 

.1uF 

3 

CF25 CFOOT2 


1 F2_AIFTXP4 

F2_AIFTXP4 29 

3 

CF26 CFOOT1 

CF27 CFOOT2 

2 AMCC_P14_RXN 2 

18 F1_AIFRXN1 

F1_AIFRXN1 

1 2 

F2_AIFTXN1 

F2_AIFTXN1 29 

18 F1_AIFRXN4 

F1_AIFRXN4 1 

.1uF 

.1uF 

3 

CF28 CFOOT2 


1 F2_AIFTXN4 

F2_AIFTXN4 29 

3 

CF29 CFOOT2 

2 AMCC_P18_TXP 2 

F1_AIFTXP2 

18 F1_AIFTXP2 

1 

3 

AMCC_P19_RXP 

CF30 CFOOT2 

CF31 CFOOT2 

2 

2 

F2_AIFRXP2 

F2_AIFRXP2 29 18 F1_AIFTXP5 

F1_AIFTXP5 

.1uF 

1 

1 

3 

3 


CF32 CFOOT2 


.1uF 1 F2_AIFRXP5 

F2_AIFRXP5 29 

3 

C C 

CF33 CFOOT2 

2 AMCC_P18_TXN 2 

18 F1_AIFTXN2 

F1_AIFTXN2 1 

3 

AMCC_P19_RXN 

CF34 CFOOT2 

CF35 CFOOT2 

2 

2 

F2_AIFRXN2 

F2_AIFRXN2 29 18 F1_AIFTXN5 

F1_AIFTXN5 

.1uF 

1 

1 

3 

3 


CF36 CFOOT2 


.1uF 1 F2_AIFRXN5 

F2_AIFRXN5 29 

3 

CF37 CFOOT2 

2 AMCC_P18_RXP 2 

18 F1_AIFRXP2 

F1_AIFRXP2 1 

.1uF 

3 

CF38 CFOOT2 


1 F2_AIFTXP2 

F2_AIFTXP2 29 18 F1_AIFRXP5 

3 

CF39 CFOOT2 

CF40 CFOOT2 

2 AMCC_P12_RXP 2 AMCC_P13_TXP 2 

F1_AIFRXP5 1 .1uF 

1 F2_AIFTXP5 

3 

3 

F2_AIFTXP5 29 

CF41 CFOOT2 


18 F1_AIFRXN2 

F1_AIFRXN2 1 

.1uF 

3 

CF42 CFOOT2 

CF43 CFOOT2 



1 F2_AIFTXN2 

F2_AIFTXN2 29 18 F1_AIFRXN5 

F1_AIFRXN5 1 .1uF 

3 

3 

CF44 CFOOT2 


1 F2_AIFTXN5 

F2_AIFTXN5 29 

3 

CF45 CFOOT2 

CFOOT2 CF46 

B 2 AMCC_P16_TXP 2 AMCC_P17_RXP 2 

J2 

1 

J3 

F1_AIFTXN0_SMA 18 

1 

F2_AIFRXN0_SMA 29 

B 

18 F1_AIFTXP3 

F1_AIFTXP3 1 

F2_AIFRXP3 

.1uF 

1 

F2_AIFRXP3 29 

SMA 

SMA 

3 

3 

CF47 CFOOT2 

2 AMCC_P16_TXN 2 

18 F1_AIFTXN3 

F1_AIFTXN3 1 

3 

CFOOT2 CF48 


F2_AIFRXN3 

.1uF 

1 

F2_AIFRXN3 29 

3 

18 

F1_AIFRXP3 

F1_AIFRXP3 


AMCC_P17_TXP 

F2_AIFTXP3 

F2_AIFTXP3 29 

J4 

SMA 

1 

J5 

F1_AIFTXP0_SMA 18 1 

F2_AIFRXP0_SMA 29 

SMA 

CF51 CFOOT2 


18 F1_AIFRXN3 

F1_AIFRXN3 1 

.1uF 

3 

CF52 CFOOT2 


1 F2_AIFTXN3 

F2_AIFTXN3 29 

3 


A 

Title: 



AIF ROUTING 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


0 

0 

2 

2 

2 

2 

2 

2 

2 

2 

0 

0 

0 

0 

0 

2 

2 

2 

2 

2 

2 

2 

2 

0 

0 

0 

0 

2 

3 

4 

5 

2 

3 

4 

5 

2 

3 

4 

5 

2 

3 

4 

5 

CF49 CFOOT2 

2 

1 

.1uF 

3 

CF50 CFOOT2 

2 

1 

3 

0 

0 

0 

0 

0 

A-5

5 

5 

4 

4 

3 

3 

2 

2 

1 

0 

0 

0 

0 

1 



L1 

L2 

1 2 1 2 

BLM18AG102 BLM18AG102 


L3 

1 2 

C1 C2 

C3 C4 

BLM18AG102 

C5 C6 C7 

C8 

0.047UF 0.1UF 0.01UF 560PF 

0.1UF 0.01UF 560PF 0.047UF 

+ C9 

C10 C11 C12 

D 1UF 0.01UF 560PF 0.1UF 

D 

U1 CDCE906 

3 

VCC.1 VCCOUT1 

14 

7 

VCC.2 VCCOUT2 

18 

F1_SYSCLK 61.44 MHz 

C13 18 pF 

5 

L4 

CLK_IN0 

F2_SYSCLK 61.44 MHz 

1 2 

Y1 

CLK_30.72MHZ 

20MHz 

Y0 

11 R4 10 

R5 230 

BLM18AG102 

F1_SYNC_CLK 30.72 MHz 

R6 10 

C15 

U2 

C18 18 pF 

Y1 

12 

+ C14 

C16 C17 

CPLD_CLK 10 

6 

R7 

1UF 0.01UF 560PF 0.1UF 

CLK_IN1 

F2_SYNC_CLK 30.72 MHz 

R8 10 

267 

R9 NO-POP 

Y2 

15 

1 

R10 NO-POP 

S0/A0/CLK_SEL 

2 

Y3 

16 R11 10 

S1/A1 

2 

AVDD 

YP0 

6 

F1_SYSCLK_P 21 

5 

F1_SYSCLK_N 21 

R12 10 

AVDD 

YPN 7 

20 F1_3V3_SCL 

10 

SCL 

Y4 

19 

C19 NO-POP 

44 

R13 0 

AVDD 

20 F1_3V3_SDA 

9 

SDA 

1 

47 

F2_SYSCLK_P 32 

R14 10 

AVDD 

YP1 

9 

Y5 

20 

F2_SYSCLK_N 32 

C20 NO-POP 

YN1 

10 

4 

R15 NO-POP 

GND.1 

8 

J6 

GND.2 

48 

VCP 

YP2 

15 

13 

SMA 

GND.3 

1 

VCN 

YN2 

16 

17 

GND.4 

YP3 

18 

C YN3 

19 

C 


C267 

0.1uF 

11,20 

11,20 

F1_SCL 

F1_SDA 


C34 0.01uF 

F1_FSYNC_CLKP 18 

F1_FSYNC_CLKN 18 

C37 0.01uF 

F2_FSYNC_CLKP 29 

C38 0.01uF 

F2_FSYNC_CLKN 29 

R23 22 

CPLD_FSYNC_CLKP 6 

R25 22 

CPLD_FSYNC_CLKN 6 

B B 

TP1 

R18 

NO-POP 

CDCL6010 

CF53 CFOOT2 

3 

1 

2 


C23 

VCC 16 

1 

1A 

1Y 2 

F1_ALTCORE_CLKP 21 

1Z 

3 

F1_ALTCORE_CLKN 21 

7 

2A 

2Y 6 

F1_DDRCLK_P 21 

2Z 

5 

F1_DDRCLK_N 21 

0.1uF 

3Y 10 

F2_ALTCORE_CLKP 32 

9 

3Z 

11 

U4 

3A 

F2_ALTCORE_CLKN 32 

CF54 CFOOT2 

15 

4A 

4Y 14 

F2_DDRCLK_P 32 

1 

EN VCC 4 

3 

4Z 

13 

F2_DDRCLK_N 32 

1 

2 

OUT 

3 R29 22 

GND 

2 

4 

R31 0 

G 

12 

66 MHz 

G 

GND 8 

R30 

SN65LVDS31 

A 10K 



A 

T ROUTE WITH VERY SHORT LINES 

Title: 


CPU_CLKS_EN 


MASTER CLOCK DOMAIN 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


9 

12 

49 

GND 

GND 

2 

3 

4 

5 

VDD 8 

VDD 11 

VDD 14 

VDD 17 

VDD 20 

VDD 23 

VDD 26 

VDD 29 

VDD 32 

VDD 35 

VDD 38 

VDD 41 

1 

2 

EN 

GND 

U18 

50 MHz 

VCC 4 

OUT 

3 

1 

J7 

SMA 

R17 0 

R16 0 

TP2 

TP3 

3 

4 

13 

24 

25 

37 

36 

46 

45 

CLKP 

CLKN 

STATUS 

SCL 

SDA 

ADD1 

ADD0 

YP10 

YN10 

YP4 

YN4 

YP5 

YN5 

YP6 

YN6 

YP7 

YN7 

YP8 

YN8 

YP9 

YN9 

21 

22 

27 

28 

30 

31 

2 

3 

4 

5 

R132 22 

CF57 CFOOT2 

3 

1 

2 

CF58 CFOOT2 

3 

1 

2 

R27 

10K 

R28 

10K 

33 

34 

40 

39 

43 

42 

C36 0.01uF 

C21 

C22 

0.001UF 0.1UF 

U3 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 




L5 

C24 

U5 

Ferrite Chip 

C25 .01uF 

F1_RIOSGMIICLKP 22 

0.1uF 

4 

C27 C28 C29 C30 

U6 

VCC.1 

1Y 16 

1Z 

15 

C26 .01uF 

F1_RIOSGMIICLKN 22 

1 

1.0uF 0.01uF 560pF 0.1uF 

E/D VCC 6 

R32 0 

6 

D VoD+ 

4 

A 

2Y 14 

C31 .01uF 

F2_RIOSGMIICLKN 33 

D 

VoD- 

5 

7 

B 

2Z 

13 

R33 0 

C32 .01uF 

F2_RIOSGMIICLKP 33 

3 

GND NC 2 

R34 0 

1 

LV7745D-125Mhz 

EN1 

3Y 12 

2 

EN2 

3Z 

11 

R35 0 

3 

EN3 

8 

EN4 

4Y 10 

5 

R37 

GND.1 

4Z 

9 

R36 

10K 10K 

SN65LVDS104PW 

SRIO_CLK_EN 


C33 

U7 

0.1uF 

VCC 8 

CPLD_FSYNC_CLKP 

CPLD_FSYNC_CLKP 

2 

A 

R38 0 

CPLD_FSYNC_CLK 9 

CPLD_FSYNC_CLKN 

R 7 

C CPLD_FSYNC_CLKN 

1 

B 

C 

3 

NC.3 GND 5 

4 

NC.4 

6 

NC.6 


SN65LVDT2D 

U8 

C35 

R24 0 

F1_FRAMEBURSTP 18 

4 

0.1uF 

VCC.1 

1Y 16 

1Z 

15 

R26 0 

F1_FRAMEBURSTN 18 

R39 0 

CPLD_FRAME_BURST 

6 

R147 0 

A 

2Y 14 

F2_FRAMEBURSTP 29 

7 

NC.1 

2Z 

13 

R148 0 

F2_FRAMEBURSTN 29 

R40 0 

BURST_CLK_EN 

1 

EN1 

3Y 12 

2 

R41 0 

EN2 

3Z 

11 

3 

EN3 

8 

EN4 

4Y 10 

B 5 

B 

R42 R43 

GND.1 

4Z 

9 

10K 10K 

SN65LVDS105PW EVM_3V3 

C39 

U9 

0.1uF 

VCC 8 

J8 

1 EXT_FSYNC_BURSTP 

R260 0 2 

SMA 

A 

R44 0 

R 7 

EXT_CPLD_FSYNC_BURST 9 

R259 0 1 

B 

3 

4 

6 

NC.3 

NC.4 

NC.6 

GND 5 

SN65LVDT2D 


A 

J9 

1 EXT_FSYNC_BURSTN 

SMA 



SRIO CLOCK DOMAIN 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: Sheet o f Wednesday, October 15, 2008 6 45 

9 

5 

5 

9 

9 

2 

3 

4 

5 

2 

3 

4 

5 

A-7

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


JP1 

F1_CLKS0 

1 2 

F2_CLKS0 

3 4 

HEADER 2X2 

LA1 

1 

GND1 GND3 

38 

2 

GND2 GND4 

37 

3 

EMU_2V5 

CLK:0 CLK:1 

36 

D 16 F1_CLKS0 

F1_CLKS0 

4 

F2_CLKS0 

3:7 1:7 

35 

F2_CLKS0 27 

D 

5 

16,27 F1_CLKR0_F2_CLKX0 

F1_CLKR0_F2_CLKX0 

3:6 1:6 

34 

6 

16,27 F1_FSR0_F2_FSX0 

F1_FSR0_F2_FSX0 

3:5 1:5 

33 

NOTE: 

7 

16,27 F1_DR0_F2_DX0 

F1_DR0_F2_DX0 

3:4 1:4 

32 

McBSP0 on CPU1 TIED 

8 

16,27 F1_CLKX0_F2_CLKR0 

F1_CLKX0_F2_CLKR0 

1:3 

31 

R475 R476 R477 R478 

3:3 

9 

TO McBSP0 on CPU2 

16,27 F1_FSX0_F2_FSR0 

F1_FSX0_F2_FSR0 

3:2 1:2 

30 

360 

360 

360 

360 

10 

F1_DX0_F2_DR0 

3:1 1:1 

29 

16,27 F1_DX0_F2_DR0 

11 

3:0 1:0 

28 

NOTE: 

McBSP1 on CPU1 

Device 

16 

16 

16 

16 

16 

16 

16 

F1_CLKS1 

F1_CLKR1 

F1_FSR1 

F1_DR1 

F1_CLKX1 

F1_FSX1 

F1_DX1 

F1_CLKS1 

F1_CLKR1 

F1_FSR1 

F1_DR1 

F1_CLKX1 

F1_FSX1 

F1_DX1 

12 

13 

14 

15 

16 

17 

18 

19 

2:7 

2:6 

2:5 

2:4 

2:3 

2:2 

2:1 

2:0 

0:7 

0:6 

0:5 

0:4 

0:3 

0:2 

0:1 

0:0 

27 

26 

25 

24 

23 

22 

21 

20 

F2_CLKS1 

F2_CLKX1 

F2_FSX1 

F2_DX1 

F2_CLKR1 

F2_FSR1 

F2_DR1 

F2_CLKS1 27 

F2_CLKX1 27 

F2_FSX1 27 

F2_DX1 27 

F2_CLKR1 27 

F2_FSR1 27 

F2_DR1 27 

DS10 

GRN 

NOTE: 

McBSP1 

on CPU_2 Device 

DS11 

GRN 

DS12 

GRN 

DS13 

GRN 

39 

GND5 GND8 

42 

40 

GND6 GND9 

43 

41 

LED1_F1 

GND7 KEY 44 

11 LED1_F1 

LED2_F1 

11 LED2_F1 

LED3_F1 

P6434 Probe 

11 LED3_F1 

LED4_F1 

11 LED4_F1 

C C 

JP2 

F1_CLKS1 

1 2 

F2_CLKS1 

EMU_2V5 

3 4 

45 

46 

45 

46 

HEADER 2X2 

LA2 

1 

GND1 GND3 

38 

2 

R479 R480 R481 R482 

GND2 GND4 

37 

3 

CLK:0 CLK:1 

36 

360 

360 

360 

360 

20 F1_TIMI0 

4 

3:7 1:7 

35 

F2_TIMI0 31 

20 F1_TIMI1 

5 

3:6 1:6 

34 

F2_TIMI1 31 

DS21 

DS22 DS23 

18,20 F1_TIMO0 

6 

1:5 

33 

DS20 

3:5 

F2_TIMO0 31 

GRN GRN 

20 F1_TIMO1 

7 

1:4 

32 

GRN 

3:4 

F2_TIMO1 31 

8 

GRN 

3:3 1:3 

31 

9 

3:2 1:2 

30 

10 

3:1 1:1 

29 

11 

3:0 1:0 

28 

10,16 F1_GP10_DEVNUM2 

12 

2:7 0:7 

27 

F2_GP10_DEVNUM2 12,27 


13 

2:6 0:6 

26 


10,16 F1_GP12 

14 

2:5 0:5 

25 

F2_GP12 12,27 

B 10,16 F1_GP13 

15 

F2_GP13 12,27 

B 

2:4 0:4 

24 

LED1_F2 

10,16 F1_GP14 

16 

2:3 0:3 

23 

F2_GP14 12,27 

11 LED1_F2 

LED2_F2 

10,16 F1_GP15 

17 

2:2 0:2 

22 

F2_GP15 12,27 

11 LED2_F2 

18 

LED3_F2 

2:1 0:1 

21 

11 LED3_F2 

19 

LED4_F2 

2:0 0:0 

20 

11 LED4_F2 

39 

40 


41 

GND5 

GND6 

GND7 

GND8 

42 

GND9 

43 

KEY 44 

JP8 

P6434 Probe 

1 2 

45 

46 

45 

46 

R45 

4.75K 

R46 

4.75K 

HEADER 2X1 

JP3 

U10 

1 

2 

1A0 1Y0 

18 

R47 22 

1 2 

2 

F1_FSYNC_CLK 18 

3 

4 

1A1 1Y1 

16 

R48 22 

3 4 

4 

F2_FSYNC_CLK 29 

5 

6 

1A2 1Y2 

14 

R49 22 

5 6 

6 

F1_SYNC_BURST 18 

7 

8 

1A3 1Y3 

12 

R50 22 

7 8 

8 

F2_SYNC_BURST 29 

9 

R51 22 

9 10 

10 

11 

2A0 2Y0 

9 

F1_TRTCLK 18 

11 

13 

2A1 2Y1 

7 

R52 22 

11 12 

12 

F2_TRTCLK 29 

13 

15 

2A2 2Y2 

5 

R53 22 

13 14 

14 

F1_TRT 18 

A 17 

R54 22 


A 

2A3 2Y3 

3 

F2_TRT 29 

HEADER 7X2 

1 

1OE_L VCC 20 

19 



2OE_L GND 10 

74LVT244 


McBSP Mictor 

18 F1_SMFRAMECLK 

C42 

Revision: 

0.1UF 

Size: B 

DWG NO 511222-0001 

A 

29 F2_SMFRAMECLK 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


EVM_3V3 EVM_3V3 EVM_3V3 

R55 

R56 

10K 

R57 

10K 


D D 

J10 

JTAG14_TMS 

R58 22 

1 

JTAG14_TRST 9 

JTAG14_TDI 

R61 22 

TMS nTRST 

2 

R59 22 

R60 

3 

TDI 4 

4 

1K 

5 

JTAG14_TDO 

R62 22 

Vcc Key 

6 

7 

JTAG14_DECTECTn 

TDO 8 

8 

JTAG14_DECTECTn 9 

R130 22 9 

RTCK 10 

10 

JTAG14_TCK 

R63 22 

11 

C43 

TCK 12 

12 

13 

0.1uF 

EMU0 EMU1 

14 

R483 

NO-POP 

JTAG 

R64 22 

ALT3V3_MASTER_F1F2_EMU1 14 

R65 22 



Embedded_USB 

EVM_5V 

C C 

EMU_2V5 EVM_3V3 



R468 

EM_EMU_TRSTn 

EM_EMU_TRSTn 9 

10K 

EM_TRSTn 

EM_EMU_TCK 


T_TCK 

EM_EMU_TCK 9 


EMU_2V5 

T_TMS 

EM_EMU_TMS 

EM_EMU_TMS 9 

9,41 

3V3_SYS_OKAY 

EM_EMU_DSP_RSTn 

3V3_SYS_OKAY 


PONRSn 

USB_DSP_RSTn 

T_TDI 

T_TDO 

T_EMU0 

EM_EMU_TDI 

EM_EMU_TDO 

ALT3V3_MASTER_F1F2_EMU0 

EM_EMU_TDI 9 

EM_EMU_TDO 9 


R469 

10K 

T_EMU1 



T_TCK_RET 

EM_EMU_TCK_RET 

EM_EMU_TCK_RET 9 

12 EM_EMU_CLK_24MHZ 

EM_EMU_CLK_24MHZ 

CLK_24MHZ 

GND 

EM_EMU_D0 

EM_EMU_D0 9 

B B 

EM_EMU_D1 

EM_EMU_D1 9 

EM_EMU_D2 

EM_EMU_D2 9 

EM_EMU_D3 

EM_EMU_D3 9 

EM_EMU_D4 

EM_EMU_D4 9 

EM_EMU_D5 

EM_EMU_D5 9 

EM_EMU_D6 

EM_EMU_D6 9 

EM_EMU_D7 

EM_EMU_D7 9 

EM_EMU_A0 

EM_EMU_A0 9 

EM_EMU_A1 

EM_EMU_A1 9 

EM_EMU_A2 

EM_EMU_A2 9 

EM_EMU_A3 

EM_EMU_A3 9 

EM_EMU_CE 

EM_EMU_CEn 9 

EM_EMU_RD 

EM_EMU_RDn 9 

EM_EMU_WEn 12 

Embedded_USB 

EM_EMU_WE 

EM_EMU_OE 

EM_EMU_OEn 9 


A 

Title: 



McBSP Mictor 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


9 

9 

9 

9 

9 

0 

A-9

5 

5 

6 

6 

5 

6 

6 

8 

8 

6 

8 

8 

8 

8 

8 

2 

8 

4 

4 

3 

3 

2 

2 

1 

1 


U11B 


JTAG14_DECTECTn 

B16 

B2.IO_1 

VCCIO.B2.1 

A3 

JTAG14_TMS 

C13 

14 PIN JTAG 

B2.IO_2 

VCCIO.B2.2 

A14 

JTAG14_TRST 

A15 

B2.IO_3 

VCCIO.B2.3 

F8 

JTAG14_TCK 

C12 

B2.IO_4 

VCCIO.B2.4 

F9 

D JTAG14_TDO 

B14 

B2.IO_13 

D 

JTAG14_TDI 

D12 

B2.IO_14 

41 3V3_SYS_OKAY 

B13 

B2.IO_15 


C11 

B2.IO_16 



A13 

B2.IO_17 

41 CORE_F1_SYS_OKAY 

D11 

B2.IO_18 

41 CORE_F2_SYS_OKAY 

B12 

B2.IO_19 


E11 

B2.IO_20 

EM_EMU_TRSTn 

A12 

B2.IO_21 

EM_EMU_TCK 

C10 

C44 C45 C46 C47 

B2.IO_22 

EM_EMU_TMS 

B11 

0.1UF 0.1UF 0.1UF 0.1UF 

B2.IO_23 

EM_EMU_TDI 

D10 

B2.IO_24 

EM_EMU_TDO 

A11 

B2.IO_25 

EM_EMU_TCK_RET 

E10 

B2.IO_26 


B10 

EM_EMU_D0 

B2.IO_27 

EM_EMU_D0 

C9 

EM_EMU_D1 

B2.IO_28 

EM_EMU_D1 

A10 

EM_EMU_D2 

B2.IO_29 

EMBEDDED EMU 

EM_EMU_D2 

D9 

EM_EMU_D3 

B2.IO_30 

EM_EMU_D3 

B9 

EM_EMU_D4 

B2.IO_31 

EM_EMU_D4 

E9 

EM_EMU_D5 

B2.IO_32 

EM_EMU_D5 

A9 

EM_EMU_D6 

B2.IO_33 

EM_EMU_D6 

A8 

EM_EMU_D7 

B2.IO_34 

EM_EMU_D7 

B8 

EM_EMU_A0 

EM_EMU_A0 

B2.IO_35 

E8 

EM_EMU_A1 

B2.IO_36 

C EM_EMU_A1 

A7 

C 

EM_EMU_A2 

EM_EMU_A2 

B2.IO_37 

D8 

EM_EMU_A3 

EM_EMU_A3 

B2.IO_38 

B7 

EM_EMU_CEn 

EM_EMU_CEn 

B2.IO_39 

C8 

EM_EMU_OEn 

EM_EMU_OEn 

B2.IO_40 

A6 

B2.IO_41 

EM_EMU_RDn 

E7 

B2.IO_42 

37 ENET_RESETn 

B6 

B2.IO_43 

40 EN_DUT_2V5 

D7 

B2.IO_44 

40 EN_DUT_1V2 

A5 

B2.IO_45 

40 EN_DUT_3V3 

C7 

B2.IO_46 

40 EN_DUT_1V8 

B5 

B2.IO_47 

42 EN_F1_CORE 

E6 

B2.IO_48 

43 EN_F2_CORE 

A4 

B2.IO_49 

D6 

B2.IO_50 

CPLD_FSYNC_CLK 

B4 

B2.IO_51 

EXT_CPLD_FSYNC_BURST 

C6 

B2.IO_52 

CPLD_FRAME_BURST 

C4 

B2.IO_53 

C5 

AMC.ENABLEn 

B2.IO_54 

AMC.ENABLEn 

B3 

B2.IO_55 

D5 

B2.IO_56 

A2 

B2.IO_63 

B1 

B2.IO_64 

SRIO_CLK_EN 

D4 

TP15 

B2.IO_65 

A-10 TMS320C6474 Mezzanine EVM Board Technical Reference 

B B 

BURST_CLK_EN 

TP16 

CPU_CLKS_EN 

TP17 

TP18 

EPM2210GF256C5N 


R445 DS3 

220 RED 


A 

Config Error 



CPLD BANK2 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: Wednesday, October 15, 2008 Sheet 9 o f 45


A-11 

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

F1_NMI0 

F1_NMI1 

F1_NMI2 

F1_HURRICANE_DETz 

ALT_F1_TMS 

ALT_F1_TRST 

ALT_F1_TDI 

ALT_F1_TDO 

ALT_F1_TCK 



F1_GP00_BOOTMODE0 

16 


16 


16 


16 

F1_GP04_LENDIAN 

16 

F1_GP05_L2CONFIG 

16 

F1_GP06 

16 

F1_GP07 

16 

F1_GP08_DEVNUM0 

16 


16 

F1_CORECLKSEL 

16 

F1_DDRSLRATE 

16 

F1_NMI0 

20 

F1_NMI1 

20 

F1_NMI2 

20 

F1_PORz 

20 


19 

F1_RESETSTAT 

20 

F1_XWRSTz 

20 

F1_HITEMPz_IN 

20 

F1_CPLD_ALERT1z 

20 

F1_CPLD_CRIT1z 

20 

ALT_F1_TDO 

19 

ALT_F1_TCK 

19 

ALT_F1_TMS 

19 

ALT_F1_TRST 

19 

ALT_F1_TDI 

19 

CPLD_CLK 

5 


7,16 


7,16 

F1_GP12 

7,16 

F1_GP13 

7,16 

F1_GP14 

7,16 

F1_GP15 

7,16 

Size: 

Date: 

DWG NO 

Revision: 

Sheet o f 

Title: 


A 


511222-0001 

Wednesday, October 15, 2008 10 45 

B 


CPLD BANK3 

CONFIGURATION 

C54 

0.1UF 

C55 

0.1UF 

R439 

220 

C56 

0.1UF 

C53 

0.1UF 

TP9 

R440 

270 

TP10 

TP11 

U11C 


VCCIO.B3.1 

C16 

VCCIO.B3.2 

H11 

VCCIO.B3.3 

J11 

VCCIO.B3.4 

P16 

B3.IO_3 

P14 

B1.IO_12 

M14 

B3.IO_5 

P15 

B3.IO_6 

N13 

B1.IO_13 

N15 

B3.IO_16 

L14 

B3.IO_17 

M15 

B3.IO_67 

D13 

B3.IO_11 

N14 

B3.IO_18 

L13 

B3.IO_19 

M16 

B3.IO_20 

L12 

B3.IO_21 

L15 

B3.IO_22 

L11 

B3.IO_23 

L16 

B3.IO_24 

K14 

B3.IO_25 

K15 

B3.IO_26 

K13 

B3.IO_27 

K16 

B3.IO_28 

K12 

B3.IO_29 

J15 

B3.IO_30 

J14 

B3.IO_31 

J16 

B3.IO_32 

J13 

B3.IO_33 

H16 

B3.IO_34 

H13 

B3.IO_35 

H15 

B3.IO_36 

H14 

B3.IO_37 

G16 

B3.IO_38 

G12 

B3.IO_41 

F16 

B3.IO_42 

G14 

B3.IO_43 

F15 

B3.IO_44 

F11 

B3.IO_47 

E15 

B3.IO_48 

F13 

B3.IO_49 

D16 

B3.IO_51 

D15 

B3.IO_50 

F14 

B3.IO_52 

E12 

B3.IO_55 

D14 

B3.IO_58 

E13 

B3.IO_61 

C15 

B3.IO_64 

C14 

B3.IO_65 

E14 

B3.GLK2 

J12 

B3.GLK3 

H12 

B3.IO_15 

N16 

B1.IO_14 

M13 

B3.IO_39 

G15 

B1.IO_40 

G13 

B3.IO_45 

E16 

B3.IO_46 

F12

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 



U11D 



R456 R457 R458 

10K 10K 10K 

C52 

CPLD.BTSW0 

VCCIO.B4.1 

L8 

14 CPLD.BTSW0 

R1 

0.1UF 

CPLD.BTSW1 

B4.IO_2 

VCCIO.B4.2 

L9 

14 CPLD.BTSW1 

P4 

CPLD.BTSW2 

B4.IO_3 

VCCIO.B4.3 

T3 

U12 

14 CPLD.BTSW2 

T2 

CPLD.BTSW3 

B4.IO_4 

VCCIO.B4.4 

T14 

14 CPLD.BTSW3 

P5 

0 R66 

14 CPLD.BTSW4 

CPLD.BTSW4 

B4.IO_5 

1 

R3 

NO-POP R67 

A0 VCC 8 

CPLD.BTSW5 

B4.IO_6 

2 

D 14 CPLD.BTSW5 

0 R68 

A1 WP 7 

N5 

CPLD.BTSW6 

B4.IO_7 

D 

3 

A2 SCL 

6 

14 CPLD.BTSW6 

R4 

CPLD.BTSW7 

B4.IO_14 

4 

GND SDA 5 EVM_1V8 

14 CPLD.BTSW7 

P6 

14 CPLD.OPTSW0 

CPLD.OPTSW0 

B4.IO_15 

T4 


CPLD.OPTSW1 

B4.IO_16 

N6 

CAT24C256WI-G 


CPLD.OPTSW2 

B4.IO_17 

R5 


CPLD.OPTSW3 

B4.IO_18 

M6 

CONFIGURATION I2C EEPROMS USER EEPROM I2C ADDRESS 0X52 

B4.IO_19 

T5 


R69 

B4.IO_20 

P7 

10K 

B4.IO_21 

R6 


B4.IO_22 

N7 

B4.IO_23 

T6 


B4.IO_24 

M7 

C61 C62 C63 C64 

B4.IO_25 

R7 

0.1UF 0.1UF 0.1UF 0.1UF 

R459 R460 R461 

B4.IO_26 

P8 

10K 10K 10K 

C57 

B4.IO_27 

T7 

0.1UF 

B4.IO_28 

N8 

U13 

B4.IO_29 

R8 

B4.IO_30 

N9 

NO-POP R70 

1 

0 R71 

A0 VCC 8 

B4.IO_31 

T8 

2 

0 R72 

A1 WP 7 

B4.IO_32 

T9 

B4.IO_33 

3 

A2 SCL 

6 

R9 

4 

GND SDA 5 B4.IO_34 

P9 

B4.IO_35 

T10 

B4.IO_36 

C M10 

C 

CAT24C256WI-G 

B4.IO_37 

R10 

Factory EEPROM I2C ADDRESS 0X51 

B4.IO_38 

N10 

B4.IO_39 

T11 

B4.IO_40 

5,20 F1_SCL 

P10 

B4.IO_41 

R11 

B4.IO_42 

5,20 F1_SDA 

M11 

B4.IO_43 

T12 

B4.IO_44 

LED1_F2 

N11 

B4.IO_45 

LED2_F2 

R12 

B4.IO_46 

LED3_F2 

P11 

B4.IO_47 

LED4_F2 

T13 

TP19 

B4.IO_48 

M12 

TP20 

B4.IO_49 

R13 


TP21 

B4.IO_50 

N12 

TP22 

B4.IO_51 

R14 

B4.IO_52 

LED1_F1 

P12 

B4.IO_53 

LED2_F1 

T15 

B4.IO_54 

SW1 

R73 

LED3_F1 

R16 

10K 

B4.IO_63 

A B 

R74 

LED4_F1 

P13 

B4.IO_64 

AA 

BB 

PUSHBUTTON SW 

C58 

B 33 

1uF 

B 

M8 


B4.DEV_OE 

M9 

B4.DEV_CLRn 

R75 

SW2 

10K 


A B 

R76 

AA BB 

PUSHBUTTON SW 

C59 

33 

1uF 

LED_STS3V3 

LED_STS2V5 

LED_STS3V3 41 

LED_STS1V8 

LED_STS2V5 41 

LED_STS1V1 

LED_STS1V8 41 


LED_STSF1CORE 

LED_STS1V1 41 

LED_STSF2CORE 

LED_STSF1CORE 41 

LED_STSF2CORE 41 

SW3 

R77 

A 10K 


A 

R78 

AA 

BB 


PUSHBUTTON SW 

C60 

33 

1uF 


CPLD BANK4 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 

Sheet o f Saturday, October 25, 2008 11 45 

A 

B 

7 

7 

7 

7 

7 

7 

7 

7 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


U11A 


D EVM_1V8 

D 

27 F2_GP00_BOOTMODE0 

D3 

B1.IO_1 

VCCIO.B1.1 

C1 


C2 

B1.IO_2 

VCCIO.B1.2 

H6 


C3 

B1.IO_5 

VCCIO.B1.3 

J6 


E3 

B1.IO_6 

VCCIO.B1.4 

P1 

27 F2_GP04_LENDIAN 

D2 

B1.IO_7 

27 F2_GP05_L2CONFIG 

E4 

B1.IO_8 

27 F2_GP06 

D1 

C48 C49 C50 C51 

B1.IO_9 

27 F2_GP07 

E5 

0.1UF 0.1UF 0.1UF 0.1UF 

B1.IO_10 

27 F2_GP08_DEVNUM0 

E2 

B1.IO_11 

27 F2_GP09_DEVNUM1 

F3 

B1.IO_18 

27 F2_CORECLKSEL 

E1 

B1.IO_19 

27 F2_DDRSLRATE 

F4 

B1.IO_20 

F2 

B1.IO_21 

F5 

F2_NMI0 

B1.IO_22 

31 F2_NMI0 

F1 

F2_NMI1 

B1.IO_23 

31 F2_NMI1 

F6 

F2_NMI2 

B1.IO_24 

31 F2_NMI2 

G2 

B1.IO_25 


G3 

B1.IO_26 

G1 

B1.IO_27 


G4 

B1.IO_28 

H2 

B1.IO_29 

7,27 F2_GP12 

G5 

B1.IO_30 

C H1 

B1.IO_31 

C 

7,27 F2_GP13 

H3 

B1.IO_32 

J1 

B1.IO_33 

7,27 F2_GP14 

H4 

B1.IO_34 

J2 

B1.IO_35 

7,27 F2_GP15 

J4 

B1.IO_36 

K1 

B1.IO_37 

J3 

ALT_F2_TCK 

B1.IO_40 

30 ALT_F2_TCK 

K2 

ALT_F2_TMS 

B1.IO_41 

30 ALT_F2_TMS 

K5 

ALT_F2_TRST 

B1.IO_42 

30 ALT_F2_TRST 

L1 

ALT_F2_TDI 

B1.IO_43 

30 ALT_F2_TDI 

K4 

ALT_F2_TDO 

B1.IO_44 

30 ALT_F2_TDO 

L2 

B1.IO_47 

K3 

B1.IO_48 

31 F2_CPLD_ALERT1z 

M1 

TP12 

B1.IO_49 

31 F2_CPLD_CRIT1z 

L5 

B1.IO_50 

M2 

B1.IO_51 

L4 


B1.IO_52 

30 F2_HURRICANE_DETz 

L3 

B1.IO_54 

N1 

B1.IO_57 

31 F2_RESETSTAT 

M4 

B1.IO_58 

N2 

TP13 

B1.IO_59 

31 F2_HITEMPz_IN 

M3 

B1.IO_60 

31 F2_PORz 

N3 

B1.IO_62 

B 31 F2_XWRSTz 

P2 

B 

B1.IO_65 

ISR_TMS 

TP14 

B1.TMS N4 

ISR_TDI 

B1.TDI 

L6 

ISR_TCK 

B1.TCK P3 

ISR_TDO 

B1.TDO M5 ISR_TCK 

R441 

ISR_TDO 

EM_EMU_CLK_24MHZ 

ISR_TMS 

220 


H5 

B1.GLK0 

J5 


B1.GLK1 

RN1 

J11 

R442 

1 

8 

ISR_TCK 

270 

ISR_TDO 

1 2 

2 

7 

ISR_TMS 

3 4 

3 

6 

5 6 


4 5 

ISR_TDI 

7 8 

9 10 

R443 

RPACK4-10K 

SMT FEMALE HEADER 5X2 

EM_EMU_WEn 

A 220 


A 


R444 

270 


CPLD BANK1 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


A-13

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 


U11E 

F10 

VCCINT.1 

GNDINT.1 

F7 

G11 

VCCINT.2 

GNDINT.2 

G6 

H8 


VCCINT.3 

GNDINT.3 

H7 

H10 

VCCINT.4 

GNDINT.4 

H9 

J7 

VCCINT.5 

GNDINT.5 

J8 

C J9 

VCCINT.6 

GNDINT.6 

J10 

C 

K6 

VCCINT.7 

GNDINT.7 

K11 

L7 

VCCINT.8 

GNDINT.8 

L10 

C65 C66 C67 C68 C69 C70 C71 C72 

0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 

GNDIO.1 

A1 

GNDIO.2 

A16 

GNDIO.3 

B2 

GNDIO.4 

B15 

GNDIO.5 

G7 

GNDIO.6 

G8 

GNDIO.7 

G9 

GNDIO.8 

G10 

GNDIO.9 

K7 

GNDIO.10 

K8 

GNDIO.11 

K9 

GNDIO.12 

K10 

GNDIO.13 

R2 

GNDIO.14 

R15 

B B 

GNDIO.15 

T1 

GNDIO.16 

T16 



A 

Title: 



CPLD POWER PINS 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 




R79 

100K 

C73 

D 0.1uF 

D 

R80 R81 

U14 

1K 

1K 

8 

GATE GND1 

1 


7 

B1 

A1 

2 

R82 


6 

B2 

A2 

3 

ALT_MASTER_F1F2_EMU0 19,30 


5 

B3 

A3 

4 

ALT_MASTER_F1F2_EMU1 19,30 

SN74TVC3306 

C C 

SW4 

ON 

1 8 

CPLD.OPTSW0 

CPLD.OPTSW0 11 

2 7 

CPLD.OPTSW1 


3 6 

CPLD.OPTSW2 


4 5 

CPLD.OPTSW3 


DIP_SWITCH-4 

RN2 

RPACK4-10K 


SW5 

B 16 

1 

CPLD.BTSW0 

CPLD.BTSW0 11 

B 

15 

2 

CPLD.BTSW1 

CPLD.BTSW1 11 

14 

3 

CPLD.BTSW2 

CPLD.BTSW2 11 

13 

4 

CPLD.BTSW3 

CPLD.BTSW3 11 

12 

5 

CPLD.BTSW4 

CPLD.BTSW4 11 

11 

6 

CPLD.BTSW5 

CPLD.BTSW5 11 

10 

7 

CPLD.BTSW6 

CPLD.BTSW6 11 

9 

8 

CPLD.BTSW7 

CPLD.BTSW7 11 

SW DIP-8 

RN3 

RPACK8-10K 



A 

Title: 



BOOT SWITCHES/ EMU PINS VOLTAGE SHIFTER 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


8 

8 

1 

2 

3 

4 

0 

9 

10 

11 

12 

13 

14 

15 

16 

1 

2 

3 

4 

5 

6 

7 

8 

5 

6 

7 

8 

1 

2 

3 

4 

A-15

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


F1_DDRD[0:31] 

F1_DDRD[0:31] 17 

F1_DDRA[0:13] 

F1_DDRA[0:13] 17 

F1_DDRD[0:31] 

EVM_1V8 EVM_1V8 

F1_DDRD[0:31] 17 


U15 

U16 

F1_DDRA13 F1_DDRA13 

NC/A13 

V8 

V8 

F1_DDRA12 

F1_DDRA12 

NC/A13 

M9 

VDD 

A12 

V2 

V2 

F1_DDRA11 

F1_DDRA11 

A12 

VDD M9 

H1 

VDD 

A11 

U7 

U7 

F1_DDRA10 

F1_DDRA10 

A11 

VDD H1 

R9 

R2 

D R133 

VDD 

A10 

R2 

F1_DDRA9 

F1_DDRA9 

A10 

VDD R9 

D 

D1 

U3 

1K 

C97 

VDD 

A9 

U3 

F1_DDRA8 

F1_DDRA8 

A9 

VDD D1 

V1 

U8 

0.1UF 

VDD 

A8 

U8 

F1_DDRA7 

F1_DDRA7 

A8 

VDD V1 

F3 

VDDQ 

A7 

U2 

U2 

F1_DDRA6 

F1_DDRA6 

A7 

VDDQ F3 

F7 

F1_DDR_VREF 

VDDQ 

A6 

T7 

T7 

F1_DDRA5 

F1_DDRA5 

A6 

VDDQ F7 

K1 

VDDQ 

A5 

T3 

T3 

A5 

VDDQ K1 

K3 

VDDQ 

VDDQ K3 

K7 

F1_DDR_VREF 

VDDQ 

VDDQ K7 

K9 

F1_DDR_VREF 

R138 

VDDQ 

F1_DDRA4 

F1_DDRA4 

VDDQ K9 

D9 

T8 

1K 

VDDQ 

A4 

T8 

F1_DDRA3 

F1_DDRA3 

A4 

VDDQ D9 

F1 

T2 

C98 

VDDQ 

A3 

T2 

F1_DDRA2 

F1_DDRA2 

A3 

VDDQ F1 

F9 

R7 

0.1UF 

VDDQ 

A2 

R7 

F1_DDRA1 

F1_DDRA1 

A2 

VDDQ F9 

H9 

R3 

C75 

F1_DDRA0 

F1_DDRA0 

A1 

VDDQ H9 

C74 

VDDQ 

A1 

R3 

R8 

0.1UF 

0.1UF 

A0 

R8 

F1_DDRBA2 

F1_DDRBA2 

A0 

BA2 

P1 

P1 

F1_DDRBA1 

F1_DDRBA1 

BA2 

M1 

VDDL 

BA1 

P3 

P3 

F1_DDRBA0 

F1_DDRBA0 

BA1 

VDDL 

M1 

BA0 

P2 

P2 

BA0 

M2 

VREF 

VREF 

M2 

RN30 RPACK4-22 

NC1 

AA9 

AA9 

NC1 

AA8 


F1_DDRD31 

F1_TDDRD31 

F1_TDDRD31 

NC2 

AA8 

NC2 

5 4 

E9 

F1_TDDRD15 F1_TDDRD15 

F1_DDRD15 

F1_DDRD29 

F1_TDDRD29 

F1_TDDRD30 

DQ15 

NC3 

AA2 

AA2 

NC3 

DQ15 

E9 

8 1 

6 3 

E1 


F1_DDRD13 

F1_DDRD26 

F1_TDDRD26 

F1_TDDRD29 

DQ14 

NC4 

AA1 Layout for the 92-ball DDR 

AA1 

NC4 

DQ14 

E1 

7 2 

7 2 

G9 


F1_DDRD10 

F1_DDRD24 

F1_TDDRD24 

F1_TDDRD28 

DQ13 

NC5 

D2 Package but populate the 

D2 

NC5 

DQ13 

G9 

6 3 


F1_DDRD8 

C 8 1 

G1 

DQ12 

C 

84-ball MT47H64M16HR-3:E. 

DQ12 

G1 

5 4 

F1_DDRD30 

F1_TDDRD30 

F1_TDDRD27 

NC7 

A9 

A9 

NC7 

5 4 

G3 

84 Ball memories reside in 

R83 

A8 


F1_DDRD14 

F1_DDRD28 

F1_TDDRD28 

F1_TDDRD26 

DQ11 

NC8 

A8 

NC8 

DQ11 

G3 

8 1 

6 3 

G7 

DNP_0603 A2 


F1_DDRD12 

F1_DDRD27 

F1_TDDRD27 

F1_TDDRD25 

DQ10 

NC9 

A2 

the center section of the 92 

NC9 

DQ10 

G7 

7 2 

7 2 

F2 

A1 

F1_TDDRD9 

F1_TDDRD11 

F1_DDRD11 

F1_DDRD25 

F1_TDDRD25 

F1_TDDRD24 

DQ9 

NC10 

A1 

NC10 

DQ9 

F2 

6 3 

8 1 

F8 

Ball Package 

H2 

F1_TDDRD8 

F1_TDDRD9 

F1_DDRD9 

NC11 

DQ8 

F8 


DQ8 

NC11 

H2 

5 4 




F1_DDRD23 5 4 F1_TDDRD23 

F1_TDDRD23 J9 

F1_TDDRD7 

F1_TDDRD7 

F1_DDRD7 

F1_DDRD21 

F1_TDDRD21 

F1_TDDRD22 

DQ7 

DQ7 

J9 

8 1 

6 3 

J1 

V3 

F1_TDDRD6 

F1_TDDRD5 

F1_DDRD5 

F1_DDRD18 

F1_TDDRD18 

F1_TDDRD21 

DQ6 

RFU V3 

RFU 

DQ6 

J1 

7 2 

7 2 

L9 

V7 

F1_TDDRD5 

F1_TDDRD2 

F1_DDRD2 

F1_DDRD16 

F1_TDDRD16 

F1_TDDRD20 

DQ5 

RFU V7 

RFU 

DQ5 

L9 

6 3 

8 1 

L1 

N9 

F1_TDDRD4 

F1_TDDRD0 

F1_DDRD0 

DQ4 

ODT 

N9 

ODT 

DQ4 

L1 

5 4 

F1_DDRD22 8 1 F1_TDDRD22 

F1_TDDRD19 L3 

F1_TDDRD3 

F1_TDDRD6 

F1_DDRD6 

F1_DDRD20 

F1_TDDRD20 

F1_TDDRD18 

DQ3 

DQ3 

L3 

8 1 

7 2 

L7 

F1_TDDRD2 

F1_TDDRD4 

F1_DDRD4 

F1_DDRD19 

F1_TDDRD19 

F1_TDDRD17 

DQ2 

DQ2 

L7 

7 2 

6 3 

K2 

F1_TDDRD1 

F1_TDDRD3 

F1_DDRD3 

F1_DDRD17 

F1_TDDRD17 

F1_TDDRD16 

DQ1 

CS# 

P8 

P8 

CS# 

DQ1 

K2 

6 3 

5 4 

K8 

F1_TDDRD0 

F1_TDDRD1 

F1_DDRD1 

DQ0 

CAS# 

P7 

P7 

CAS# 

DQ0 

K8 

5 4 


RAS# 

N7 

N7 

RAS# 

N3 


WE# 

N3 

WE# 

U9 



VSS 

CKE N2 

N2 

CKE 

VSS U9 

T1 

VSS 

VSS T1 

H3 

VSS 

F1_DDRCLKOUTP1 


VSS H3 

D3 

VSS 

CK M8 

M8 

F1_DDRCLKOUTN1 


CK 

VSS D3 

M3 

N8 

B + C77 

CK# 

VSS M3 

+ C76 

VSS 

CK# 

N8 

G8 

C81 

B 

10UF 

C83 C84 C85 

VSSQ G8 

10UF C78 C79 C80 

C82 

VSSQ 

J8 

0.1UF 

0.1UF 0.1UF 0.1UF 

VSSQ J8 

0.1UF 0.1UF 0.1UF 

0.1UF 

VSSQ 

D7 

VSSQ UDQS#/NU D8 

D8 

UDQS#/NU VSSQ D7 

J2 

VSSQ 

UDQS E7 

E7 

UDQS 

VSSQ J2 

E2 

VSSQ LDQS#/NU H8 

H8 

LDQS#/NU VSSQ E2 

L8 

VSSQ 

LDQS J7 

J7 

LDQS 

VSSQ L8 

L2 



VSSQ 

VSSQ L2 

E8 

VSSQ 

VSSQ E8 

H7 

VSSQ 

UDM E3 

E3 

UDM 

VSSQ H7 

G2 

VSSQ 

LDM J3 

J3 

LDM 

VSSQ G2 

M7 

VSSDL 

VSSDL 

M7 

C86 C87 C88 C89 

C90 C91 C92 C93 

560PF 560PF 560PF 560PF 

560PF 560PF 560PF 560PF 

MT47H64M16HR-3:E 


RN8 

RN9 

F1_TDDRDQS2P 

F1_TDDRDQS0P 

17 F1_DDRDQS2P 

5 4 

8 1 

F1_DDRDQS0P 17 

F1_TDDRDQS2N 

F1_TDDRDQS0N 

17 F1_DDRDQS2N 

6 3 

7 2 

F1_DDRDQS0N 17 

F1_TDDRDQS3P F1_TDDRDQS1P 


7 2 

6 3 


F1_TDDRDQS3N 

F1_TDDRDQS1N 


8 1 

5 4 



A 

RPACK4-22 

RPACK4-22 

A-16 TMS320C6474 Mezzanine EVM Board Technical Reference 

F1_DDRDQM0 17 

F1_DDRDQM1 17 

F1_DDRDQM2 

F1_DDRDQM3 

17 

17 



C6474 CPU-1: DDR2 

F1_DDRBA0 17 

F1_DDRBA1 17 

F1_DDRBA2 17 



17 

17 

Revision: 

DWG NO 511222-0001 

A 

45 

Sheet o f Wednesday, October 15, 2008 15 F1_DDRCLKOUTN0 17 

F1_DDRCLKOUTP0 17 

Size: B 

Date: 

F1_DDRODT 17 

17 F1_DDRCKEz 

17 F1_DDRWEz 

17 F1_DDRRASz 

17 F1_DDRCASz 

17 F1_DDRCSz

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

F_DVDD_18 F_DVDD_18 

R88 DNP 

R89 DNP R90 DNP 

R91 DNP 

R92 DNP 


R95 DNP 

R96 DNP 


R99 DNP 

R100 DNP 


R103 DNP 

R104 DNP 

R105 DNP 

U17G 

R106 DNP 

R107 DNP 


F1_CLKR0_F2_CLKX0 B20 



CLKR0 GP00/BOOTM0 

T3 

F1_GP00_BOOTMODE0 10 

7,27 F1_FSR0_F2_FSX0 

B21 


F1_DR0_F2_DX0 

FSR0 

GP01/BOOTM1 

U4 


7,27 F1_DR0_F2_DX0 

A20 



F1_CLKX0_F2_CLKR0 

DR0 

GP02/BOOTM2 

V1 


C20 



7,27 F1_FSX0_F2_FSR0 


CLKX0 

GP03/BOOTM3 

U3 

A21 

F1_DX0_F2_DR0 

FSX0 


C 7,27 F1_DX0_F2_DR0 

D19 

DX0 

GP04/LENDIAN T4 

F1_GP04_LENDIAN 10 

C 


F1_GP05_L2CONFIG 10 

F1_CLKS0 

F1_CLKS0 

GP05/L2_CONFIG V2 

D20 

F1_GP06 

CLKS0 

GP06 

V3 

F1_GP06 10 

F1_GP07 

GP07 

Y3 

F1_GP07 10 

F1_CLKR1 

F1_CLKR1 

A24 


F1_FSR1 

CLKR1 GP08/DEVNUM0 

Y4 

F1_GP08_DEVNUM0 10 

F1_FSR1 

C21 


F1_DR1 

FSR1 GP09/DEVNUM1 

AA2 


F1_DR1 

D21 



F1_CLKX1 

DR1 

GP10/DEVNUM2 

AA3 

F1_CLKX1 

C22 



F1_FSX1 

F1_FSX1 

CLKX1 GP11/DEVNUM3 

AB4 

A22 

F1_DX1 

F1_DX1 

FSX1 

B22 

F1_GP12 

DX1 

GP12 

AB3 

F1_GP12 7,10 

F1_GP13 

F1_GP13 7,10 

F1_CLKS1 

F1_CLKS1 

GP13 

AB2 

A25 

F1_GP14 

CLKS1 

GP14 

AA4 

F1_GP14 7,10 

F1_GP15 

GP15 

AC3 

F1_GP15 7,10 

F1_CORECLKSEL 

CORECLKSEL 

AF7 

F1_CORECLKSEL 10 

F1_DDRSLRATE 

F1_DDRSLRATE 10 


F_DVDD_18 

R108 DNP 

R109 DNP 

B B 

R110 DNP 

R111 DNP 

R112 DNP 

R113 DNP 

R114 DNP 

R115 DNP 

R116 DNP 

R117 DNP 

R118 DNP 

R119 DNP 

DDRSLRATE AE23 R120 DNP 

R121 DNP 

R122 DNP 

R123 DNP 


A 

Title: 



C6474 CPU-1: McBSP, GPIO, CONFIG 

Revision: 

Size: B 

DWG NO 511222-0001 

A 


7 

7 

7 

7 

7 

7 

7 

7 

A-17

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


F1_DDRA[0:13] 

F1_DDRA[0:13] 15 

DDRA0_F1 

R126 22 

F1_DDRA0 

DDRA8_F1 

R127 22 

F1_DDRA8 

F1_DDRD[0:31] 


15 F1_DDRD[0:31] 

DDRA13_F1 5 4 

F1_DDRA13 

DDRA4_F1 

F1_DDRA4 

U17B 

6 3 

DDRA6_F1 7 2 

F1_DDRA6 

F1_DDRD0 W27 

DDRA0_F1 

DDRA11_F1 

F1_DDRA11 

D F1_DDRD1 

DDRD00 

DDRA00 

K25 

8 1 

DDRA1_F1 

D 

W25 

F1_DDRD2 

DDRD01 

DDRA01 

N25 

Y27 

DDRA2_F1 

F1_DDRD3 

DDRD02 

DDRA02 

M25 

W26 

DDRA3_F1 

F1_DDRD4 

DDRD03 

DDRA03 

R26 

AA27 

DDRA4_F1 

F1_DDRD5 

DDRD04 

DDRA04 

L25 

AA26 

DDRA5_F1 

DDRA2_F1 

F1_DDRA2 

F1_DDRD6 

DDRD05 

DDRA05 

N27 

9 8 

AA25 

DDRA6_F1 

DDRA1_F1 

F1_DDRA1 

F1_DDRD7 

DDRD06 

DDRA06 

L26 

10 7 

AA24 

DDRA7_F1 

DDRA5_F1 

F1_DDRA5 

DDRD07 

DDRA07 

U26 

11 6 

DDRA10_F1 12 5 

F1_DDRA10 

DDRA3_F1 13 4 

F1_DDRA3 

DDRA9_F1 14 3 

F1_DDRA9 

F1_DDRD8 AC27 

DDRA8_F1 

DDRA7_F1 

F1_DDRA7 

F1_DDRD9 

DDRD08 

DDRA08 

K26 

15 2 

AC26 

DDRA9_F1 

DDRA12_F1 

F1_DDRA12 

F1_DDRD10 

DDRD09 

DDRA09 

R27 

16 1 

AC25 

DDRA10_F1 

F1_DDRD11 

DDRD10 

DDRA10 

P25 

AD27 

DDRA11_F1 

F1_DDRD12 

DDRA11 

L27 


DDRD11 

AC24 

DDRA12_F1 


F1_DDRD13 

DDRD12 

DDRA12 

U27 

AE26 

DDRA13_F1 

DDRBA2_F1 16 1 

F1_DDRBA2 

F1_DDRBA2 15 

F1_DDRD14 

DDRD13 

DDRA13 

K27 

AE27 

DDRBA0_F1 


F1_DDRBA0 

F1_DDRBA0 15 

F1_DDRD15 

DDRD14 

DDRBA0 

T25 

AE25 

DDRBA1_F1 

DDRCKE_F1 

DDRD15 

DDRBA1 

R25 

14 3 

F1_DDRCKEz 15 

DDRBA2_F1 


F1_DDRBA1 

DDRBA2 

U25 

F1_DDRBA1 15 

DDRWE_F1 12 5 

F1_DDRWEz 15 

DDRCAS_F1 11 6 

F1_DDRCASz 15 

F1_DDRD16 B25 

DDRCE_F1 

DDRRAS_F1 10 7 

F1_DDRRASz 15 

F1_DDRD17 

DDRD16 

DDRCEz 

L24 

D25 

DDRCE_F1 9 8 

F_DVDD_18 

F1_DDRCSz 15 

F1_DDRD18 

DDRD17 

C B26 

C 

F1_DDRD19 

DDRD18 

DDRODT 

K24 

D24 

F1_DDRD20 

DDRD19 

B27 

R124 22 

F1_DDRODT 15 

F1_DDRD21 

DDRD20 

D26 

F1_DDRD22 

DDRD21 

D27 

R125 

F1_DDRD23 

DDRD22 

VREFSSTL 

T26 

C94 

C27 

1K 

0.1UF 

DDRD23 

F1_DDRD24 F24 

DDRCAS_F1 

F1_DDRD25 

DDRD24 

DDRCASz 

N26 

F25 

DDRRAS_F1 

F1_DDRD26 

DDRD25 

DDRRASz 

M24 

F26 

DDRWE_F1 

F1_VREFSSTL 

F1_DDRD27 

DDRD26 

DDRWEz 

P24 

F27 

DDRCKE_F1 

F1_DDRD28 

DDRD27 

DDRCKE T24 

G27 

F1_DDRD29 

DDRD28 

H25 

C95 

F1_DDRD30 

DDRD29 

H26 

0.1UF 

F1_DDRD31 

DDRD30 

H27 

DDRD31 

DDRDQS0P Y26 


DDRDQS0N Y25 


DDRDQS1P AD26 

R131 


C96 


22 R84 

DDRDQS1N AD25 

1K 

0.1UF 

15 F1_DDRDQM0 

W24 

22 R85 

DDRDQM0 

15 F1_DDRDQM1 

AE24 

22 R86 

DDRDQM1 

15 F1_DDRDQM2 

B24 

22 R87 

DDRDQM2 

15 F1_DDRDQM3 

H24 

DDRDQM3 DDRDQS2P C26 


B F1_DDRDQS2N 15 

B 

DDRDQS2N C25 

DDRDQS3P G25 



10 R134 

F1_DDRRCVENOUT0 

DDRDQS3N G26 

AB24 

DDRRCVENOUT0 

AB25 

DDRRCVENIN0 

E25 

10 R135 


DDRRCVENOUT1 

E24 

F1_TDDRCLKOUTP0 

DDRRCVENIN1 DDRCLKOUTP0 

V25 

R136 22 


F1_TDDRCLKOUTN0 R137 22 

DDRCLKOUTN0 

V24 

F1_DDRCLKOUTN0 15 

F1_TDDRCLKOUTP1 R139 22 

DDRCLKOUTP1 

J25 


F1_TDDRCLKOUTN1 

DDRCLKOUTN1 

J24 

R140 22 



NOTE: Route DDRRCVENOUT0 signals needs to 

run to DDR memories near D31-D16 and back to DDRRCVENIN0 




A 

Title: 



C6474 CPU-1: DDR2 interface 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


F_DVDD_18 

R141 AND R143 POPULATED FOR DEBUG PURPOSES ONLY ( 100 OHM ). 

REMOVE WHEN C6474 DEVICE IS INSTALLED 

R19 

10K 

R141 NO-POP 

U17F 

F1_FSYNCCLKP 

D F1_FSYNC_CLKP 

AD7 

33 R142 

F1_FSYNCCLKN 

FSYNCCLKP SMFRAMECLK AD4 

F1_SMFRAMECLK 7 

D 

F1_FSYNC_CLKN 

AD8 

R143 NO-POP 

FSYNCCLKN 

F1_FRAMEBURSTP 


AD9 

R20 

F1_FRAMEBURSTN 

FRAMEBURSTP 

10K 


AD10 

FRAMEBURSTN 

F1_FSYNC_CLK 

AF6 

ALTFSYNCCLK 

F1_SYNC_BURST 

AE6 

R144 0 

ALTFSYNCPULSE 

7,20 F1_TIMO0 

F1_TRTCLK 

AC4 

TRTCLK 

F1_TRT 

AD3 

TRT 

AE19 

RESV.1 

AD14 

RESV.2 

F1_AIFRXN3 

F1_AIFRXN3 AE17 

F1_AIFRXN0 

F1_AIFRXP3 

AIFRXN3 

AIFRXN0 

AF22 

F1_AIFRXP3 

AE18 

F1_AIFRXP0 

F1_AIFTXP3 

F1_AIFTXP3 

AIFRXP3 

AIFRXP0 

AF21 

AD16 

F1_AIFTXP0 

F1_AIFTXN3 

F1_AIFTXN3 

AIFTXP3 

AIFTXP0 

AE22 

AD17 

F1_AIFTXN0 

AIFTXN3 

AIFTXN0 

AE21 

F1_AIFRXN4 

F1_AIFRXN4 

AE14 

F1_AIFRXN1 

F1_AIFRXP4 

AIFRXN4 

AIFRXN1 

AG20 

F1_AIFRXN1 4 

F1_AIFRXP1 

C F1_AIFRXP4 

AE13 

F1_AIFRXP1 4 

C 

F1_AIFTXP4 

F1_AIFTXP4 

AIFRXP4 

AIFRXP1 

AG21 

AG14 

F1_AIFTXP1 

F1_AIFTXP1 4 

F1_AIFTXN4 

F1_AIFTXN4 

AIFTXP4 

AIFTXP1 

AD20 

AG13 

F1_AIFTXN1 

AIFTXN4 

AIFTXN1 

AD21 

F1_AIFTXN1 4 

F1_AIFRXN5 

F1_AIFRXN5 

AF12 

F1_AIFRXN2 

F1_AIFRXP5 

AIFRXN5 

AIFRXN2 

AG18 

F1_AIFRXN2 4 

F1_AIFRXP5 

AF13 

F1_AIFRXP2 

F1_AIFRXP2 4 

F1_AIFTXP5 

F1_AIFTXP5 

AIFRXP5 

AIFRXP2 

AG17 

AD12 

F1_AIFTXP2 

F1_AIFTXP2 4 

F1_AIFTXN5 

F1_AIFTXN5 

AIFTXP5 

AIFTXP2 

AF17 

AD13 

F1_AIFTXN2 

AIFTXN5 

AIFTXN2 

AF16 

F1_AIFTXN2 4 


B B 

F1_AIFTXP0 

R145 0 F1_AIFTXP0_SMA 

F1_AIFTXP0_SMA 4 

F1_AIFTXN0 

R146 0 F1_AIFTXN0_SMA 

F1_AIFTXN0_SMA 4 

C500 

F1_AIFRXP0 

F2_AIFTXP0 

F2_AIFTXP0 29 

0.1uF 

C501 

F1_AIFRXN0 

F2_AIFTXN0 

F2_AIFTXN0 29 

0.1uF 


A 

Title: 



C6474 CPU-1: AIF and FSYNC Interfaces 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


5 

5 

6 

6 

7 

7 

7 

7 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

A-19

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


U17A 



G4 

F3 

RESV.21 

RESV.22 

EMU21 

EMU20 

K1 

K3 

R150 

100 

R149 

4.75K 

NOTE: TCLKRTN line must be 1 in. 

NOTE: ALL Traces MUST not exceed a maxium of length of 2 in. 


F1_HURRICANE_DETz 10 

J13 

D F1_EMU19 

D 

K4 

B1 

F1_EMU19 

ID0 

NC D1 

NO-POP R151 

EMU19 

A1 

F1_EMU18 

F1_TMS_BUF 

F1_TMS 43 R152 F1_TMS_T 

GND* 

ID2 

C1 

M3 

EMU18 

TMS W1 

B2 

TMS 

GND D2 

A2 

F1_EMU18_T 

F1_EMU18 

F1_TRST_BUF 

F1_EMU17 

F1_EMU17 43 R154 F1_EMU17_T 

GND 

EMU18 

C2 

43 R153 

W2 

TRSTz 

EMU17 

L4 

B3 

EMU17 

GND D3 

A3 

F1_TRST_T 43 R155 F1_TRST 

F1_EMU16 

F1_TDI_BUF 

F1_TDI 

F1_TDI_T 

GND 

TRST 

C3 

P3 

TDI 

V4 

43 R156 

EMU16 

B4 

TDI 

GND D4 

A4 

F1_EMU16_T 

F1_EMU16 

F1_EMU15 

F1_EMU14 

F1_EMU14 

F1_EMU14_T 

GND 

EMU16 

C4 

43 R157 

T1 

EMU14 

K2 

43 R158 

EMU15 

B5 

EMU14 

GND D5 

A5 

F1_EMU15_T 

F1_EMU15 

F1_EMU13 

F1_EMU12 

F1_EMU12 

F1_EMU12_T 

GND 

EMU15 

C5 

43 R159 

P4 

EMU12 

L3 

43 R160 

EMU13 

B6 

EMU12 

GND D6 

A6 

F1_EMU13_T 43 R161 F1_EMU13 

F1_EMU11 

F1_TDO 

F1_TDO_BUF 43 R162 F1_TDO_T 

GND 

EMU13 

C6 

T2 

EMU11 

TDO W3 

B7 

TDO 

GND D7 

A7 

F1_EMU11_T 

F1_EMU11 

GND 

EMU11 

C7 

43 R163 

B8 

F1_TRST 

TVD 

Type 1 

D8 

NO-POP R164 

A8 

F1_TCLKRET_T 22 R165 F1_TCLKRET 

F1_EMU10 

F1_EMU9 

F1_EMU9 

F1_EMU9_T 

Type 0 TCLKRTN C8 

R1 

EMU09 

N2 

43 R166 

EMU10 

B9 

EMU9 

GND D9 

A9 

F1_EMU10_T 

F1_EMU10 

F1_EMU8 

F1_EMU7 

F1_EMU7 43 R168 F1_EMU7_T 

GND 

EMU10 

C9 

43 R167 

M4 

EMU08 

EMU07 

R3 

B10 

EMU7 

GND D10 

A10 

F1_EMU8_T 43 R169 F1_EMU8 

F1_EMU6 

F1_EMU5 

F1_EMU5 

F1_EMU5_T 

GND 

EMU8 

C10 

N4 

EMU05 

M1 

43 R170 

EMU06 

B11 

EMU5 

GND D11 

A11 

F1_EMU6_T 43 R171 F1_EMU6 

F1_EMU4 

F1_TCK_BUF 

F1_TCK 

F1_TCK_T 

GND 

EMU6 

C11 

M2 

TCK W4 

43 R172 

EMU04 

B12 

TCLK 

GND D12 

F1_EMU4_T 

F1_EMU4 

C A12 

C 

F1_EMU3 

F1_EMU2 

F1_EMU2 

F1_EMU2_T 

GND 

EMU4 

C12 

43 R173 

N1 

EMU03 

EMU02 

N3 

43 R174 

B13 

EMU2 

GND D13 

A13 

F1_EMU3_T 

F1_EMU3 

F1_EMU1 

F1_EMU0 

F1_EMU0 

F1_EMU0_T 

GND 

EMU3 

C13 

43 R175 

R2 

EMU01 

EMU00 

R4 

43 R176 

B14 

EMU0 

GND D14 

A14 

F1_EMU1_T 

F1_EMU1 

GND 

EMU1 

C14 

43 R177 

B15 

F_DVDD_18 

C99 

ID1 

GND D15 

A15 

OUT 

ID3 

C15 

6.8pF 


Emulation Header 

R178 

NO-POP 

R179 

NO-POP 

TERMINATION AT PIN FOR TCLK 

R180 

49.9 1% 


C604 

0.1UF 


14,30 ALT_MASTER_F1F2_EMU1 

2 

U19 

F1_TDI 

2 

F1_TDI_BUF 

C102 

ALT_F1_TDI 

1A0 1Y0 

18 

R184 33 

0.1uF 

10 ALT_F1_TDI 

17 

2A3 2Y3 

3 

4 F1_EMU1 

U51 

SN74CBTLV1G125DCKR 

B F1_TCK 

4 

F1_TCK_BUF 

B 

ALT_F1_TCK 

1A1 1Y1 

16 

10 ALT_F1_TCK 

15 

2A2 2Y2 

5 

F1_TCK 2 

4 F1_TCLKRET 

F1_TMS 

6 

F1_TMS_BUF 


ALT_F1_TMS 

1A2 1Y2 

14 

R182 33 

10 ALT_F1_TMS 

13 

2A1 2Y1 

7 

U20 

F1_TRST 

8 

F1_TRST_BUF 

C100 

ALT_F1_TRST 

1A3 1Y3 

12 

R181 33 

SN74AUC1G125 


0.1UF 


11 

2A0 2Y0 

9 

R183 33 


VCC 20 

1OE 2OE GND 10 

C101 

74AUC244PW 

0.1UF 


EVM_1V8 14,30 ALT_MASTER_F1F2_EMU0 

2 

C603 

0.1uF 

4 

F1_EMU0 

U52 


U21 


4 

F1_HURRICANE_DET 

C103 

VCC 5 

0.1UF 

U56 

A SN74AHC1G14 


A 


F1_TDO_BUF 

A Y0 

6 

F1_TDO 3 


E Y1 

4 

33 R185 

ALT_F1_TDO 10 

3 

5 

1 

3 

5 

3 

1 

5 

1 

3 

5 


F1_HURRICANE_DET 19 

R487 

NO-POP 

R486 

NO-POP 


C6474 CPU-1: Emulation Interface 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

SN74AUC1G19 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


R186 NO-POP 

U17D 

F1_NMI0 

10 F1_NMI0 

J4 

F1_RESETSTAT 10 

F1_NMI1 

NMI0 

RESETSTATz 

AF4 

10 F1_NMI1 

J2 

F1_NMI2 

NMI1 

10 F1_NMI2 

J1 

NMI2 

F1_PORz 

10 F1_PORz 

AE5 

F1_XWRSTz 

PORz 

D 10 F1_XWRSTz 

AD5 

XWRSTz 

TIMI0 

E3 

F1_TIMI0 7 

D 

TIMI1 

C4 

F1_TIMI1 7 

22 R187 

TIMO0 

F2 

F1_TIMO0 7,18 

TIMO1 

F4 

22 R188 

F1_TIMO1 7 

F1_PTV18 N24 

RESV.27(NC) 

D5 NO-POP R189 

PTV18 

NO-POP 

RESV.28(NC) 

C5 

AG10 

R191 

RESV.3 

AG24 

C104 

45.3 1% 

RESV.4 

RESV.7(GND) 

D22 

NO-POP 

RESV.8(GND) 

C23 

RN12 

RPACK4-10K 

VCNTL0 

G3 

F1_VCNTL0 42 

D7 

RESV.5(GND) 

VCNTL1 

G2 

F1_VCNTL1 42 

C7 

RESV.6(GND) 

VCNTL2 

H4 

F1_VCNTL2 42 

VCNTL3 

H3 

F1_VCNTL3 42 

5 

6 

7 

8 

1 

2 

3 

4 

HITEMPz 

J3 

F1_HITEMPz_IN 10 


SCL 

E4 

SDA D4 


F1_SCL 5,11 

F1_SDA 5,11 

R190 

DUT_3V3 

C C 

R192 R193 


U22 

4.75K 4.75K 


1 

VDD 

ALERTz 

6 

F1_CPLD_ALERT1z 10 

2 

R462 R463 R464 

D+ 

3 

D- T_CRIT_Az 

4 

F1_CPLD_CRIT1z 10 

NO-POP NO-POP NO-POP 

R194 R195 

F1_3V3_SCL 8 

C105 4.75K 4.75K 

F1_3V3_SDA 

CLK 

7 

0.1UF 

DATA GND 5 

U23 

NO-POP 

R196 0 

1 

R197 0 

A0 VCC 8 

2 

R198 0 

A1 WP 7 

3 

A2 SCL 

6 

4 

GND SDA 5 

AT24C1024W-10SU-2.7 

C6474 CPU-1: I2C EEPROM 

B B 

JP4 

4 3 

2 1 

DUT_3V3 

HDR_2X2 

DUT_3V3 DUT_3V3 

R199 

229K 

F_DVDD_18 

2 

U24 

VREF1 VREF2 

7 

EN_9306 

R200 

4.75K 

R201 

4.75K 

F1_SCL 3 

F1_3V3_SCL 

F1_SDA 

SCL1 SCL2 

6 

F1_3V3_SCL 5 

4 

F1_3V3_SDA 

SDA1 SDA2 

5 

F1_3V3_SDA 5 

EN_9306 

8 

EN GND 1 

PCA9306 

C106 

0.1UF 


A 

Title: 



C6474 CPU-1: I2C,Timer,VCNTL,Reset/NMI,Misc Test 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


A-21

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

R202 AND R203 POPULATED FOR DEBUG PURPOSES ONLY ( 100 OHM ). 


R202 NO-POP 

F1_SYSCLK_P 

C107 

0.01UF 

Place on the trace with minimum stubs as close 

as possible to the c6474 pins on the top layer 

C108 

F1_SYSCLK_N 

0.01UF 

R203 NO-POP 

U17C 

TP4 

C109 

F1_SYSCLKP_T 


AE9 

0.01UF 

F1_SYSCLKN_T 

SYSCLKP 

AE10 

F1_SYSCLKOUT 

F1_ALTCORECLKP_T 

SYSCLKOUT 

AD6 33 R204 

SYSCLKN 

AF9 

C110 

F1_ALTCORECLKN_T 

ALTCORECLKP 


AF10 

RESV.11 

AE4 

0.01UF 

ALTCORECLKN 

C111 

F1_DDRCLKP_T 

RESV.12 

AG25 

C F1_DDRCLK_P 

AD24 

C 

0.01UF 

F1_DDRCLKN_T 

DDRREFCLKP 

AD23 

DDRREFCLKN 

F1_DDRCLK_N 

C112 

0.01UF 

R205 

D6 

RESV.9 

C6 

F_DVDD_18 

RESV.10 

NO-POP 

E1 

R205 POPULATED FOR DEBUG PURPOSES ONLY. 


AE7 

AE8 

AF24 

AF25 

RESV.13 

RESV.14 

RESV.15 

RESV.16 

AVDD1_18 

AVDD2_18 

AG9 

AG23 

F1_AVDD1 

C113 

0.01UF 

C114 

0.1UF 

3 

OUT 

IN 1 

GND 2 

NFM18CC223R1C3 

C115 

0.1UF 


E2 

B F1_AVDD2 

3 

B 

OUT IN 1 

C116 C117 

GND 2 

C118 

0.01UF 0.1UF NFM18CC223R1C3 

0.1UF 


A 

Title: 



C6474 CPU-1: PLLs 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


5 

5 

5 

5 

5 

5 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


R206 FOR POPULATE FOR DEBUG PURPOSES ONLY( 100 OHM ). 


U17E 

F1_RIORXN1 

F1_RIORXN1 3 

C119 0.01UF 

RIORXN1 

A13 

F1_RIORXP1 

D F1_RIOSGMIICLKP 

F1_RIORXP1 3 

R206 NO-POP 

RIORXP1 

A12 

F1_RIOTXP1 

D 

RIOTXP1 

C14 

F1_RIOTXP1 3 

F1_RIOTXN1 

F1_RIOTXN1 3 

F1_RIOSGMIICLKP_T 

RIOTXN1 

C13 

C9 

C120 0.01UF 

F1_RIOSGMIICLKN_T 

RIOSGMIICLKP 

F1_RIOSGMIICLKN 

D9 

RIOSGMIICLKN 

F1_RIORXN0 

RIORXN0 

A9 

F1_RIORXN0 3 

F1_RIORXP0 

RIORXP0 

A10 

F1_RIORXP0 3 

F1_RIOTXP0 

RIOTXP0 

C10 

F1_RIOTXP0 3 

F1_RIOTXN0 

RIOTXN0 

C11 

F1_RIOTXN0 3 

B12 

RESV.19 

B18 

RESV.20 

SGMIIRXN C16 

C19 

MDCLK SGMIIRXP C17 

B19 

MDIO SGMIITXP A15 

SGMIITXN A16 


DUT_3V3 

C C 


R207 

100K 

F1_SGMIIRXN C121 0.01UF 

F1_SGMIIRXN_PHY 37 

C122 

0.1uF 

R208 R209 

U25 

1K 

1K 

8 

GATE GND1 

1 

F_DVDD_18 

F1_SGMIIRXP C123 0.01UF 

F1_SGMIIRXP_PHY 37 

7 

B1 

A1 

2 

R210 

37 MDC_CPU_ENETSLAVE 

6 

F1_SGMII_MDCLK 

B2 

A2 

3 

F1_SGMIITXP C124 0.01UF 

F1_SGMIITXP_PHY 37 

F1_SGMII_MDIO 

37 MDIO_CPU_ENETSLAVE 

5 

B3 

A3 

4 

SN74TVC3306 

B F1_SGMIITXN C125 0.01UF 

F1_SGMIITXN_PHY 37 

B 


A 

Title: 



C6474 CPU-1: SRIO, SGMII 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


6 

6 

0 

A-23

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


F1_CVDD 

42 

F1_CVDDMON 

F_DVDD_18 

D D 

Resistor on top layer. Allows 

probing of internal VSS. 

U17I 

DVDD18MON AG7 

0 

DVDD_18 

E27 

H1 

R212 

VSS 

DVDD_18 

E5 

B10 

VSS 

DVDD_18 

G23 

B11 

VSS 

DVDD_18 

G5 

B14 

VSS 

DVDD_18 

H2 

B15 

VSS 

DVDD_18 

J23 

B16 

VSS 

DVDD_18 

J27 

B2 

VSS 

DVDD_18 

J5 

B23 

VSS 

DVDD_18 

L1 

B3 

VSS 

DVDD_18 

L23 

B4 

VSS 

DVDD_18 

L5 

B5 

VSS 

DVDD_18 

M26 

B6 

VSS 

DVDD_18 

N23 

B7 

VSS 

DVDD_18 

N5 

B9 

VSS 

DVDD_18 

P2 

C C1 

VSS 

DVDD_18 

P26 

C 

C15 

VSS 

DVDD_18 

R23 

C18 

VSS 

DVDD_18 

R5 

C2 

VSS 

DVDD_18 

U1 

C24 

VSS 

DVDD_18 

U23 

C3 

VSS 

DVDD_18 

U5 

C8 

VSS 

DVDD_18 

V26 

D1 

VSS 

DVDD_18 

A1 

D10 

VSS 

DVDD_18 

A19 

D11 

VSS 

DVDD_18 

A23 

D13 

VSS 

DVDD_18 

A27 

D14 

VSS 

DVDD_18 

A5 

D15 

VSS 

DVDD_18 

AA23 

D16 

VSS 

DVDD_18 

AA5 

D17 

VSS 

DVDD_18 

AB26 

D2 

VSS 

DVDD_18 

AC1 

D23 

VSS 

DVDD_18 

AC23 

D3 

VSS 

DVDD_18 

AC5 

D8 

VSS 

DVDD_18 

AC7 

E10 

VSS 

DVDD_18 

AC9 

E12 

VSS 

DVDD_18 

AF5 

E14 

VSS 

DVDD_18 

AG1 

E16 

VSS 

DVDD_18 

AG27 

E18 

VSS 

DVDD_18 

AG8 

B E2 

B 

VSS 

DVDD_18 

E1 

E20 

VSS 

DVDD_18 

E19 

E22 

VSS 

DVDD_18 

E21 

E26 

VSS 

DVDD_18 

E23 

E8 

VSS 

DVDD_18 

W23 

F1 

VSS 

DVDD_18 

W5 

F23 

VSS 

DVDD_18 

Y2 

F5 

VSS 

DVDD_18 

Y24 

G1 

VSS 

G24 

VSS 

DNP 

R211 

TP7 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

CVDDMON AG6 

VPP E6 

VPP E7 


H23 

H5 

J10 

J12 

J14 

J16 

J18 

J26 

K11 

K13 

K15 

K17 

K19 

K23 

K5 

K9 

L10 

L12 

L14 

L16 

L18 

L2 

M11 

U16 

M13 

M15 

M17 

M19 

M23 

M27 

M5 

M9 

N10 

N12 

N14 

N16 

N18 

P1 

P11 

P13 

P15 

P17 

P19 

P23 

P27 

P5 

P9 

R10 

R12 

R14 

R16 

R18 

R24 

T11 

T13 

T15 

T17 

T19 

T23 

T27 

T5 

T9 

U10 

U12 

U14 

U18 

U2 

U24 

V11 

V13 

V15 

V17 

V19 

V23 

V27 

V5 

V9 

W10 

W12 

W14 

W16 

W18 

Y1 

Y23 

Y5 

CVDD J11 

CVDD J17 

CVDD J19 

CVDD J9 

CVDD K10 

CVDD K18 

CVDD L11 

CVDD L13 

CVDD L15 

CVDD L17 

CVDD L19 

CVDD L9 

CVDD M10 

CVDD M12 

CVDD M14 

CVDD M16 

CVDD M18 

CVDD N11 

CVDD N13 

CVDD N15 

CVDD N17 

CVDD N19 

CVDD N9 

CVDD P10 

CVDD P12 

CVDD P14 

CVDD P16 

CVDD P18 

CVDD R11 

CVDD R13 

CVDD R15 

CVDD R17 

CVDD R19 

CVDD R9 

CVDD T10 

CVDD T12 

CVDD T14 

CVDD T16 

CVDD T18 

CVDD U11 

CVDD U13 

CVDD U15 

CVDD U19 

CVDD U9 

CVDD V10 

CVDD V12 

CVDD V14 

CVDD W11 

CVDD W13 

CVDD W9 


A 

Title: 



C6474 CPU-1: Power Pins; CVDD, DVDD_18, VSS 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


F_VDDD_11 

F_VDDD_11 

D E3 

U17H 

D 

1 

F1_AIF_VDDD 

IN OUT 

3 

AG26 

AIF_VDDD_11 

E4 

U17 

2 

C126 C127 

AIF_VDDD_11 

F1_SGR_VDDD 

GND 

V16 

0.1UF 560PF 

AIF_VDDD_11 

3 

OUT IN 1 

V18 

AIF_VDDD_11 

SGR_VDDD_11 

J13 

W15 

C128 C129 


AIF_VDDD_11 

SGR_VDDD_11 

J15 

560PF 0.1UF 

GND 2 

W17 

AIF_VDDD_11 

SGR_VDDD_11 

K12 

W19 

AIF_VDDD_11 

SGR_VDDD_11 

K14 

SGR_VDDD_11 

K16 


AC11 

AIF_VDDT_11 

E5 

AC14 

AIF_VDDT_11 

SGR_VDDT_11 

B13 

AC17 

F1_SGR_VDDT 

AIF_VDDT_11 

SGR_VDDT_11 

B17 

3 

OUT IN 1 

AC20 

AIF_VDDT_11 

SGR_VDDT_11 

B8 

C130 C131 

E6 

AF15 

AIF_VDDT_11 

SGR_VDDT_11 

E13 

560PF 0.1UF 

GND 2 

AF19 

1 

F1_AIF_VDDT 

AIF_VDDT_11 

SGR_VDDT_11 

E17 

IN OUT 

3 

AG11 

AIF_VDDT_11 

SGR_VDDT_11 

E9 


2 

C132 C133 

GND 

AC12 

0.1UF 

AIF_VDDA_11 

SGR_VDDA_11 

D18 

560PF 

AC15 

AIF_VDDA_11 

SGR_VDDA_11 

D12 

E7 

AC18 


AIF_VDDA_11 

SGR_VDDA_11 

E11 

AC21 

F1_SGR_VDDA 

AIF_VDDA_11 

SGR_VDDA_11 

E15 

3 

OUT IN 1 

E8 

AD15 

C134 C135 

F1_AIF_VDDA 

AIF_VDDR_18 

SGR_VDDR_18 

A18 

560PF 0.1UF 

GND 2 

C 1 

IN OUT 

3 

AD19 

AIF_VDDR_18 

SGR_VDDR_18 

C12 

C 

VSS A11 

VSS A14 

VSS A17 

VSS A2 

VSS A26 

VSS A3 

VSS A4 

VSS A6 

VSS A7 

VSS A8 

VSS AA1 

VSS AB1 

VSS AB23 

VSS AB27 

VSS AB5 

VSS AC10 

VSS AC13 

VSS AC16 

VSS AC19 

VSS AC2 

VSS AC22 

VSS AC6 

VSS AC8 

VSS AD1 

VSS AD11 

VSS AD18 

VSS AD2 

VSS AD22 



E9 

F_DVDD_18 

F1_SGR_VDDR 3 

OUT IN 1 

C138 C139 

560PF 0.1UF 

GND 2 

AE1 

VSS 

AE11 

VSS 

AE12 

VSS 

AE15 

VSS 

AE16 

VSS 

AE2 

VSS 

AE20 

VSS 

AE3 

VSS 

AF1 

VSS 

AF11 

VSS 

AF14 

VSS 

AF18 

VSS 

AF2 

VSS 

AF20 

VSS 

AF23 

VSS 

AF26 

VSS 

AF27 

VSS 

AF3 

VSS 

AF8 

VSS 

AG12 

VSS 

AG15 

VSS 

AG16 

VSS 

AG19 

VSS 

AG2 

VSS 

AG22 

VSS 

AG3 

VSS 

AG4 

VSS 

AG5 

VSS 

B1 

VSS 

2 

C136 C137 

GND 

0.1UF 560PF 


F_DVDD_18 

E10 

1 

F1_AIF_VDDR 

IN OUT 

3 

2 

C140 C141 


GND 

0.1UF 560PF 


F_VDDD_11 

F_VDDD_11 

F_DVDD_18 

1 

1 

2 

2 

B 3 

B 

+ C142 

C143 C144 C145 C146 

3 

+ C147 

C148 C149 C150 C151 

10UF 

0.1UF 0.1UF 560PF 560PF 

HDR_1X3 

+ C152 

C153 C154 C155 C156 

10UF 

0.1UF 0.1UF 560PF 560PF 

10UF 

0.1UF 0.1UF 560PF 560PF 


P1 

Header for Fan Power. Place within 

1 inch of DSP. 

F_VDDD_11 

R591 0 

F_DVDD_18_MON 


F_DVDD_18 


A 

F_VDDD_11_MON R592 0 

40 F_VDDD_11_MON 



C6474 CPU-1: Power pins; SERDES PWR, VSS 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


A-25

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


F1_CVDD 

+ C160 + C161 

C163 C164 C165 

1000UF 1000UF 

22UF 22UF 47UF 

D D 

F1_CVDD 

C168 C169 C170 C171 C172 C173 C174 C175 C176 C177 C178 C179 C180 C181 C182 C183 C184 C185 C186 C187 

0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 

C C 

F1_CVDD 


0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 

F_DVDD_18 

B B 

+ C208 C209 C210 C211 C212 C213 C214 C215 C216 C217 C218 C219 C220 C221 C222 C223 C224 C225 C226 C227 C228 

330UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 

F_DVDD_18 

C229 C230 C231 C232 C233 C234 C235 C236 C237 C238 C239 C240 

A 22UF 22UF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 


A 

Title: 



C6474 CPU-1: Decoupling; CVDD and DVDD_18 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


F2_DDRD[0:31] 

F2_DDRD[0:31] 28 



U26 

U27 

F2_DDRA13 F2_DDRA13 

NC/A13 

V8 

V8 

F2_DDRA12 

F2_DDRA12 

NC/A13 

M9 

VDD 

A12 

V2 

V2 

R263 

F2_DDRA11 

F2_DDRA11 

A12 

VDD M9 

H1 

VDD 

A11 

U7 

U7 

1K 

F2_DDRA10 

F2_DDRA10 

A11 

VDD H1 

R9 

D VDD 

A10 

R2 

R2 

C264 

F2_DDRA9 

F2_DDRA9 

A10 

VDD R9 

D 

D1 

VDD 

A9 

U3 

U3 

F2_DDRA8 

F2_DDRA8 

A9 

VDD D1 

V1 

VDD 

A8 

U8 

U8 

0.1UF 

F3 

F2_DDRA7 

F2_DDRA7 

A8 

VDD V1 

VDDQ 

A7 

U2 

U2 

F7 

F2_DDRA6 

F2_DDRA6 

A7 

VDDQ F3 

VDDQ 

A6 

T7 

T7 

K1 

F2_DDRA5 

F2_DDRA5 

A6 

VDDQ F7 

F2_DDR_VREF 

VDDQ 

A5 

T3 

T3 

A5 

VDDQ K1 

K3 

VDDQ 

VDDQ K3 

K7 

VDDQ 

VDDQ K7 

K9 

F2_DDR_VREF 

VDDQ 

D9 

F2_DDRA4 

F2_DDRA4 

VDDQ K9 

VDDQ 

A4 

T8 

T8 

F1 

F2_DDRA3 

F2_DDRA3 

A4 

VDDQ D9 

F2_DDR_VREF 

VDDQ 

A3 

T2 

T2 

F9 

F2_DDRA2 

F2_DDRA2 

A3 

VDDQ F1 

VDDQ 

A2 

R7 

R7 

H9 

F2_DDRA1 

F2_DDRA1 

A2 

VDDQ F9 

C241 

VDDQ 

A1 

R3 

R3 

R268 

F2_DDRA0 

F2_DDRA0 

A1 

VDDQ H9 

0.1UF 

C242 

A0 

R8 

R8 

1K 

C265 

F2_DDRBA2 

F2_DDRBA2 

A0 

0.1UF 

BA2 

P1 

P1 

0.1UF 

M1 

F2_DDRBA1 

F2_DDRBA1 

BA2 

VDDL 

BA1 

P3 

P3 

F2_DDRBA0 

F2_DDRBA0 

BA1 

VDDL 

M1 

BA0 

P2 

P2 

BA0 

F2_DDRA[0:13] 

F2_DDRD[0:31] 

F2_DDRA[0:13] 28 

F2_DDRD[0:31] 28 

M2 

VREF 

VREF 

M2 

NC1 

AA9 

AA9 


NC1 

F2_DDRD31 


NC2 

AA8 

AA8 


NC2 

5 4 

E9 


F2_DDRD15 

F2_DDRD29 


DQ15 

NC3 

AA2 Layout for the 92-ball DDR 

AA2 

NC3 

DQ15 

E9 

8 1 

6 3 

E1 


F2_DDRD13 

F2_DDRD26 


DQ14 

NC4 

AA1 Package but populate the 

AA1 

NC4 

DQ14 

E1 

7 2 

7 2 

G9 


F2_DDRD10 

F2_DDRD24 


DQ13 

NC5 

D2 

D2 

84-ball MT47H64M16HR-3:E. 

NC5 

DQ13 

G9 

6 3 


F2_DDRD8 

C 8 1 

G1 

DQ12 

DQ12 

G1 

5 4 

C 

84 Ball memories reside in 

F2_DDRD30 


NC7 

A9 

A9 

G3 


F2_DDRD14 

F2_DDRD28 


NC8 

A8 

R213 

NC7 

5 4 

DQ11 

A8 

8 1 

the center section of the 92 

G7 


F2_DDRD12 

F2_DDRD27 


DQ10 

NC9 

A2 

DNP_0603 NC8 

DQ11 

G3 

6 3 

A2 

NC9 

DQ10 

G7 

7 2 

7 2 

F2 

Ball Package 


F2_DDRD11 

F2_DDRD25 


DQ9 

NC10 

A1 

A1 

NC10 

DQ9 

F2 

6 3 

8 1 

F8 


F2_DDRD9 

DQ8 

NC11 

H2 

H2 

DQ8 

F8 

5 4 


NC11 




F2_DDRD23 5 4 F2_TDDRD23 F2_TDDRD23 J9 


F2_DDRD7 

F2_DDRD21 


DQ7 

J1 


F2_DDRD5 

F2_DDRD18 


DQ6 

RFU V3 

DQ7 

J9 

8 1 

6 3 

V3 

L9 


F2_DDRD2 

F2_DDRD16 


DQ5 

RFU V7 

RFU 

DQ6 

J1 

7 2 

7 2 

V7 

RFU 

DQ5 

L9 

6 3 

8 1 

L1 


F2_DDRD0 

DQ4 

ODT 

N9 

N9 

ODT 

DQ4 

L1 

5 4 

F2_DDRD22 8 1 F2_TDDRD22 F2_TDDRD19 L3 


F2_DDRD6 

F2_DDRD20 


DQ3 

DQ3 

L3 

8 1 

7 2 

L7 


F2_DDRD4 

F2_DDRD19 


DQ2 

DQ2 

L7 

7 2 

6 3 

K2 


F2_DDRD3 

F2_DDRD17 


DQ1 

CS# 

P8 

P8 

CS# 

DQ1 

K2 

6 3 

5 4 

K8 

F2_TDDRD0 F2_TDDRD1 5 4 F2_DDRD1 

DQ0 

CAS# 

P7 

P7 

CAS# 

DQ0 

K8 


RAS# 

N7 

N7 


RAS# 

WE# 

N3 

N3 



CKE N2 

WE# 

U9 

VSS 

N2 

CKE 

VSS U9 

T1 

VSS 

VSS T1 

H3 

VSS 

D3 



VSS 

CK M8 

VSS H3 

M8 

M3 



CK 

VSS D3 

B + C244 

VSS 

CK# 

N8 

N8 

VSS M3 

+ C243 

CK# 

G8 

C245 C246 C247 

B 

10UF C249 C250 C251 C252 

VSSQ 

VSSQ G8 

10UF 

C248 

J8 

0.1UF 0.1UF 0.1UF 

0.1UF 0.1UF 0.1UF 0.1UF 

VSSQ 

D7 

VSSQ UDQS#/NU D8 

VSSQ J8 

0.1UF 

D8 

J2 

VSSQ 

UDQS E7 

UDQS#/NU VSSQ D7 

E7 

E2 

VSSQ LDQS#/NU H8 

UDQS 

VSSQ J2 

H8 

L8 

VSSQ 

LDQS J7 

LDQS#/NU VSSQ E2 

J7 

LDQS 

VSSQ L8 

L2 



VSSQ 

VSSQ L2 

E8 

VSSQ 

H7 

VSSQ 

UDM E3 

VSSQ E8 

E3 

G2 

VSSQ 

LDM J3 

UDM 

VSSQ H7 

J3 

LDM 

VSSQ G2 

M7 

VSSDL 

VSSDL 

M7 

C253 C254 C255 C256 

C257 C258 C259 C260 

560PF 560PF 560PF 560PF 

560PF 560PF 560PF 560PF 



F2_DDRDQM0 28 

28 F2_DDRDQM2 

F2_DDRDQM1 28 

28 F2_DDRDQM3 

RPACK4-22 

RPACK4-22 


5 4 

8 1 F2_DDRDQS0P 28 


6 3 

7 2 F2_DDRDQS0N 28 


7 2 

6 3 F2_DDRDQS1P 28 


8 1 

5 4 F2_DDRDQS1N 28 


A 

RN17 

RN18 

28 F2_DDRCLKOUTN1 

F2_DDRBA2 28 


F2_DDRBA1 28 

28 F2_DDRCLKOUTP1 

F2_DDRBA0 28 

28 F2_DDRCKEz 


C6474 CPU-2: DDR2 

28 F2_DDRWEz 


28 F2_DDRRASz 

Revision: 


28 F2_DDRCASz 

Size: B 

DWG NO 511222-0001 

A 

28 F2_DDRCSz 

F2_DDRODT 28 


A-27

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 


R218 DNP 


R221 DNP 

R222 DNP 


R225 DNP 

R226 DNP 


R229 DNP 

R230 DNP 


R233 DNP 

R234 DNP 

U30G 

R236 DNP 

R237 DNP 

R235 DNP 


F1_CLKX0_F2_CLKR0 B20 



CLKR0 GP00/BOOTM0 

T3 


7,16 F1_FSX0_F2_FSR0 

B21 


F1_DX0_F2_DR0 

FSR0 

GP01/BOOTM1 

U4 


7,16 F1_DX0_F2_DR0 

A20 



F1_CLKR0_F2_CLKX0 

DR0 

GP02/BOOTM2 

V1 


C20 



7,16 F1_FSR0_F2_FSX0 


CLKX0 

GP03/BOOTM3 

U3 

A21 

F1_DR0_F2_DX0 

FSX0 


C 7,16 F1_DR0_F2_DX0 

D19 

DX0 

GP04/LENDIAN T4 

F2_GP04_LENDIAN 12 

C 


F2_GP05_L2CONFIG 12 

F2_CLKS0 

F2_CLKS0 

GP05/L2_CONFIG V2 

D20 

F2_GP06 

CLKS0 

GP06 

V3 

F2_GP06 12 

F2_GP07 

GP07 

Y3 

F2_GP07 12 

DDRSLRATE AE23 

F2_CLKR1 

F2_FSR1 

F2_DR1 

F2_CLKX1 

F2_FSX1 

F2_DX1 

F2_CLKS1 

F2_CLKR1 

F2_FSR1 

F2_DR1 

F2_CLKX1 

F2_FSX1 

F2_DX1 

F2_CLKS1 

A24 

C21 

D21 

C22 

A22 

B22 

A25 

CLKR1 

FSR1 

DR1 

CLKX1 

FSX1 

DX1 

CLKS1 

GP08/DEVNUM0 

GP09/DEVNUM1 

GP10/DEVNUM2 

GP11/DEVNUM3 

GP12 

GP13 

GP14 

GP15 

Y4 

AA2 

AA3 

AB4 

AB3 

AB2 

AA4 

AC3 





F2_GP12 

F2_GP13 

F2_GP14 

F2_GP15 





F2_GP12 7,12 

F2_GP13 7,12 

F2_GP14 7,12 

F2_GP15 7,12 

CORECLKSEL 

AF7 

F2_CORECLKSEL 

F2_CORECLKSEL 12 

F2_DDRSLRATE 

F2_DDRSLRATE 12 


F_DVDD_18 

R238 DNP 

R239 DNP 

B B 

R240 DNP 

R241 DNP 

R242 DNP 

R243 DNP 

R244 DNP 

R245 DNP 

R246 DNP 

R247 DNP 

R248 DNP 

R249 DNP 

R250 DNP 

R251 DNP 

R252 DNP 

R253 DNP 


A 

Title: 



C6474 CPU-2: McBSP, GPIO, CONFIG 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


7 

7 

7 

7 

7 

7 

7 

7 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


F2_DDRA[0:13] 

F2_DDRA[0:13] 26 

DDRA0_F2 R256 22 F2_DDRA0 

DDRA8_F2 R257 22 F2_DDRA8 

F2_DDRD[0:31] 

26 F2_DDRD[0:31] 

DDRA13_F2 5 4 

F2_DDRA13 

DDRA4_F2 

F2_DDRA4 

U30B 

6 3 

DDRA6_F2 7 2 

F2_DDRA6 

F2_DDRD0 W27 

DDRA0_F2 

DDRA11_F2 

F2_DDRA11 

F2_DDRD1 

DDRD00 

DDRA00 

K25 

8 1 

W25 

DDRA1_F2 


D F2_DDRD2 

DDRD01 

DDRA01 

N25 

DDRA2_F2 

D 

Y27 

F2_DDRD3 

DDRD02 

DDRA02 

M25 

W26 

DDRA3_F2 

F2_DDRD4 

DDRD03 

DDRA03 

R26 

AA27 

DDRA4_F2 

F2_DDRD5 

DDRD04 

DDRA04 

L25 

AA26 

DDRA5_F2 

DDRA2_F2 

F2_DDRA2 

F2_DDRD6 

DDRD05 

DDRA05 

N27 

9 8 

AA25 

DDRA6_F2 

DDRA1_F2 

F2_DDRA1 

F2_DDRD7 

DDRD06 

DDRA06 

L26 

10 7 

AA24 

DDRA7_F2 

DDRA5_F2 

F2_DDRA5 

DDRD07 

DDRA07 

U26 

11 6 

DDRA10_F2 12 5 

F2_DDRA10 

DDRA3_F2 13 4 

F2_DDRA3 

DDRA9_F2 14 3 

F2_DDRA9 

F2_DDRD8 AC27 

DDRA8_F2 

DDRA7_F2 

F2_DDRA7 

F2_DDRD9 

DDRD08 

DDRA08 

K26 

15 2 

AC26 

DDRA9_F2 

DDRA12_F2 

F2_DDRA12 

F2_DDRD10 

DDRD09 

DDRA09 

R27 

16 1 

AC25 

DDRA10_F2 

F2_DDRD11 

DDRD10 

DDRA10 

P25 

AD27 

DDRA11_F2 

F2_DDRD12 

DDRA11 

L27 


DDRD11 

AC24 

DDRA12_F2 


F2_DDRD13 

DDRD12 

DDRA12 

U27 

AE26 

DDRA13_F2 

DDRBA2_F2 16 1 F2_DDRBA2 

F2_DDRBA2 26 

F2_DDRD14 

DDRD13 

DDRA13 

K27 

AE27 

DDRBA0_F2 


F2_DDRBA0 26 

F2_DDRD15 

DDRD14 

DDRBA0 

T25 

AE25 

DDRBA1_F2 

DDRCKE_F2 

DDRD15 

DDRBA1 

R25 

14 3 

F2_DDRCKEz 26 

DDRBA2_F2 


DDRBA2 

U25 

F2_DDRBA1 26 

DDRWE_F2 12 5 

F2_DDRWEz 26 

DDRCAS_F2 11 6 

F2_DDRCASz 26 

F2_DDRD16 B25 

DDRCE_F2 

DDRRAS_F2 10 7 

F2_DDRRASz 26 

F2_DDRD17 

DDRD16 

DDRCEz 

L24 

D25 

DDRCE_F2 9 8 

F2_DDRCSz 26 

F2_DDRD18 

DDRD17 

B26 

F2_DDRD19 

DDRD18 

DDRODT 

K24 

C D24 

C 

F2_DDRD20 

DDRD19 

B27 

R254 22 

F2_DDRODT 26 

F2_DDRD21 

DDRD20 

D26 

F2_DDRD22 

DDRD21 

D27 

F2_DDRD23 

DDRD22 

VREFSSTL 

T26 

C27 

DDRD23 

F2_DDRD24 F24 

DDRCAS_F2 

F2_DDRD25 

DDRD24 

DDRCASz 

N26 

F25 

DDRRAS_F2 

F2_DDRD26 

DDRD25 

DDRRASz 

M24 

F26 

DDRWE_F2 

F2_DDRD27 

DDRD26 

DDRWEz 

P24 

F27 

DDRCKE_F2 

F_DVDD_18 

F2_DDRD28 

DDRD27 

DDRCKE T24 

G27 

F2_DDRD29 

DDRD28 

H25 

F2_DDRD30 

DDRD29 

H26 

F2_DDRD31 

DDRD30 

H27 

DDRD31 

DDRDQS0P Y26 


DDRDQS0N Y25 


DDRDQS1P AD26 



22 R214 

DDRDQS1N AD25 

26 F2_DDRDQM0 

W24 

22 R215 

DDRDQM0 

26 F2_DDRDQM1 

AE24 

R255 

22 R216 

DDRDQM1 

C261 

26 F2_DDRDQM2 

B24 

1K 

22 R217 

DDRDQM2 

0.1UF 

26 F2_DDRDQM3 

H24 

DDRDQM3 DDRDQS2P C26 


DDRDQS2N C25 


B F2_VREFSSTL 


B 

DDRDQS3P G25 


10 R264 


DDRDQS3N G26 

AB24 

DDRRCVENOUT0 

AB25 

C262 

DDRRCVENIN0 

E25 

0.1UF 

10 R265 


DDRRCVENOUT1 

E24 


DDRRCVENIN1 DDRCLKOUTP0 

V25 

R266 22 


F2_TDDRCLKOUTN0 R267 22 

DDRCLKOUTN0 

V24 


DDRCLKOUTP1 

DDRCLKOUTN1 

J25 

J24 


F2_TDDRCLKOUTN1 

R269 22 

R270 22 



R261 

1K 

C263 

0.1UF 







A 

Title: 



C6474 CPU-2: DDR2 interface 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


A-29

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


F_DVDD_18 

R271 AND R273 FOR POPULATE FOR DEBUG PURPOSES ONLY ( 100 ohms ). 


R21 

D 10K 

D 

F2_FSYNC_CLKP 

F2_FSYNC_CLKN 

R22 

10K 



F2_FSYNC_CLK 

F2_FSYNCCLKP 

F2_FSYNCCLKN 


R271 NO-POP 

R273 NO-POP 


AD7 

AD8 

AD9 

AD10 

AF6 

FSYNCCLKP 

FSYNCCLKN 

FRAMEBURSTP 

FRAMEBURSTN 

ALTFSYNCCLK 

U30F 

SMFRAMECLK AD4 

33 

R272 

F2_AIFRXN0 

CF55 CFOOT1 

1 2 

.1uF 

F2_SMFRAMECLK 7 

F2_AIFRXN0_SMA 4 

F2_SYNC_BURST 

AE6 

ALTFSYNCPULSE 

CF56 CFOOT1 

F2_AIFRXP0 

F2_TRTCLK 

AC4 

TRTCLK 

1 2 

.1uF 

F2_TRT 

AD3 

TRT 

F2_AIFRXP0_SMA 4 

AE19 

RESV.1 

AD14 

RESV.2 

F2_AIFRXN3 

F2_AIFRXN3 AE17 

F2_AIFRXN0 

F2_AIFRXP3 

AIFRXN3 

AIFRXN0 

AF22 

F2_AIFRXP0 

C F2_AIFRXP3 

AE18 

C 

F2_AIFTXP3 

F2_AIFTXP3 

AIFRXP3 

AIFRXP0 

AF21 

AD16 

F2_AIFTXP0 

F2_AIFTXP0 18 

F2_AIFTXN3 

F2_AIFTXN3 

AIFTXP3 

AIFTXP0 

AE22 

AD17 

F2_AIFTXN0 

AIFTXN3 

AIFTXN0 

AE21 

F2_AIFTXN0 18 

F2_AIFRXN4 

F2_AIFRXN4 

AE14 

F2_AIFRXN1 

F2_AIFRXP4 

AIFRXN4 

AIFRXN1 

AG20 

F2_AIFRXN1 4 

F2_AIFRXP4 

AE13 

F2_AIFRXP1 

F2_AIFRXP1 4 

F2_AIFTXP4 

F2_AIFTXP4 

AIFRXP4 

AIFRXP1 

AG21 

AG14 

F2_AIFTXP1 

F2_AIFTXP1 4 

F2_AIFTXN4 

F2_AIFTXN4 

AIFTXP4 

AIFTXP1 

AD20 

AG13 

F2_AIFTXN1 

AIFTXN4 

AIFTXN1 

AD21 

F2_AIFTXN1 4 

F2_AIFRXN5 

F2_AIFRXN5 

AF12 

F2_AIFRXN2 

F2_AIFRXP5 

AIFRXN5 

AIFRXN2 

AG18 

F2_AIFRXN2 4 

F2_AIFRXP5 

AF13 

F2_AIFRXP2 

F2_AIFRXP2 4 

F2_AIFTXP5 

F2_AIFTXP5 

AIFRXP5 

AIFRXP2 

AG17 

AD12 

F2_AIFTXP2 

F2_AIFTXP2 4 

F2_AIFTXN5 

AIFTXP5 

AIFTXP2 

AF17 

F2_AIFTXN2 

F2_AIFTXN5 

AD13 

AIFTXN5 

AIFTXN2 

AF16 

F2_AIFTXN2 4 


B B 


A 

Title: 



C6474 CPU-2: AIF and FSYNC Interfaces 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


5 

5 

6 

6 

7 

7 

7 

7 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 

4 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


U30A 


G4 

F3 

RESV.21 

RESV.22 

EMU21 

EMU20 

K1 

K3 

R274 

100 

R275 

4.75K 

NOTE: ALL Traces MUST not exceed a maxium of length of 2 in. 

NOTE: TCLKRTN line must be 1 in. 



D J14 

D 

F2_EMU19 K4 

F2_EMU19 

EMU19 

B1 

DNP R276 

ID0 

NC D1 

A1 

F2_EMU18 

F2_TMS_BUF 

F2_TMS 43 R277 F2_TMS_T 

TMS W1 

GND* 

ID2 

C1 

M3 

EMU18 

B2 

TMS 

GND D2 

A2 

F2_EMU18_T 43 R278 F2_EMU18 

F2_TRST_BUF 

F2_EMU17 

F2_EMU17 43 R279 F2_EMU17_T 

GND 

EMU18 

C2 

W2 

TRSTz 

EMU17 

L4 

B3 

EMU17 

GND D3 

A3 

F2_TRST_T 43 R280 F2_TRST 

F2_EMU16 

F2_TDI_BUF 

F2_TDI 43 R281 F2_TDI_T 

GND 

TRST 

C3 

P3 

EMU16 

TDI 

V4 

B4 

TDI 

GND D4 

A4 

F2_EMU16_T 43 R282 F2_EMU16 

F2_EMU15 

F2_EMU14 F2_EMU14 

F2_EMU14_T 

GND 

EMU16 

C4 

T1 

EMU14 

K2 

43 R283 

EMU15 

B5 

EMU14 

GND D5 

A5 

F2_EMU15_T 43 R284 F2_EMU15 

F2_EMU13 

F2_EMU12 

F2_EMU12 43 R285 F2_EMU12_T 

GND 

EMU15 

C5 

P4 

EMU13 

EMU12 

L3 

B6 

EMU12 

GND D6 

A6 

F2_EMU13_T 43 R286 F2_EMU13 

F2_EMU11 

F2_TDO 

F2_TDO_BUF 43 R287 F2_TDO_T 

TDO W3 

GND 

EMU13 

C6 

T2 

EMU11 

B7 

TDO 

GND D7 

A7 

F2_EMU11_T 43 R288 F2_EMU11 

GND 

EMU11 

C7 

B8 

F2_TRST DNP R289 F2_TYPE 

TVD 

Type 1 

D8 

A8 

F2_TCLKRET_T 22 R290 F2_TCLKRET 

F2_EMU10 R1 

F2_EMU9 

F2_EMU9 43 R291 F2_EMU9_T 

Type 0 TCLKRTN C8 

EMU10 

EMU09 

N2 

B9 

EMU9 

GND D9 

A9 

F2_EMU10_T 43 R292 F2_EMU10 

F2_EMU8 M4 

F2_EMU7 

F2_EMU7 43 R293 F2_EMU7_T 

GND 

EMU10 

C9 

EMU08 

EMU07 

R3 

B10 

EMU7 

GND D10 

A10 

F2_EMU8_T 43 R294 F2_EMU8 

F2_EMU6 N4 

F2_EMU5 

F2_EMU5 43 R295 F2_EMU5_T 

GND 

EMU8 

C10 

EMU06 

EMU05 

M1 

B11 

EMU5 

GND D11 

A11 

F2_EMU6_T 43 R296 F2_EMU6 

F2_EMU4 

F2_TCK_BUF 

F2_TCK 43 R297 F2_TCK_T 

C M2 

EMU04 

TCK W4 

GND 

EMU6 

C11 

B12 

TCLK 

GND D12 

C 

A12 

F2_EMU4_T 43 R298 F2_EMU4 

F_DVDD_18 

F2_EMU3 

N1 

F2_EMU2 

F2_EMU2 43 R299 F2_EMU2_T 

GND 

EMU4 

C12 

EMU03 

EMU02 

N3 

B13 

EMU2 

GND D13 

A13 

F2_EMU3_T 43 R300 F2_EMU3 

F2_EMU1 R2 

F2_EMU0 

F2_EMU0 43 R301 F2_EMU0_T 

GND 

EMU3 

C13 

EMU01 

EMU00 

R4 

B14 

EMU0 

GND D14 

A14 

F2_EMU1_T 43 R302 F2_EMU1 

GND 

EMU1 

C14 

B15 

C266 

ID1 

GND D15 

A15 

6.8pF 

OUT 

ID3 

C15 


Emulation Header 

R303 

DNP_0603 

R304 

DNP_0603 

R305 

49.9 1% 

WHAT ABOUT EMULATOR RESET OUTPUT 



C600 

0.1UF 

C268 

0.1uF 

F2_EMU1 


2 

4 

U32 

F2_TDI 

2 

F2_TDI_BUF 

B ALT_F2_TDI 

1A0 1Y0 

18 

R309 33 

U53 

F2_TCK 

F2_TCLKRET 

12 ALT_F2_TDI 

17 

B 

2A3 2Y3 

3 

2 

4 


F2_TCK 

4 

R308 33 F2_TCK_BUF 

ALT_F2_TCK 

1A1 1Y1 

16 

U33 

12 ALT_F2_TCK 

15 

2A2 2Y2 

5 

SN74AUC1G125 

F2_TMS 

6 

R307 33 F2_TMS_BUF 



ALT_F2_TMS 

1A2 1Y2 

14 

12 ALT_F2_TMS 

13 

2A1 2Y1 

7 

F2_TRST 

8 

F2_TRST_BUF 

ALT_F2_TRST 

1A3 1Y3 

12 

R306 33 

C602 


11 

2A0 2Y0 

9 

0.1UF 

4 

F2_EMU0 

U54 


1 

3 

5 

3 

1 

1 

3 

5 

5 



1OE VCC 20 


2 

R485 

F1_HURRICANE_DET 19 

NO-POP 

R484 

2OE GND 10 


NO-POP 

C269 

74AUC244PW 

0.1UF 


C601 

0.1uF 

F1_HURRICANE_DET 

U34 

C270 

A F2_HURRICANE_DETz 


A 

VCC 5 

0.1UF 

2 

4 


F2_TDO_BUF 

A Y0 

6 

U55 

F2_TDO 3 

E Y1 

4 

33 R310 

SN74AHC1G14 

ALT_F2_TDO 12 



C6474 CPU-2: Emulation Interface 

3 

5 

GND 2 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

SN74AUC1G19 


A-31

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


R311 NO-POP 

U30D 

F2_NMI0 

12 F2_NMI0 

J4 

F2_RESETSTAT 12 

F2_NMI1 

NMI0 

RESETSTATz 

AF4 

12 F2_NMI1 

J2 

F2_NMI2 

NMI1 

12 F2_NMI2 

J1 

NMI2 

F1_PORz 

12 F2_PORz 

AE5 

F1_XWRSTz 

PORz 

D 12 F2_XWRSTz 

AD5 

XWRSTz 

TIMI0 

E3 

F2_TIMI0 7 

D 

TIMI1 

C4 

F2_TIMI1 7 

TIMO0 

F2 

22 R312 

F2_TIMO0 7 

TIMO1 

F4 

22 R313 

F2_TIMO1 7 

F2_PTV18 N24 

PTV18 

RESV.27(NC) 

D5 NO-POP R314 

RESV.28(NC) 

C5 NO-POP R315 

AG10 

R316 

RESV.3 

AG24 

C271 

45.3 1% 

RESV.4 

RESV.7(GND) 

D22 

NO-POP 

RESV.8(GND) 

C23 

1 

2 

3 

4 

RN21 

RPACK4-10K 

D7 

C7 

RESV.5(GND) 

RESV.6(GND) 

VCNTL0 

VCNTL1 

VCNTL2 

VCNTL3 

G3 

G2 

H4 

H3 

F2_VCNTL0 43 

F2_VCNTL1 43 

F2_VCNTL2 43 

F2_VCNTL3 43 

5 

6 

7 

8 

HITEMPz 

J3 

F2_HITEMPz_IN 12 

SCL 

E4 

SDA D4 



C DUT_3V3 

C 

R317 R318 


U35 

4.75K 4.75K 


1 

VDD 

ALERTz 

6 

F2_CPLD_ALERT1z 12 

2 

D+ 

3 

F2_CPLD_CRIT1z 12 

R465 

R467 

D- T_CRIT_Az 

4 

R466 

NO-POP NO-POP NO-POP 

R319 R320 

F2_3V3_SCL 8 

C272 4.75K 4.75K 

F2_3V3_SDA 

CLK 

7 

0.1UF 

DATA GND 5 

U36 

NO-POP 

0 R321 

1 

0 R322 

A0 VCC 8 

2 

0 R323 

A1 WP 7 

3 

A2 SCL 

6 

4 

GND SDA 5 

AT24C1024W-10SU-2.7 

C6474 CPU-2: I2C EEPROM 

B B 

JP5 

4 3 

2 1 

DUT_3V3 

HDR_2X2 

DUT_3V3 DUT_3V3 

R324 

229K 

F_DVDD_18 

2 

U37 

VREF1 VREF2 

7 

EN_9306 

R325 

4.75K 

R326 

4.75K 

F2_SCL 3 

F2_3V3_SCL 

F2_SDA 

SCL1 SCL2 

6 

4 

F2_3V3_SDA 

SDA1 SDA2 

5 

EN_9306 

8 

EN GND 1 

PCA9306 

C273 

0.1UF 


A 

Title: 



C6474 CPU-2: I2C,Timer,VCNTL,Reset/NMI,Misc Test 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

R327 AND R328 AND R330 POPULATED FOR DEBUG PURPOSES ONLY ( 100 OHM). 


R327 NO-POP 

F2_SYSCLK_P 

C274 

0.01UF 

Place on the trace with minimum stubs as close 

as possible to the C6474 pins on the top layer 

C275 

F2_SYSCLK_N 

0.01UF 

R328 NO-POP 

U30C 

TP5 

C276 

F2_SYSCLKP_T 


AE9 

0.01UF 

F2_SYSCLKN_T 

SYSCLKP 

AE10 

33 R329 

F2_SYSCLKOUT 

F2_ALTCORECLKP_T 

SYSCLKN SYSCLKOUT 

AD6 

AF9 

C277 

F2_ALTCORECLKN_T 

ALTCORECLKP 


AF10 

0.01UF 

ALTCORECLKN RESV.11 

AE4 

F2_DDRCLKP_T 

RESV.12 

AG25 

C278 

C F2_DDRCLK_P 

AD24 

C 

0.01UF 

F2_DDRCLKN_T 

DDRREFCLKP 

AD23 

DDRREFCLKN 

C279 R330 

F2_DDRCLK_N 

0.01UF 

NO-POP 



D6 

C6 

RESV.9 

RESV.10 

E11 

F_DVDD_18 

AE7 

F2_AVDD1 

RESV.13 

AVDD1_18 

AG9 

3 

OUT IN 1 

AE8 

RESV.14 

C281 

GND 2 

AF24 

RESV.15 

AVDD2_18 

AG23 

C280 

C282 

AF25 

0.01UF 0.1UF NFM18CC223R1C3 

0.1UF 

RESV.16 


E12 

B F2_AVDD2 

3 

B 

OUT IN 1 

C283 C284 

GND 2 

C285 

0.01UF 0.1UF NFM18CC223R1C3 

0.1UF 


A 

Title: 



C6474 CPU-2: PLLs 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


5 

5 

5 

5 

5 

5 

A-33

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 




D D 

U30E 

F2_RIORXN1 

RIORXN1 

A13 

F2_RIORXN1 3 

C286 0.01UF 

F2_RIORXP1 

F2_RIOSGMIICLKP 

RIORXP1 

A12 

F2_RIORXP1 3 

R331 NO-POP 

F2_RIOTXP1 

RIOTXP1 

C14 

F2_RIOTXP1 3 

F2_RIOTXN1 

F2_RIOTXN1 3 

F2_RIOSGMIICLKP_T 

RIOTXN1 

C13 

C9 

C287 0.01UF 

F2_RIOSGMIICLKN_T 

RIOSGMIICLKP 

F2_RIOSGMIICLKN 

D9 

RIOSGMIICLKN 

F2_RIORXN0 

RIORXN0 

A9 

F2_RIORXN0 3 

F2_RIORXP0 

RIORXP0 

A10 

F2_RIORXP0 3 

F2_RIOTXP0 

F_DVDD_18 

RIOTXP0 

C10 

F2_RIOTXP0 3 

F2_RIOTXN0 

RIOTXN0 

C11 

F2_RIOTXN0 3 

B12 

RESV.19 

B18 

RESV.20 

R128 R129 

SGMIIRXN C16 

C19 

10k 10k 

MDCLK SGMIIRXP C17 

B19 

MDIO SGMIITXP A15 

SGMIITXN A16 

C C 


F2_SGMIIRXN 

C288 0.01UF 

F2_SGMIIRXN_PHY 37 

F2_SGMIIRXP 

C289 0.01UF 

F2_SGMIIRXP_PHY 37 

B B 

F2_SGMIITXP C290 0.01UF 

F2_SGMIITXP_PHY 37 

F2_SGMIITXN 

C291 0.01UF 

F2_SGMIITXN_PHY 37 


A 

Title: 



C6474 CPU-2: SRIO, SGMII 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


6 

6 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


F2_CVDD 

43 

F2_CVDDMON 

D D 

Resistor on top layer. Allows 

probing of internal VSS. 

U30I 

DVDD18MON AG7 

DVDD_18 

E27 

0 

H1 

VSS 

DVDD_18 

E5 

R333 

B10 

VSS 

DVDD_18 

G23 

B11 

VSS 

DVDD_18 

G5 

B14 

VSS 

DVDD_18 

H2 

B15 

VSS 

DVDD_18 

J23 

B16 

VSS 

DVDD_18 

J27 

B2 

VSS 

DVDD_18 

J5 

B23 

VSS 

DVDD_18 

L1 

B3 

VSS 

DVDD_18 

L23 

B4 

VSS 

DVDD_18 

L5 

B5 

VSS 

DVDD_18 

M26 

B6 

VSS 

DVDD_18 

N23 

B7 

VSS 

DVDD_18 

N5 

B9 

VSS 

DVDD_18 

P2 

C C1 

VSS 

DVDD_18 

P26 

C 

C15 

VSS 

DVDD_18 

R23 

C18 

VSS 

DVDD_18 

R5 

C2 

VSS 

DVDD_18 

U1 

C24 

VSS 

DVDD_18 

U23 

C3 

VSS 

DVDD_18 

U5 

C8 

VSS 

DVDD_18 

V26 

D1 

VSS 

DVDD_18 

A1 

D10 

VSS 

DVDD_18 

A19 

D11 

VSS 

DVDD_18 

A23 

D13 

VSS 

DVDD_18 

A27 

D14 

VSS 

DVDD_18 

A5 

D15 

VSS 

DVDD_18 

AA23 

D16 

VSS 

DVDD_18 

AA5 

D17 

VSS 

DVDD_18 

AB26 

D2 

VSS 

DVDD_18 

AC1 

D23 

VSS 

DVDD_18 

AC23 

D3 

VSS 

DVDD_18 

AC5 

D8 

VSS 

DVDD_18 

AC7 

E10 

VSS 

DVDD_18 

AC9 

E12 

VSS 

DVDD_18 

AF5 

E14 

VSS 

DVDD_18 

AG1 

E16 

VSS 

DVDD_18 

AG27 

E18 

VSS 

DVDD_18 

AG8 

B E2 

B 

VSS 

DVDD_18 

E1 

E20 

VSS 

DVDD_18 

E19 

E22 

VSS 

DVDD_18 

E21 

E26 

VSS 

DVDD_18 

E23 

E8 

VSS 

DVDD_18 

W23 

F1 

VSS 

DVDD_18 

W5 

F23 

VSS 

DVDD_18 

Y2 

F5 

VSS 

DVDD_18 

Y24 

G1 

VSS 

G24 

VSS 

F_DVDD_18 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

CVDDMON AG6 

VPP E6 

VPP E7 


H23 

H5 

J10 

J12 

J14 

J16 

J18 

J26 

K11 

K13 

K15 

K17 

K19 

K23 

K5 

K9 

L10 

L12 

L14 

L16 

L18 

L2 

M11 

U16 

M13 

M15 

M17 

M19 

M23 

M27 

M5 

M9 

N10 

N12 

N14 

N16 

N18 

P1 

P11 

P13 

P15 

P17 

P19 

P23 

P27 

P5 

P9 

R10 

R12 

R14 

R16 

R18 

R24 

T11 

T13 

T15 

T17 

T19 

T23 

T27 

T5 

T9 

U10 

U12 

U14 

U18 

U2 

U24 

V11 

V13 

V15 

V17 

V19 

V23 

V27 

V5 

V9 

W10 

W12 

W14 

W16 

W18 

Y1 

Y23 

Y5 

CVDD J11 

CVDD J17 

CVDD J19 

CVDD J9 

CVDD K10 

CVDD K18 

CVDD L11 

CVDD L13 

CVDD L15 

CVDD L17 

CVDD L19 

CVDD L9 

CVDD M10 

CVDD M12 

CVDD M14 

CVDD M16 

CVDD M18 

CVDD N11 

CVDD N13 

CVDD N15 

CVDD N17 

CVDD N19 

CVDD N9 

CVDD P10 

CVDD P12 

CVDD P14 

CVDD P16 

CVDD P18 

CVDD R11 

CVDD R13 

CVDD R15 

CVDD R17 

CVDD R19 

CVDD R9 

CVDD T10 

CVDD T12 

CVDD T14 

CVDD T16 

CVDD T18 

CVDD U11 

CVDD U13 

CVDD U15 

CVDD U19 

CVDD U9 

CVDD V10 

CVDD V12 

CVDD V14 

CVDD W11 

CVDD W13 

CVDD W9 

DNP 

R332 

TP8 


A 

Title: 



C6474 CPU-2: Power Pins; CVDD, DVDD_18, VSS 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


A-35

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


F_VDDD_11 

E13 

U30H 

1 

F2_AIF_VDDD 

IN OUT 

3 

AG26 

AIF_VDDD_11 

E14 

U17 

2 

C292 C293 

AIF_VDDD_11 

F2_SGR_VDDD 

GND 

V16 

0.1UF 560PF 

AIF_VDDD_11 

3 

OUT IN 1 

V18 

D AIF_VDDD_11 

SGR_VDDD_11 

J13 

C294 

D 

W15 


SGR_VDDD_11 

J15 

C295 

AIF_VDDD_11 

W17 

560PF 

AIF_VDDD_11 

SGR_VDDD_11 

K12 

0.1UF 

GND 2 

W19 

AIF_VDDD_11 

SGR_VDDD_11 

K14 

SGR_VDDD_11 

K16 


AC11 

AIF_VDDT_11 

E15 

AC14 

AIF_VDDT_11 

SGR_VDDT_11 

B13 

AC17 

F2_SGR_VDDT 

AIF_VDDT_11 

SGR_VDDT_11 

B17 

3 

OUT IN 1 

AC20 

AIF_VDDT_11 

SGR_VDDT_11 

B8 

E16 

AF15 

SGR_VDDT_11 

E13 

C296 C297 

AIF_VDDT_11 

GND 2 

AF19 

1 

F2_AIF_VDDT 

AIF_VDDT_11 

SGR_VDDT_11 

E17 

560PF 0.1UF 

IN OUT 

3 

AG11 

AIF_VDDT_11 

SGR_VDDT_11 

E9 


2 

C298 C299 

GND 

AC12 

AIF_VDDA_11 

SGR_VDDA_11 

D18 

0.1UF 560PF 

AC15 

AIF_VDDA_11 

SGR_VDDA_11 

D12 

E17 

AC18 


AIF_VDDA_11 

SGR_VDDA_11 

E11 

AC21 

F2_SGR_VDDA 

AIF_VDDA_11 

SGR_VDDA_11 

E15 

3 

OUT IN 1 

E18 

AD15 

C300 C301 

F2_AIF_VDDA 

AIF_VDDR_18 

SGR_VDDR_18 

A18 

AD19 

560PF 0.1UF 

GND 2 

1 

IN OUT 

3 

AIF_VDDR_18 

SGR_VDDR_18 

C12 

F_VDDD_11 

VSS A11 

VSS A14 

VSS A17 

VSS A2 

VSS A26 

VSS A3 

VSS A4 

VSS A6 

VSS A7 

VSS A8 

VSS AA1 

VSS AB1 

VSS AB23 

VSS AB27 

VSS AB5 

VSS AC10 

VSS AC13 

VSS AC16 

VSS AC19 

VSS AC2 

VSS AC22 

VSS AC6 

VSS AC8 

VSS AD1 

VSS AD11 

VSS AD18 

VSS AD2 

VSS AD22 

2 

C302 C303 


GND 

0.1UF 560PF 


E19 

F_DVDD_18 


F2_SGR_VDDR 

C 3 

OUT IN 1 

C 

F_DVDD_18 

E20 

C304 C305 

F2_AIF_VDDR 

560PF 

GND 2 

1 

IN OUT 

3 

0.1UF 

AE1 

AE11 

AE12 

AE15 

AE16 

AE2 

AE20 

AE3 

AF1 

AF11 

AF14 

AF18 

AF2 

AF20 

AF23 

AF26 

AF27 

AF3 

AF8 

AG12 

AG15 

AG16 

AG19 

AG2 

AG22 

AG3 

AG4 

AG5 

B1 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

2 

C306 C307 


GND 

0.1UF 560PF 



F_VDDD_11 

F_VDDD_11 

F_DVDD_18 

1 

2 

3 

P2 

1 

2 

3 

Header for Fan Power. Place within 

1 inch of DSP. 

HDR_1X3 

+ C308 

C309 C310 C311 C312 

+ C313 

C314 C315 C316 C317 

B + C318 

C319 C320 C321 C322 

10UF 

0.1UF 0.1UF 560PF 560PF 

10UF 

0.1UF 0.1UF 560PF 560PF 

B 

10UF 

0.1UF 0.1UF 560PF 560PF 


A 

Title: 



C6474 CPU-2:: Power pins; SERDES PWR, VSS 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 



5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


F2_CVDD 

+ C323 + C324 

C328 C329 C330 

1000UF 1000UF 22UF 22UF 47UF 

D D 

F2_CVDD 


0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 

C C 

F2_CVDD 


0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 

F_DVDD_18 

B B 

+ C373 C374 C375 C376 C377 C378 C379 C380 C381 C382 C383 C384 C385 C386 C387 C388 C389 C390 C391 C392 C393 

330UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 

F_DVDD_18 

C394 C395 C396 C397 C398 C399 C400 C401 C402 C403 C404 C405 

A 22UF 22UF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 560PF 


A 

Title: 



C6474 CPU-2: Decoupling; CVDD and DVDD_18 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


A-37

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


U38A 

R354 1M 

E6122_2V5 

XTAL_IN 7 

C406 18 pF 

Y2 

XTAL_OUT 

8 

25MHz C407 18 pF 

D D 

P3_ENABLE 87 

R334 10K 

E6122_VDDAH_1V8 

P3_COL 

86 

P3_CRS 85 

P3_RXCLK 83 

P3_RXD0 

82 

P3_RXD1 

81 

36 

P4_SDET 

P3_RXD2 

80 

35 

P4_LED/P4_MODE 

P3_RXD3 

78 

P3_RXD4 

76 

P3_RXD5 

75 

34 

P5_SDET 

P3_RXD6 

74 

33 

P5_LED/P5_MODE 

P3_RXD7 

73 

P3_RXERR 72 

P3_RXDV 70 

22 F1_SGMIITXP_PHY 

37 

P6_RXN 

22 F1_SGMIITXN_PHY 

38 

P6_RXP 

P3_GTXCLK 68 

39 

P6_VDDAH 

P3_TXCLK 67 

22 F1_SGMIIRXN_PHY 

40 

P6_TXN 

P3_TXD0/ADDR0 

66 

C 22 F1_SGMIIRXP_PHY 

41 

P6_TXP 

P3_TXD1/ADDR1 

65 

C 

P3_TXD2/ADDR2 

64 

P3_TXD3/ADDR3 

63 

33 F2_SGMIITXP_PHY 

47 

P5_RXN 

P3_TXD4/ADDR4 

61 

33 F2_SGMIITXN_PHY 

46 

P5_RXP 

P3_TXD5/P3_MODE0 

60 


58 

45 

P5_VDDAH 


57 

33 F2_SGMIIRXN_PHY 

44 

P5_TXN 

P3_TXEN/P3_HALFDPX 56 

33 F2_SGMIIRXP_PHY 

43 

P5_TXP 

P2_LED0 

26 

AMCC_P0_TXP 

P2_LED1 

25 

C408 0.01UF 

AMCC_P0_TXP 

49 

P4_RXN 

P2_LED2 

24 

50 

P4_RXP 

P2_LED3 

23 

AMCC_P0_TXN 

AMCC_P0_TXN 

C409 0.01UF 

51 

P4_VDDAH 

P2_MDIN3 

103 

52 

AMCC_P0_RXP 

R262 0 

P4_TXN 

P2_MDIP3 

104 

AMCC_P0_RXP 

53 

P4_TXP 

P2_MDIN2 

106 

P2_MDIP2 

107 

AMCC_P0_RXN 

R353 0 

P2_MDIN1 

108 

AMCC_P0_RXN 

P2_MDIP1 

109 

E6122_2V5 

P2_MDIN0 

112 

P2_MDIP0 

113 

B B 

88 

R335 0 

P1_SGMII_LED_LINK 39 

R336 

INTn 

P1_LED0 

21 

P1_LED1 

20 R337 DNP 

10K 

P1_LED2 

19 

P1_SGMII_LED_RX 39 

P1_LED3 

17 

ENET_RESETn 

101 

RESETn 

P1_MDIN3 

115 

P1_SGMII_MDI3- 39 

P1_MDIP3 

116 

P1_SGMII_MDI3+ 39 

P1_MDIN2 

118 


22 MDIO_CPU_ENETSLAVE 

30 

MDIO_PHY 

P1_MDIP2 

119 


P1_MDIN1 

120 


28 

MDC_PHY/PPUEN 

P1_MDIP1 

121 


22 MDC_CPU_ENETSLAVE 


MDIO_CPU_ENETSLAVE 

P1_MDIN0 

124 

89 


E6122_2V5 

MDIO_CPU 

P1_MDIP0 

125 

MDC_CPU_ENETSLAVE 

90 

U39 

MDC_CPU 

8 

96 

C412 

VCC CS 1 

EE_CSE/EE_1K 

7 

95 

0.1uF 

NC SK 2 

EE_CLK/FD_FLOW_DIS 

6 

ORG DI 

3 

94 

EE_DIN/HD_FLOW_DIS 

5 

GND DO 4 

92 

EE_DOUT 

A AT93C66 


A 

E6122_2V5 

E6122_2V5 

98 

SW_MODE0 

99 


SW_MODE1 


R340 DNP R341 DNP R342 DNP R343 DNP 

R344 DNP R345 DNP R346 DNP R347 DNP 

Page Contents: MARVELL 88E6122 INTERFACE 

88E6122 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


2 

2 

2 

2 

9 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 



R348 1 1Watt 

E6122_2V5 

R349 4.99K 

U38B 

C413 C414 

U40 

4.7uF 

FEEDBACK_18 

10 

0.1uF 

93 

VDDO_SIM_CPU 

CONTROL_18 

11 

1 

B 

E 3 

2 

E6122_VDDAH_1V8 

D AVDDC.1 

D 

6 

AVDDC.2 

FEEDBACK_12 

14 

PHY_1V8 E6122_AVDD_1V8 E6122_CT_1V8 

CONTROL_12 

13 

9 

BCP69T1 

L6 

VDD_CORE.1 

15 

E6122_2V5 

PHY_VDD_1V2 

VDD_CORE.2 

VDDO_LED.1 

16 

18 

VDD_CORE.3 

VDDO_LED.2 

22 

27 

E6122_AVDD_1V8 

VDD_CORE.4 

32 

BLM41P750SPT 

VDD_CORE.5 

42 

C415 

C418 

VDD_CORE.6 

P0.AVDD.1 

127 

C416 

C417 

54 

0.1uF 

10uF 

VDD_CORE.7 

P0.AVDD.2 

128 

4.7uF 

0.1uF 

59 

VDD_CORE.8 

71 

VDD_CORE.9 

77 

VDD_CORE.10 

P1.AVDD.1 

117 

84 


VDD_CORE.11 

P1.AVDD.2 

122 

91 

VDD_CORE.12 

P1.AVDD.3 

123 

97 

R350 1 1Watt 

VDD_CORE.13 

R351 4.99K 

P2.AVDD.1 

105 

C419 

P2.AVDD.2 

110 

U41 

12 

0.1uF 

VDD_REG.1 

P2.AVDD.3 

111 

4.7uF 

2 

4 

C 

TAB 

C420 

1 

E6122_2V5 

B 

E 3 

C 31 

C 

E6122_2V5 

VDD_PLL.1 

VDDO_P3.1 

55 

VDDO_P3.2 

62 

VDDO_P3.3 

69 

PHY_1V2 

PHY_VDD_1V2 

VDDO_P3.4 

79 

29 

VDD_SMI_PHY 

BCP69T1 

L7 

VSS.1 

48 

VSS.2 

100 

4 

NC.4 

VSS.3 

102 

3 

NC.3 

VSS.4 

114 

BLM41P750SPT 

C421 C422 

VSS.5 

126 

C423 C424 

0.1uF 4.7uF 

EPAD 129 0.1uF 10uF 

1 

RSET 

2 

4 

C 

TAB 

R352 

4.99K 

88E6122 

EVM_2V5 E6122_2V5 

L8 

B B 

E6122_2V5 

BLM41PG750 

C425 C426 C427 C428 C429 C430 C431 C432 C433 C434 C435 C436 C437 C438 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 10uF 

E6122_AVDD_1V8 

C439 C440 C441 C442 C443 C444 C445 C446 C447 C448 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 10uF 


A 

PHY_VDD_1V2 

Title: 


Page Contents: MARVELL 88E6122 POWER 

C449 C450 C451 C452 C453 C454 C455 C456 C457 C458 C459 C460 C461 C462 C463 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 10uF 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


A-39

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


E6122_CT_1V8 

E6122_CT_1V8 

L9 

D BLM18AG601SN1 


D 

J15 

37 P1_SGMII_MDI0+ 

11 

T1+ 

12 

CT1 

1 

CT3 

37 P1_SGMII_MDI0- 

10 

T1- 


4 

T2+ 

6 

CT2 


5 

T2- 


3 

T3+ 


2 

T3- 


8 

T4+ 

C 7 

CT4 

C 


9 

T4- 

14 

LED1-A 

13 

LED1-K 

75 75 75 75 

0826-1X1T-23-F 

R358 

49.9 1% 

R360 

49.9 1% 

R361 

49.9 1% 

R362 

49.9 1% 

R363 

49.9 1% 

C465 

R364 0.1uF 

49.9 1% 

C466 

0.1uF 

C467 

0.1uF 

B B 

C468 

0.1uF 

R365 0ohm 1/4W 

C469 

C470 

C471 

C472 

0.01uF 

0.01uF 

0.01uF 

0.01uF 


A 

R366 221 

37 P1_SGMII_LED_LINK 


R367 221 

37 P1_SGMII_LED_RX 

Page Contents: ETHERNET CONNECTOR 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


1 

2 

3 

6 

4 

5 

7 

8 

17 

18 

SHLD1 

SHLD2 

16 

LED2-AK 

15 

LED2-KA 

R357 

49.9 1% 

R359 

49.9 1% 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 



CHECK POWER TOTAL 

U42 


PWR1 

2 S D 1 

3 

5 

6 

8 

1 

7 

+ C473 

GND 

VOUT 

6 

R368 

4 

2 

2.7K 

4.7uF 

D TRACK 

+ C474 

Si6475DQ 

D 

DUT_3V3 

C475 

100UF,16V 

C476 

10uF 

3 

4 

VIN 

INHIBIT 

PTH05050WAH 

ADJ 

5 

EN_DUT_3V3 

100UF,6.3V 

47K 

R370 

1K 

Q1 

FJV3109 

R369 

R371 698 1% 


R446 

10K 

C40 

1uF 


PWR2 

F_DVDD_18 

U43 

2 S D 1 

1 

GND 

VOUT 

6 

3 

5 

6 

8 

2 

TRACK 

7 

+ C477 

R372 

4 

2.7K 

C 3 

100UF,6.3V 

Si6475DQ 

VIN 

C 

C478 

C479 

4 

INHIBIT 

ADJ 

5 

4.7uF 

1K R373 

C480 

J17 

100UF,16V 10uF 

PTH05050WAH 

1 

47K R374 

Q2 

1 

EN_DUT_1V8 

2 

FJV3109 

2 

3 

R375 5.49K 1% 

3 

4 

R447 

C41 

4 

5 

F_DVDD_18_MON 

5 

10K 


6 

6 

1uF 

1A LINEAR REGULATOR 

U28 

CONN_1x6_RA 


5 

EMU_2V5 

EN 

RESET 

16 

U57 

6 


IN.1 

OUT.1 

13 

2 S D 1 

7 

IN.2 

OUT.2 

14 

3 

5 

6 

8 

C464 

4 

R355 

NC.4 

NC.17 

17 

7 

C483 

8 

2.7K 

NC.8 

NC.18 

18 

R376 

4 

10uF .1uF 

FB/NC 15 

3 

33.2K, 1% 

Si6475DQ 

GND.1 

B 1 

1K R474 

B 

GND/HSINK.1 GND/HSINK.8 

11 

+ C481 

2 


12 

10uF 

9 


19 

+ C411 

10 

47K R473 

Q11 


20 

10uF 

EN_DUT_2V5 

FJV3109 

TPS76701QPWP 

R472 

10K 


R448 

NO-POP 


1 

2 

3 

PWR4 

GND 

TRACK 

VIN 

VOUT 

6 

+ C484 

100UF,6.3V 

F_VDDD_11 

EN_DUT_1V2 

4 

INHIBIT 

ADJ 

5 

J18 

A PTH05050WAH 

1 


A 

R449 

1 

2 

2 

NO-POP 

3 

R377 24.3K 1% 

3 

4 


4 

5 

F_VDDD_11_MON 

5 

Page Contents: BLANK 

24 F_VDDD_11_MON 

6 

6 

CONN_1x6_RA 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


9 

+ 

+ 

9 

9 

9 

G 

G 

21 

PWRPLANE 

R258 

30.1K 1% 

C410 

1uF 

C485 

100UF 

C486 

10uF 

+ 

+ 

G 

A-41

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 




EMU_2V5 


C487 

R378 

U44 

10K 

R379 20K 1% 

5 

0.1uF 

SENSE1 VDD 6 

R380 

4 

CT RESET 

1 

3V3_SYS_OKAY 9 

10K 1% 

C488 

3 

R452 R451 

GND 2 

R455 R454 R453 

R450 

MR 

360 

360 

360 

360 

360 

360 

D 0.1uF 

D 

TPS3808G09DBVRG4 

Reset Threhold 0.84 Volts 

3.3VOLTS 

DS4 



GRN 


C497 

R393 

R394 

U49 

10K 

5 

11 LED_STS3V3 

LED_STS3V3 2.5VOLTS 

SENSE1 VDD 6 0.1uF 

R395 

4 


DS5 

CT RESET 

1 

10K 1% 

1.8VOLTS 

C498 

3 

GRN 

MR GND 2 

DS6 

0.1uF 


GRN 


11 LED_STS2V5 

LED_STS2V5 



11 LED_STS1V8 

LED_STS1V8 


C489 

R381 

C U45 

C 

1K 

R382 9.09K 1% 

5 


R383 

4 

CT RESET 

1 


10K 1% 

1.1 VOLTS 

C490 

3 

DS7 

MR GND 2 

GRN 

0.1uF 





11 LED_STS1V1 

LED_STS1V1 

F_VDDD_11 

C491 

R384 

F1 CORE 

R385 

U46 

10K 

DS8 

5 

GRN 


R386 

4 

CT RESET 

1 


10K 1% 

11 LED_STSF1CORE 

LED_STSF1CORE 

C492 

3 

MR GND 2 

F2 CORE 

0.1uF 


DS9 

B GRN 

B 




LED_STSF2CORE 

F1_CVDD 

11 LED_STSF2CORE 

C493 

R387 

R388 

U47 

10K 

5 


R389 

4 

CT RESET 

1 

CORE_F1_SYS_OKAY 9 

10K 1% 

C494 

3 

MR GND 2 

0.1uF 





F2_CVDD 

A C495 

R390 


A 

R391 

U48 

10K 

5 

0.1uF 

SENSE1 VDD 6 


R392 

4 

CT RESET 

1 

CORE_F2_SYS_OKAY 9 

10K 1% 

Page Contents: Power Monitors 1.1V,Core1,Core2,1.8V,2.5V,3.3V 

C496 

3 

MR GND 2 

Revision: 

0.1uF 


Size: B 

DWG NO 511222-0001 

A 



0 

0 

0 

0 


5 

5 

9 

4 

4 

3 

3 

2 

2 

1 

1 


D D 

EN_F1_CORE 

F1_CVDD 

R470 

10K 

PWR5 

11 

F1_CVDD_OUT 

INH/UVLO Vout 

5 

1 

SYNC VoSense_p 

6 


TT 

9 R396 4.75K 

+ C157 + C158 + C159 

J19 

L10 

R397 0 10 

1000UF 1000UF 1000UF C162 C166 C167 

Track 

1 

22UF 47UF 47UF 

1 

2 

2 

2 

Vin VoSense_n 

7 

3 

3 

4 

BLM41PG750 

GND 3 

4 

5 

L11 

+ C612 + C613 

8 

VoAdjust GND 4 

5 

23 F1_CVDDMON 

6 

+ C614 

330UF 100UF C615 C616 C617 

6 

220UF 

22UF 0.1UF 560PF 

PTH08T240F 

CONN_1x6_RA 

C C 

BLM41PG750 

NOTE: This circuit 

should be placed close 

R398 0 

F1_CVDDMON 23 

to Pin 8. 

R399 0 

NOTE: Place resistors 

under the C6474 CPU-1: 

B B 

F_DVDD_18 

R404 

30.9K 

R403 

37.4K 

R402 

76.8K 

R401 

154K 

R400 

348K 

R408 

10K 

R407 

10K 

R406 

10K 

R405 

10K 



to Pin 8. 

Q6 

NTA4153 

Q5 

NTA4153 

Q4 

NTA4153 

Q3 

NTA4153 

R409 

300 

D 

D 

D 

D 

G 

G 

G 

G 

S 

S 

S 

S 

F1_TVCNTL0 

F1_TVCNTL1 

F1_TVCNTL2 

F1_TVCNTL3 

R410 0 

R411 0 

R412 0 

R413 0 

F1_VCNTL0 

F1_VCNTL1 

F1_VCNTL2 

F1_VCNTL3 

20 

20 

20 

20 

JP6 

2 1 

4 3 


A 

6 5 

8 7 


Title: 

HDR_2X4 

C6474 CPU-1: CORE POWER 


Revision: 

Size: B 

DWG NO 511222-0001 

A 


Date: 

A-43

5 

5 

+ 

9 

+ 

4 

4 

1 

3 

3 

+ 

2 

2 

1 

1 


EN_F2_CORE 

F2_RBIAS 

Connect 

D at pin 

D 

R414 

3.3 sq in AGND, 

C660 

R415 

min thermal pad 

110K 1% 

C652 4700pF R416 19.6K 1% 

.1uF 

NO-POP 

U50 TPS54010PWP 

28 

C653 68pF 

R417 NO-POP 

RT 

AGND 1 

27 

DUT_3V3 

SYNC VSENSE 2 

26 

SS/ENA COMP 3 

PWRGD 4 

J20 

L12 

25 

VBIAS 

BOOT 

5 

1 

R418 

1 

2 

24 

R419 

C651 

2 

C656 

VIN5 

9.53K 1% 

3 

BLM41PG750 C655 

3 

23 

C659 

VIN4 

PH1 

6 

49.9 1% 

6800pF 

4 

4 

22 

L13 

C658 

VIN3 

PH2 

7 

5 

C657 

5 

21 

34 F2_CVDDMON 

10uF LESR 

560PF 0.1uF 

VIN2 

PH3 

8 

6 

+ C661 

10uF LESR 

0.1UF 

20 

VIN1 

PH4 

9 

R420 

6 

220UF 

PH5 

10 

C650 

866 1% 

CONN_1x6_RA 

19 

BLM41PG750 

PGND5 

PH6 

11 

0.047uF 

18 

F2_CVDD 

PGND4 

PH7 

12 

17 

PGND3 

PH8 

13 

16 

PGND2 

PH9 

14 

L14 

C 15 

1 uH 

PGND1 

C 

+ C325 + C326 

C654 1000UF 1000UF C327 C331 

C332 

1000uF 

22UF 47UF 

47UF 

PWRPAD 

29 



to BIAS. 

F2_RBIAS 

F_DVDD_18 

R425 

1M 

R424 

56.2K 

R423 

110K 

R422 

221K 

R421 

523K 

R430 

10K 

R429 

10K 

R428 

10K 

R427 

10K 



to Pin 8. 

B B 

Q7 

Q8 

Q9 

Q10 

NOTE: Place resistors 

NTA4153 NTA4153 NTA4153 NTA4153 

under the C6474 CPU-2: 

R433 0 F2_TVCNTL0 

31 F2_VCNTL0 


31 F2_VCNTL1 


31 F2_VCNTL2 


31 F2_VCNTL3 

R431 0 

D 

D 

D 

D 

G 

G 

G 

G 

S 

S 

S 

S 

JP7 

2 1 

4 3 

6 5 

8 7 

HDR_2X4 


A 


Title: 

C6474 CPU-2: CORE POWER 


Revision: 

Size: B 

DWG NO 511222-0001 

A 


Date: 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 



AMC_12V 

D D 

PWR6 

2 


IN1 OUT1 

5 

3 

INH# 

ADJ 

4 

+ C620 

100UF,6.3V 

GND 

R437 

PTH1200W 

280 1% 

1 

+ C621 

C622 

100UF,16V 10uF 

C C 

POWER INPUT 

J506 

CENTER 

SHUNT 

SLEEVE 

2.5 MM JACK 

RASM712 

B B 


A 

Title: 



POWER 12 VOLT TO 5 VOLT 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 


A-45

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 


JTAG_14_DETECT 

D F1_TRST 

D 

F1_TMS 

F1_TCLK 

F1_TDO 

F1_TDI 

EMBEDDED 

EMU 

TRST 

TMS 

TCLK 

TDO 

TDI 

EMU1 

EMU0 

3V3 DOMAIN 1V8 DOMAIN 

CPLD 

F1_TRST 

F1_TMS 

F1_TCLK 

F1_TDO 

F1_TDI 

F1_HURRICANE_DETECT 

HURRICANE 

HDR 

TRST 

TMS 

TCLK 

TDO 

TDI 

BUFFER 

TRST 

TMS 

TCLK 

TDO 

TDI 

TMS320C6474-CPU1 

F2_TRST 

TRST 

F2_TMS 

C C 

TMS 

F2_TCLK 

EMU1 

TCLK 

F2_TDO 

CBTLV 

EMU0 

TDO 

F2_TDI 

JTAG14 

TDI 

EMU1 

EMU0 

F2_TRST 

F2_TMS 

LEVEL TRANSLATOR 

F2_TCLK 

F2_TDO 

F2_TDI 

TRST 

TMS 

TCLK 

BUFFER 

TDO 

TMS320C6474-CPU2 

F2_HURRICANE_DETECT 

TDI 

B 

TRST 

B 

TMS 

TCLK 

TDO 

TDI 

HURRICANE 

HDR 

CBTLV 

EMU1 

EMU0 


A 

Title: 



JTAG TOPOLOGY 

Revision: 

Size: B 

DWG NO 511222-0001 

A 

Date: 



Appendix D 

Mechanical Information 

This appendix contains the mechanical information about the 

TMS320C6474 Mezzanine Board produced by Spectrum Digital. 

B-1


THIS DRAWING IS NOT TO SCALE 

B-2 TMS320C6474 Mezzanine EVM Board Technical Reference


B-3


B-4 TMS320C6474 Mezzanine EVM Board Technical Reference

Printed in U.S.A., November 2008 

511225-0001 Rev. A

TMS320C6474 EVM Board - Spectrum Digital Support

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