UVM: Now or Never?
UVM: Now or Never?
UVM: Now or Never?
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<strong>UVM</strong>: <strong>Now</strong> <strong>or</strong> <strong>Never</strong>?<br />
John Aynsley, Doulos<br />
Copyright © 2011-2012 by Doulos. All rights reserved. 1
<strong>UVM</strong>: <strong>Now</strong> <strong>or</strong> <strong>Never</strong>?<br />
• <strong>UVM</strong>: The Basic Facts<br />
• Options f<strong>or</strong> Interoperability and Migration<br />
• Mixed Language <strong>UVM</strong><br />
• Final Remarks
Why <strong>UVM</strong>?<br />
The big wins are<br />
• Verification quality<br />
Reusable Verification Environment<br />
• Testbench / VIP reuse<br />
• Knowhow / skills reuse<br />
Copyright © 2011-2012 by Doulos. All rights reserved.<br />
3
SystemVerilog<br />
Copyright © 2011-2012 by Doulos. All rights reserved. 4
<strong>UVM</strong><br />
<strong>UVM</strong> = Universal Verification Methodology<br />
• <strong>UVM</strong> is actively supp<strong>or</strong>ted by all maj<strong>or</strong> vend<strong>or</strong>s<br />
• Drives mutually consistent SystemVerilog implementations<br />
• One standard enhances interoperability and ecosystem growth<br />
• Increases confidence f<strong>or</strong> SystemVerilog adoption<br />
Copyright © 2011-2012 by Doulos. All rights reserved.<br />
5
<strong>UVM</strong>: The Basic Facts<br />
• Open source (Apache) SystemVerilog Base Class Library<br />
• Constrained random verification<br />
• Configurable, flexible, test benches<br />
• Mixed language vision<br />
Still need a "methodology"<br />
Copyright © 2011-2012 by Doulos. All rights reserved.<br />
6
The Big Picture<br />
A consistent spatial structure<br />
uvm_env<br />
uvm_agent<br />
Copyright © 2011-2012 by Doulos. All rights reserved.<br />
7
<strong>UVM</strong> Highlights<br />
• Separation of tests from test bench<br />
• Transaction-level communication (TLM)<br />
• Sequences<br />
• Fact<strong>or</strong>y and configuration<br />
• Message rep<strong>or</strong>ting<br />
• End-of-test mechanism<br />
• Register layer<br />
Copyright © 2011-2012 by Doulos. All rights reserved.<br />
8
<strong>UVM</strong>: <strong>Now</strong> <strong>or</strong> <strong>Never</strong>?<br />
• <strong>UVM</strong>: The Basic Facts<br />
• Options f<strong>or</strong> Interoperability and Migration<br />
• Mixed Language <strong>UVM</strong><br />
• Final Remarks
<strong>UVM</strong> versus OVM versus VMM<br />
• <strong>UVM</strong> actively developed and promoted by all vend<strong>or</strong>s<br />
• OVM and VMM are not<br />
Cadence & Ment<strong>or</strong><br />
OVM<br />
Synopsys<br />
VMM<br />
• <strong>UVM</strong> adds new features to OVM<br />
• Some OVM features now deprecated<br />
OVM 2.1.1<br />
ASI<br />
<strong>UVM</strong><br />
• Advanced features of <strong>UVM</strong> still a w<strong>or</strong>k-in-progress (run-time phasing)<br />
Copyright © 2011-2012 by Doulos. All rights reserved.<br />
10
Interoperability and Migration<br />
• OVM-to-<strong>UVM</strong> Migration<br />
www.uvmw<strong>or</strong>ld.<strong>or</strong>g - ovm2uvm_migration.pdf<br />
verificationacademy.com/verification-methodology<br />
www.doulos.com/knowhow/sysverilog/uvm/ovm-to-uvm<br />
• ASI: OVMVMM Interoperability Library<br />
verificationacademy.com/verification-methodology - ovm_vmm_interop_1_0.tgz<br />
• VMM / <strong>UVM</strong> Interoperability Kit<br />
http://www.vmmcentral.<strong>or</strong>g/cgi-bin/interopkit/req1.cgi<br />
Copyright © 2011-2012 by Doulos. All rights reserved.<br />
11
<strong>UVM</strong>: <strong>Now</strong> <strong>or</strong> <strong>Never</strong>?<br />
• <strong>UVM</strong>: The Basic Facts<br />
• Options f<strong>or</strong> Interoperability and Migration<br />
• Mixed Language <strong>UVM</strong><br />
• Final Remarks
Mixed Language Communication<br />
Wires<br />
DPI Functions<br />
Transactions<br />
Vend<strong>or</strong>-specific<br />
Vend<strong>or</strong>-specific<br />
<br />
<br />
Cadence <strong>UVM</strong>-ML<br />
Synopsys TLI<br />
<br />
Copyright © 2011-2012 by Doulos. All rights reserved.<br />
Ment<strong>or</strong> <strong>UVM</strong> Connect<br />
13
<strong>UVM</strong>: <strong>Now</strong> <strong>or</strong> <strong>Never</strong>?<br />
• <strong>UVM</strong>: The Basic Facts<br />
• Options f<strong>or</strong> Interoperability and Migration<br />
• Mixed Language <strong>UVM</strong><br />
• Final Remarks
Don't Underestimate the Learning Curve<br />
Nothing<br />
SystemVerilog f<strong>or</strong> FPGA/ASIC Design<br />
RTL and test benches<br />
Verilog<br />
Comprehensive SystemVerilog<br />
SV f<strong>or</strong> Designers<br />
Class-based<br />
verification<br />
<strong>UVM</strong> Adopter Class<br />
Copyright © 2011-2012 by Doulos. All rights reserved.<br />
15
Easier <strong>UVM</strong> Coding Idioms<br />
class my_comp extends uvm_component;<br />
`uvm_component_utils(my_comp)<br />
Pattern 1<br />
function new(string name, uvm_component parent);<br />
super.new(name, parent);<br />
endfunction<br />
function void build_phase(...);<br />
...<br />
endclass<br />
class my_tx extends uvm_sequence_item;<br />
`uvm_object_utils(my_tx)<br />
function new (string name = "");<br />
super.new(name);<br />
endfunction<br />
function string convert2string;<br />
...<br />
endclass<br />
Pattern 2a<br />
class my_seq extends uvm_sequence #(my_tx);<br />
`uvm_object_utils(my_seq)<br />
function new(string name = "");<br />
super.new(name);<br />
endfunction<br />
...<br />
task body;<br />
...<br />
endclass<br />
Pattern 2b<br />
Copyright © 2011-2012 by Doulos. All rights reserved.<br />
16
What Next?<br />
• Download <strong>UVM</strong><br />
http://www.accellera.<strong>or</strong>g/downloads/standards/uvm<br />
• First Steps with <strong>UVM</strong> video and source code examples<br />
http://www.doulos.com/knowhow/video_gallery<br />
Copyright © 2011-2012 by Doulos. All rights reserved.<br />
17
Copyright © 2011-2012 by Doulos. All rights reserved. 18
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