Model based design of Imager Pixel Matrix
Model based design of Imager Pixel Matrix
Model based design of Imager Pixel Matrix
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<strong>Model</strong> <strong>based</strong> <strong>design</strong> <strong>of</strong> <strong>Imager</strong> <strong>Pixel</strong> <strong>Matrix</strong><br />
V.Viswanathan, L.Labrak, F.Frantz, D.Navarro and I.O’connor<br />
Université de Lyon, Institut des Nanotechnologies de Lyon INL-UMR5270,<br />
CNRS, Ecole Centrale de Lyon, Ecully, France<br />
Abstract— The goal <strong>of</strong> this work is to identify a methodical<br />
analysis <strong>of</strong> pixel matrix <strong>design</strong> to achieve high level <strong>of</strong> flexibility<br />
and modularity. It will enable early stages <strong>of</strong> <strong>design</strong> space<br />
exploration using hierarchical approach. In particular, we<br />
develop generic models for imager pixel matrix in order to<br />
explore early <strong>design</strong> choices throughout the hierarchy. This<br />
modeling approach supports top-down <strong>design</strong> flows.<br />
I. INTRODUCTION<br />
<strong>Model</strong> <strong>based</strong> <strong>design</strong> (MBD) <strong>of</strong> imagers allows flexibility<br />
in the early stages <strong>of</strong> <strong>design</strong> exploration and improves product<br />
time–to-market which helps in minimizing the cost.<br />
The main focus <strong>of</strong> this research is to develop flexible<br />
models supporting a top-down (TD) <strong>design</strong> methodology, and<br />
to refine them with available physical data using a bottom-up<br />
(BU) strategy. Top-down <strong>design</strong> methodology is essential<br />
when <strong>design</strong>ing large complex systems such as imagers. It<br />
relies on a hierarchical, constraint driven system description<br />
[1].<br />
In this work, models are developed at different abstraction<br />
levels. These models will represent the behavior <strong>of</strong> the system<br />
at a specific level to predict and give the range at which the<br />
system can operate [2]. Formal abstractions are important for<br />
representing individual models. The flexibility <strong>of</strong> the models<br />
helps not only in analyzing the system but also in integration<br />
and testing.<br />
In this paper we describe the principles <strong>of</strong> our<br />
methodology along with explanation <strong>of</strong> several terminologies<br />
in section II. The specific imager IC test case is explained in<br />
section III. Segregation into abstraction levels are discussed in<br />
section IV. Finally, a conclusion with future work is presented<br />
in section V.<br />
{vijay.viswam}@ec-lyon.fr<br />
Firstly, a higher abstraction level provides information and<br />
guides <strong>design</strong> in the lower levels. This is achieved by<br />
identifying the relationship between system-level parameters<br />
and sub block (lower-level) specifications. Thus, the<br />
parameters <strong>of</strong> a given abstraction level are used as the<br />
specifications for the next (lower) level (Fig.1b). Secondly,<br />
lower abstraction level models are used to refine higher level<br />
ones in order to improve the accuracy. The <strong>design</strong> task is<br />
performed using optimization at each abstraction level. The<br />
aim is to characterize the achievable solution space according<br />
to the constraints inherited from a higher abstraction level.<br />
Other constraints such as the bounds on the parameters or<br />
constant parameters will limit the <strong>design</strong> space which leads to<br />
a reduction in solution space.<br />
This work conserves both <strong>design</strong> and modeling<br />
approaches. The BU refinement approach is carried out only<br />
in the modeling phase to improve the models to fit into the<br />
<strong>design</strong> flow for synthesis. Moreover, refinement approach is<br />
not only carried out for improving the accuracy <strong>of</strong> the model<br />
but it subsequently enables predictive synthesis on other<br />
blocks (impacted by the refined models) interacting with block<br />
under synthesis within the system.<br />
B. Parameter dependency graph<br />
A dependency graph is a directed acyclic graph<br />
representing inter-dependencies <strong>of</strong> several parameters. The<br />
order <strong>of</strong> dependency identified in such graphs support the<br />
characterization <strong>of</strong> each <strong>of</strong> the models at different levels. This<br />
characterization also supports the propagation from one level<br />
to the other. Nevertheless, dependencies are also possible<br />
between parameters at the same level, which leads to the<br />
encapsulation <strong>of</strong> dependent parameters within a single<br />
abstraction level.<br />
A. Design and <strong>Model</strong>ing<br />
Synthesis<br />
Propagation<br />
II. METHODOLOGY<br />
<strong>Model</strong> l<br />
<strong>Model</strong> l-1<br />
(a)<br />
Level l<br />
Top-Down<br />
Validation<br />
Level l+1<br />
<strong>Model</strong><br />
<strong>Model</strong><br />
Spec Parameters<br />
Design<br />
(b)<br />
<strong>Model</strong> l<br />
Refinement<br />
<strong>Model</strong> l-1<br />
Figure 1. Design and modeling<br />
Bottom-Up<br />
Performances Parameters<br />
The proposed methodology relies on hierarchical<br />
abstraction modeling and top down constraint driven <strong>design</strong>.<br />
The modeling task consist <strong>of</strong> producing models linking each<br />
abstraction level in two ways (Fig.1a).<br />
III. IMAGER IC TEST CASE<br />
An imager IC is generally composed <strong>of</strong> analog (pixel<br />
matrix, correlated double sampling or CDS, analog-digital<br />
converter or ADC) and digital (decoder, controller, image<br />
signal processor) blocks [3] as shown in Fig 4.<br />
In this application, we consider the use <strong>of</strong> a conventional<br />
Active <strong>Pixel</strong> Sensor [4] (also known as the 3T-pixel) within a<br />
1 Megapixel array. The system is characterized by the<br />
following performance metrics: maximum frames per second<br />
(FPS), dynamic range (DR) and signal-to-noise ratio (SNR).<br />
We have limited the description <strong>of</strong> the imager pixel matrix at<br />
the system level to these main characteristics to demonstrate<br />
the approach, but more details could be easily added applying<br />
the proposed approach. Each <strong>of</strong> these metrics gives rise to<br />
individual dependency graphs. However, there are also cases<br />
where some parameters are inter-dependent for one or more<br />
performances to be achieved (e.g. Integration time (T integration )).
Decoder<br />
Controller<br />
Figure 2.<br />
<strong>Pixel</strong> <strong>Matrix</strong><br />
CDS<br />
Analog to Digital converter<br />
Image signal Processor<br />
<strong>Imager</strong> blocks (overall system view)<br />
Frames per second (FPS) dependency graph<br />
The first step in identifying the parameter dependency is to<br />
decompose the system into sub-blocks. Later, all the<br />
Tcolamp<br />
Iphoto<br />
Imax<br />
<strong>Imager</strong> - FPS<br />
Tadc<br />
Imin<br />
Trowdelay<br />
Trow<br />
Tmatrix<br />
Treset<br />
Tintegration<br />
Tcds<br />
Tselect<br />
Tcol delay<br />
Area- Colamp<br />
Area- diode<br />
Area<br />
Area-<strong>Pixel</strong><br />
Parameters/Performance related to<br />
Area<br />
Input current<br />
Timing<br />
Figure 3. FPS dependency graph<br />
Transistor<br />
size<br />
Area- CDS<br />
Technology<br />
parameters which are related to FPS <strong>of</strong> each sub-block are<br />
identified with their relationship. The parameters which are<br />
considered to achieve the required FPS (performance) are<br />
individual timing parameters illustrated in Fig. 3. The critical<br />
timing <strong>of</strong> the system is set by the timing <strong>of</strong> the pixel matrix.<br />
The pixel matrix timing depends on parameters such as<br />
individual matrix row T reset , T select and T integration time where<br />
T reset , T select are the reset and select windows for resetting a<br />
pixel to the supply voltage and selecting the available output<br />
voltage from the discharge curve. T integration is the time<br />
available between the reset and select timing.<br />
Along with the main timing parameters, there are other<br />
considerations such as column delay (T coldelay ), which depends<br />
on the area <strong>of</strong> the 1 Mega pixel array to route the readout wire<br />
to the output pin <strong>of</strong> the pixel matrix. T rowdelay will take care <strong>of</strong><br />
the delay which is maintained between each row to initiate the<br />
reset and select signal. All these parameters are related to the<br />
sensor block. The current work concentrates on the pixel<br />
matrix so the other timing parameters which must be<br />
considered for other blocks such as T adc , T cds are neglected.<br />
Furthermore the parameter dependence graph is developed for<br />
D.R and SNR in the same manner as described above.<br />
IV. ABSTRACTION LEVELS AND RESULTS<br />
From the parameter dependency graph, the identification<br />
<strong>of</strong> parameters and their inter-relationships enables their<br />
encapsulation as models. These models are placed at relevant<br />
abstraction levels and their hierarchical relationships are<br />
formulated. Each abstraction level is modeled individually and<br />
optimized to reach the desired performance metrics. The<br />
models are developed ensuring constraint propagation through<br />
the different levels using information obtained from the<br />
parameter dependencies. The abstraction levels which are<br />
identified with their input and output parameters are indicated<br />
in Fig. 4. We formulate the optimization problem to find the<br />
best set <strong>of</strong> parameters that respect the system specification<br />
(DR, FPS, SNR in our example). As shown in Fig.4, the<br />
performance model is built at each level in order to use the set<br />
<strong>of</strong> output parameters in other abstraction levels.<br />
All the optimizations were performed using Matlab and<br />
run on Intel (2GB RAM, 2 GHz) machine. We used the<br />
fmincon function, to find the minimum <strong>of</strong> constrained<br />
nonlinear <strong>based</strong> optimization. This optimization minimizes the<br />
cost function at each level to achieve the desired performance.<br />
In this optimization problem and as specified previously, we<br />
limit the analysis to the scope <strong>of</strong> the aforementioned<br />
dependency graphs, and detailed analyses such as the<br />
blooming effect, effect <strong>of</strong> lens are not considered.<br />
I/PSpec:FPS, D.R, SNR<br />
O/P:<br />
O/P:<br />
System level<br />
Imax,Imin,Tinteg,Idark,Qmax,SigmaR<br />
Behavioral level<br />
Tres,Tsel,Tdelay,Tzero,Tthreshold,Tselplace,Cap,Vt<br />
Accurate behavioral level<br />
Device area,Diode area,<strong>Pixel</strong> length,Metal ,Tcoldelay,Trowdelay<br />
Physical level<br />
Level<br />
Output parameter<br />
Figure 4. Abstraction levels with input spec and output parameters<br />
V. CONCLUSION AND FUTURE WORK<br />
This ongoing work utilizes the methodology described in<br />
this paper in identifying parameter/performance pairs using a<br />
parameter dependency graph approach and segregating<br />
parameter groups into models at each abstraction level. This<br />
modeling strategy is an enabling step towards system<br />
constraint-driven synthesis [5] <strong>of</strong> imager pixel matrix. The<br />
schematic and layout <strong>of</strong> a pixel are yet to be implemented with<br />
the parameters obtained as output <strong>of</strong> accurate behavioral level<br />
to extract details and to be sent back to the higher levels to<br />
refine the model in a BU approach.<br />
REFERENCES<br />
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Perspectives for 3D integration”, 21th IEEE International Conference<br />
on Microelectronics ICM'09, Marrakech, Morocco, 2009<br />
[2] F Neelamkavil, Computer simulation and modelling. John Wiley &<br />
Sons Inc, 1987<br />
[3] M.Bigas et al, “Review <strong>of</strong> CMOS image Sensors” Microelectronic<br />
Journal,2006,37,433-451<br />
[4] E.R. Fossum, “Active <strong>Pixel</strong> Sensors(APS)- Are CCDs Dinosaurs?”<br />
Proc.SPIE vol.1900,pp.2-14, 1992<br />
[5] F. Tissafi-Drissi, I. O’Connor et al, "RUNE: Platform for automated<br />
<strong>design</strong> <strong>of</strong> integrated multi-domain systems. Application to high-speed<br />
CMOS photoreceiver front-ends," Proc. Design Automation and Test in<br />
Europe, Paris, France, 2004<br />
Top-down flow