Model based design of Imager Pixel Matrix

Model based design of Imager Pixel Matrix
V.Viswanathan, L.Labrak, F.Frantz, D.Navarro and I.O’connor
Université de Lyon, Institut des Nanotechnologies de Lyon INL-UMR5270,
CNRS, Ecole Centrale de Lyon, Ecully, France
Abstract— The goal of this work is to identify a methodical
analysis of pixel matrix design to achieve high level of flexibility
and modularity. It will enable early stages of design space
exploration using hierarchical approach. In particular, we
develop generic models for imager pixel matrix in order to
explore early design choices throughout the hierarchy. This
modeling approach supports top-down design flows.
I. INTRODUCTION
Model based design (MBD) of imagers allows flexibility
in the early stages of design exploration and improves product
time–to-market which helps in minimizing the cost.
The main focus of this research is to develop flexible
models supporting a top-down (TD) design methodology, and
to refine them with available physical data using a bottom-up
(BU) strategy. Top-down design methodology is essential
when designing large complex systems such as imagers. It
relies on a hierarchical, constraint driven system description
[1].
In this work, models are developed at different abstraction
levels. These models will represent the behavior of the system
at a specific level to predict and give the range at which the
system can operate [2]. Formal abstractions are important for
representing individual models. The flexibility of the models
helps not only in analyzing the system but also in integration
and testing.
In this paper we describe the principles of our
methodology along with explanation of several terminologies
in section II. The specific imager IC test case is explained in
section III. Segregation into abstraction levels are discussed in
section IV. Finally, a conclusion with future work is presented
in section V.
{vijay.viswam}@ec-lyon.fr
Firstly, a higher abstraction level provides information and
guides design in the lower levels. This is achieved by
identifying the relationship between system-level parameters
and sub block (lower-level) specifications. Thus, the
parameters of a given abstraction level are used as the
specifications for the next (lower) level (Fig.1b). Secondly,
lower abstraction level models are used to refine higher level
ones in order to improve the accuracy. The design task is
performed using optimization at each abstraction level. The
aim is to characterize the achievable solution space according
to the constraints inherited from a higher abstraction level.
Other constraints such as the bounds on the parameters or
constant parameters will limit the design space which leads to
a reduction in solution space.
This work conserves both design and modeling
approaches. The BU refinement approach is carried out only
in the modeling phase to improve the models to fit into the
design flow for synthesis. Moreover, refinement approach is
not only carried out for improving the accuracy of the model
but it subsequently enables predictive synthesis on other
blocks (impacted by the refined models) interacting with block
under synthesis within the system.
B. Parameter dependency graph
A dependency graph is a directed acyclic graph
representing inter-dependencies of several parameters. The
order of dependency identified in such graphs support the
characterization of each of the models at different levels. This
characterization also supports the propagation from one level
to the other. Nevertheless, dependencies are also possible
between parameters at the same level, which leads to the
encapsulation of dependent parameters within a single
abstraction level.
A. Design and Modeling
Synthesis
Propagation
II. METHODOLOGY
Model l
Model l-1
(a)
Level l
Top-Down
Validation
Level l+1
Model
Model
Spec Parameters
Design
(b)
Model l
Refinement
Model l-1
Figure 1. Design and modeling
Bottom-Up
Performances Parameters
The proposed methodology relies on hierarchical
abstraction modeling and top down constraint driven design.
The modeling task consist of producing models linking each
abstraction level in two ways (Fig.1a).
III. IMAGER IC TEST CASE
An imager IC is generally composed of analog (pixel
matrix, correlated double sampling or CDS, analog-digital
converter or ADC) and digital (decoder, controller, image
signal processor) blocks [3] as shown in Fig 4.
In this application, we consider the use of a conventional
Active Pixel Sensor [4] (also known as the 3T-pixel) within a
1 Megapixel array. The system is characterized by the
following performance metrics: maximum frames per second
(FPS), dynamic range (DR) and signal-to-noise ratio (SNR).
We have limited the description of the imager pixel matrix at
the system level to these main characteristics to demonstrate
the approach, but more details could be easily added applying
the proposed approach. Each of these metrics gives rise to
individual dependency graphs. However, there are also cases
where some parameters are inter-dependent for one or more
performances to be achieved (e.g. Integration time (T integration )).

Decoder
Controller
Figure 2.
Pixel Matrix
CDS
Analog to Digital converter
Image signal Processor
Imager blocks (overall system view)
Frames per second (FPS) dependency graph
The first step in identifying the parameter dependency is to
decompose the system into sub-blocks. Later, all the
Tcolamp
Iphoto
Imax
Imager - FPS
Tadc
Imin
Trowdelay
Trow
Tmatrix
Treset
Tintegration
Tcds
Tselect
Tcol delay
Area- Colamp
Area- diode
Area
Area-Pixel
Parameters/Performance related to
Area
Input current
Timing
Figure 3. FPS dependency graph
Transistor
size
Area- CDS
Technology
parameters which are related to FPS of each sub-block are
identified with their relationship. The parameters which are
considered to achieve the required FPS (performance) are
individual timing parameters illustrated in Fig. 3. The critical
timing of the system is set by the timing of the pixel matrix.
The pixel matrix timing depends on parameters such as
individual matrix row T reset , T select and T integration time where
T reset , T select are the reset and select windows for resetting a
pixel to the supply voltage and selecting the available output
voltage from the discharge curve. T integration is the time
available between the reset and select timing.
Along with the main timing parameters, there are other
considerations such as column delay (T coldelay ), which depends
on the area of the 1 Mega pixel array to route the readout wire
to the output pin of the pixel matrix. T rowdelay will take care of
the delay which is maintained between each row to initiate the
reset and select signal. All these parameters are related to the
sensor block. The current work concentrates on the pixel
matrix so the other timing parameters which must be
considered for other blocks such as T adc , T cds are neglected.
Furthermore the parameter dependence graph is developed for
D.R and SNR in the same manner as described above.
IV. ABSTRACTION LEVELS AND RESULTS
From the parameter dependency graph, the identification
of parameters and their inter-relationships enables their
encapsulation as models. These models are placed at relevant
abstraction levels and their hierarchical relationships are
formulated. Each abstraction level is modeled individually and
optimized to reach the desired performance metrics. The
models are developed ensuring constraint propagation through
the different levels using information obtained from the
parameter dependencies. The abstraction levels which are
identified with their input and output parameters are indicated
in Fig. 4. We formulate the optimization problem to find the
best set of parameters that respect the system specification
(DR, FPS, SNR in our example). As shown in Fig.4, the
performance model is built at each level in order to use the set
of output parameters in other abstraction levels.
All the optimizations were performed using Matlab and
run on Intel (2GB RAM, 2 GHz) machine. We used the
fmincon function, to find the minimum of constrained
nonlinear based optimization. This optimization minimizes the
cost function at each level to achieve the desired performance.
In this optimization problem and as specified previously, we
limit the analysis to the scope of the aforementioned
dependency graphs, and detailed analyses such as the
blooming effect, effect of lens are not considered.
I/PSpec:FPS, D.R, SNR
O/P:
O/P:
System level
Imax,Imin,Tinteg,Idark,Qmax,SigmaR
Behavioral level
Tres,Tsel,Tdelay,Tzero,Tthreshold,Tselplace,Cap,Vt
Accurate behavioral level
Device area,Diode area,Pixel length,Metal ,Tcoldelay,Trowdelay
Physical level
Level
Output parameter
Figure 4. Abstraction levels with input spec and output parameters
V. CONCLUSION AND FUTURE WORK
This ongoing work utilizes the methodology described in
this paper in identifying parameter/performance pairs using a
parameter dependency graph approach and segregating
parameter groups into models at each abstraction level. This
modeling strategy is an enabling step towards system
constraint-driven synthesis [5] of imager pixel matrix. The
schematic and layout of a pixel are yet to be implemented with
the parameters obtained as output of accurate behavioral level
to extract details and to be sent back to the higher levels to
refine the model in a BU approach.
REFERENCES
[1] L.Labrak, I.O’Connor, “Heterogeneous System Design Platform and
Perspectives for 3D integration”, 21th IEEE International Conference
on Microelectronics ICM'09, Marrakech, Morocco, 2009
[2] F Neelamkavil, Computer simulation and modelling. John Wiley &
Sons Inc, 1987
[3] M.Bigas et al, “Review of CMOS image Sensors” Microelectronic
Journal,2006,37,433-451
[4] E.R. Fossum, “Active Pixel Sensors(APS)- Are CCDs Dinosaurs?”
Proc.SPIE vol.1900,pp.2-14, 1992
[5] F. Tissafi-Drissi, I. O’Connor et al, "RUNE: Platform for automated
design of integrated multi-domain systems. Application to high-speed
CMOS photoreceiver front-ends," Proc. Design Automation and Test in
Europe, Paris, France, 2004
Top-down flow